diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-25 17:24:51 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-25 17:24:51 -0800 |
| commit | 2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1 (patch) | |
| tree | a430dd7bcb89dc623312ad20731acde995f1368a | |
| parent | 70dbb12e95ec7585c68cb3ceae971688915021e3 (diff) | |
| parent | ac6f0825e582f2216a582c9edf0cee7bfe347ba6 (diff) | |
| download | lwn-2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1.tar.gz lwn-2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1.zip | |
Merge tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"No core changes this time.
New drivers:
- Xlinix Versal pin control driver
- Ocelot LAN969x pin control driver
- T-Head TH1520 RISC-V SoC pin control driver
- Qualcomm SM8750, IPQ5424, QCS8300, SAR2130P and QCS615 SoC pin
control drivers
- Qualcomm SM8750 LPASS (low power audio subsystem) pin control
driver
- Qualcomm PM8937 mixsig IC pin control support, GPIO and MPP
(multi-purpose-pin)
- Samsung Exynos8895 and Exynos9810 SoC pin control driver
- SpacemiT K1 SoC pin control driver
- Airhoa EN7581 IC pin control driver
Improvements:
- The Renesas subdriver now supports schmitt-trigger and open drain
pin configurations if the hardware supports it
- Support GPIOF and GPIOG banks in the Aspeed G6 SoC
- Support the DSW community in the Intel Elkhartlake SoC"
* tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
pinctrl: airoha: Use unsigned long for bit search
pinctrl: k210: Undef K210_PC_DEFAULT
pinctrl: qcom: spmi: fix debugfs drive strength
pinctrl: qcom: Add sm8750 pinctrl driver
dt-bindings: pinctrl: qcom: Add sm8750 pinctrl
pinctrl: cy8c95x0: remove unneeded goto labels
pinctrl: cy8c95x0: embed iterator to the for-loop
pinctrl: cy8c95x0: Use temporary variable for struct device
pinctrl: cy8c95x0: use flexible sleeping in reset function
pinctrl: cy8c95x0: switch to using devm_regulator_get_enable()
pinctrl: cy8c95x0: Use 2-argument strscpy()
dt-bindings: pinctrl: sx150xq: allow gpio line naming
pinctrl: single: add marvell,pxa1908-padconf compatible
dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
dt-bindings: pinctrl: correct typo of description for cv1800
pinctrl: qcom: spmi-mpp: Add PM8937 compatible
dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible
pinctrl: qcom-pmic-gpio: add support for PM8937
dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937
pinctrl: Use of_property_present() for non-boolean properties
...
161 files changed, 15902 insertions, 1170 deletions
diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml new file mode 100644 index 000000000000..67c449d804c2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Chip SCU Controller for EN7581 SoC + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The airoha chip-scu block provides a configuration interface for clock, + io-muxing and other functionalities used by multiple controllers (e.g. clock, + pinctrl, ecc) on EN7581 SoC. + +properties: + compatible: + items: + - enum: + - airoha,en7581-chip-scu + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml new file mode 100644 index 000000000000..4a81ed82ef34 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 GPIO System Controller + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + Airoha EN7581 SoC GPIO system controller which provided a register map + for controlling the GPIO, pins and PWM of the SoC. + +properties: + compatible: + items: + - const: airoha,en7581-gpio-sysctl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + pinctrl: + type: object + $ref: /schemas/pinctrl/airoha,en7581-pinctrl.yaml + description: + Child node definition for EN7581 Pin controller + + pwm: + type: object + $ref: /schemas/pwm/airoha,en7581-pwm.yaml + description: + Child node definition for EN7581 PWM controller + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + system-controller@1fbf0200 { + compatible = "airoha,en7581-gpio-sysctl", "syscon", "simple-mfd"; + reg = <0x1fbf0200 0xc0>; + + pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; + + pwm { + compatible = "airoha,en7581-pwm"; + + #pwm-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file mode 100644 index 000000000000..b2601d698dcd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -0,0 +1,400 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 Pin Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha's EN7581 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,en7581-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3, + pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1, pcie_reset2] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml index 412bbcc276f3..c954761e0150 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -46,7 +46,7 @@ patternProperties: - const: gpio gpio-line-names: - minItems: 86 # AXG + minItems: 83 # Meson8b maxItems: 120 # Meson8 unevaluatedProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml new file mode 100644 index 000000000000..0b462eb6dfe1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Pin Controller + +maintainers: + - Ze Huang <18771902331@163.com> + +description: + The Canaan Kendryte K230 platform includes 64 IO pins, each capable of + multiplexing up to 5 different functions. Pin function configuration is + performed on a per-pin basis. + +properties: + compatible: + const: canaan,k230-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-cfg$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate enable/disable, + slew-rate, drive strength. + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in + the node apply to. This should be set with the macro + 'K230_PINMUX(pin, mode)' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + minimum: 0 + maximum: 15 + + input-enable: true + + output-enable: true + + input-schmitt-enable: true + + slew-rate: + description: | + slew rate control enable + 0: disable + 1: enable + + enum: [0, 1] + + power-source: + description: | + Specifies the power source voltage for the IO bank that the + pin belongs to. Each bank of IO pins operate at a specific, + fixed voltage levels. Incorrect voltage configuration can + damage the chip. The defined constants represent the + possible voltage configurations: + + - K230_MSC_3V3 (value 0): 3.3V power supply + - K230_MSC_1V8 (value 1): 1.8V power supply + + The following banks have the corresponding voltage + configurations: + + - bank IO0 to IO1: Fixed at 1.8V + - bank IO2 to IO13: Fixed at 1.8V + - bank IO14 to IO25: Fixed at 1.8V + - bank IO26 to IO37: Fixed at 1.8V + - bank IO38 to IO49: Fixed at 1.8V + - bank IO50 to IO61: Fixed at 3.3V + - bank IO62 to IO63: Fixed at 1.8V + + enum: [0, 1] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x91105000 0x100>; + + uart2-pins { + uart2-pins-cfg { + pinmux = <0x503>, /* uart2 txd */ + <0x603>; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = <1>; + input-enable; + output-enable; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt deleted file mode 100644 index c083dfd25db9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Freescale IMX35 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx35-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx35 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) -PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE_CMOS (0 << 3) -PAD_CTL_ODE_OPENDRAIN (1 << 3) -PAD_CTL_DSE_NOMINAL (0 << 1) -PAD_CTL_DSE_HIGH (1 << 1) -PAD_CTL_DSE_MAX (2 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx35-pinfunc.h in device tree source folder for all available -imx35 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml index 906b264a9e3c..265c43ab76f4 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale IMX6UL IOMUX Controller +title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller maintainers: - Dong Aisheng <aisheng.dong@nxp.com> @@ -18,9 +18,21 @@ allOf: properties: compatible: - enum: - - fsl,imx6ul-iomuxc - - fsl,imx6ull-iomuxc-snvs + oneOf: + - enum: + - fsl,imx35-iomuxc + - fsl,imx51-iomuxc + - fsl,imx53-iomuxc + - fsl,imx6dl-iomuxc + - fsl,imx6q-iomuxc + - fsl,imx6sl-iomuxc + - fsl,imx6sll-iomuxc + - fsl,imx6sx-iomuxc + - fsl,imx6ul-iomuxc + - fsl,imx6ull-iomuxc-snvs + - items: + - const: fsl,imx50-iomuxc + - const: fsl,imx53-iomuxc reg: maxItems: 1 @@ -39,9 +51,9 @@ patternProperties: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer + be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX6UL Reference Manual for detailed CONFIG settings. + refer to matching i.MX Reference Manual for detailed CONFIG settings. $ref: /schemas/types.yaml#/definitions/uint32-matrix items: items: @@ -56,7 +68,41 @@ patternProperties: - description: | "input_val" indicates the select input value to be applied. - description: | - "pad_setting" indicates the pad configuration value to be applied: + "pad_setting" indicates the pad configuration value to be applied. + Common i.MX35 + PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) + PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE_CMOS (0 << 3) + PAD_CTL_ODE_OPENDRAIN (1 << 3) + PAD_CTL_DSE_NOMINAL (0 << 1) + PAD_CTL_DSE_HIGH (1 << 1) + PAD_CTL_DSE_MAX (2 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX50/i.MX51/i.MX53 bits + PAD_CTL_HVE (1 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE (1 << 3) + PAD_CTL_DSE_LOW (0 << 1) + PAD_CTL_DSE_MED (1 << 1) + PAD_CTL_DSE_HIGH (2 << 1) + PAD_CTL_DSE_MAX (3 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX6 bits PAD_CTL_HYS (1 << 16) PAD_CTL_PUS_100K_DOWN (0 << 14) PAD_CTL_PUS_47K_UP (1 << 14) @@ -69,6 +115,11 @@ patternProperties: PAD_CTL_SPEED_MED (1 << 6) PAD_CTL_SPEED_HIGH (3 << 6) PAD_CTL_DSE_DISABLE (0 << 3) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + i.MX6SL/MX6SLL specific bits + PAD_CTL_LVE (1 << 22) (MX6SL/SLL only) + i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits PAD_CTL_DSE_260ohm (1 << 3) PAD_CTL_DSE_130ohm (2 << 3) PAD_CTL_DSE_87ohm (3 << 3) @@ -76,8 +127,14 @@ patternProperties: PAD_CTL_DSE_52ohm (5 << 3) PAD_CTL_DSE_43ohm (6 << 3) PAD_CTL_DSE_37ohm (7 << 3) - PAD_CTL_SRE_FAST (1 << 0) - PAD_CTL_SRE_SLOW (0 << 0) + i.MX6DL/i.MX6Q/i.MX6SL specific bits + PAD_CTL_DSE_240ohm (1 << 3) + PAD_CTL_DSE_120ohm (2 << 3) + PAD_CTL_DSE_80ohm (3 << 3) + PAD_CTL_DSE_60ohm (4 << 3) + PAD_CTL_DSE_48ohm (5 << 3) + PAD_CTL_DSE_40ohm (6 << 3) + PAD_CTL_DSE_34ohm (7 << 3) required: - fsl,pins @@ -114,3 +171,14 @@ examples: >; }; }; + - | + iomuxc_mx6q: pinctrl@20e0000 { + compatible = "fsl,imx6q-iomuxc"; + reg = <0x20e0000 0x4000>; + + pinctrl_uart4: uart4grp { + fsl,pins = + <0x288 0x658 0x000 0x3 0x0 0x140>, + <0x28c 0x65c 0x938 0x3 0x3 0x140>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt deleted file mode 100644 index 6da01d619d33..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX50 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx50-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx50 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx50-pinfunc.h in device tree source folder for all available -imx50 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt deleted file mode 100644 index 4d1408fcc99c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX51 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx51-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx51 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx51-pinfunc.h in device tree source folder for all available -imx51 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt deleted file mode 100644 index 25dcb77cfaf7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX53 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx53-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx53 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx53-pinfunc.h in device tree source folder for all available -imx53 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt deleted file mode 100644 index 0ac5bee87505..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6 DualLite/Solo IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6dl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6dl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6dl-pinfunc.h in device tree source folder for all available -imx6dl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index 546610cf2ae7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6Q IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6q-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6q datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6q-pinfunc.h in device tree source folder for all available -imx6q PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt deleted file mode 100644 index e5f6d1f065a4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Freescale IMX6 SoloLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6sl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sl-pinfunc.h in device tree source folder for all available -imx6sl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt deleted file mode 100644 index 175e8939a301..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Freescale i.MX6 SLL IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sll-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6SLL - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sll-pinfunc.h in device tree source folder for all available -imx6sll PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt deleted file mode 100644 index b1b595220f1b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale i.MX6 SoloX IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sx-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml new file mode 100644 index 000000000000..e07f4723de17 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mcp23s08.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip I/O expander with serial interface (I2C/SPI) + +maintainers: + - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> + +description: + Microchip MCP23008, MCP23017, MCP23S08, MCP23S17, MCP23S18 GPIO expander + chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - microchip,mcp23s08 + - microchip,mcp23s17 + - microchip,mcp23s18 + - microchip,mcp23008 + - microchip,mcp23017 + - microchip,mcp23018 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO specifier for active-low reset pin. + maxItems: 1 + + microchip,spi-present-mask: + description: + Multiple SPI chips can share the same SPI chipselect. Set a bit in + bit0-7 in this mask to 1 if there is a chip connected with the + corresponding spi address set. For example if you have a chip with + address 3 connected, you have to set bit3 to 1, which is 0x08. mcp23s08 + chip variant only supports bits 0-3. It is not possible to mix mcp23s08 + and mcp23s17 on the same chipselect. Set at least one bit to 1 for SPI + chips. + $ref: /schemas/types.yaml#/definitions/uint8 + + microchip,irq-mirror: + type: boolean + description: + Sets the mirror flag in the IOCON register. Devices with two interrupt + outputs (these are the devices ending with 17 and those that have 16 IOs) + have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These chips + have two different interrupt outputs One for bank 1 and another for + bank 2. If irq-mirror is set, both interrupts are generated regardless of + the bank that an input change occurred on. If it is not set,the interrupt + are only generated for the bank they belong to. + + microchip,irq-active-high: + type: boolean + description: + Sets the INTPOL flag in the IOCON register.This configures the IRQ output + polarity as active high. + + drive-open-drain: + type: boolean + description: + Sets the ODR flag in the IOCON register. This configures the IRQ output as + open drain active low. + + pinmux: + type: object + properties: + pins: + description: + The list of GPIO pins controlled by this node. Each pin name + corresponds to a physical pin on the GPIO expander. + items: + pattern: '^gpio([0-9]|[1][0-5])$' + maxItems: 16 + + bias-pull-up: + type: boolean + description: + Configures pull-up resistors for the GPIO pins. Absence of this + property will leave the configuration in its default state. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + gpio@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + microchip,irq-mirror; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>, <&gpiopullups>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + gpiopullups: pinmux { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + bias-pull-up; + }; + }; + }; + + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + gpio@0 { + compatible = "microchip,mcp23s17"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + microchip,spi-present-mask = /bits/ 8 <0x01>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml index dbb3e1bd58c1..31bc30a81752 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -12,14 +12,24 @@ maintainers: properties: compatible: - enum: - - microchip,lan966x-pinctrl - - microchip,sparx5-pinctrl - - mscc,jaguar2-pinctrl - - mscc,luton-pinctrl - - mscc,ocelot-pinctrl - - mscc,serval-pinctrl - - mscc,servalt-pinctrl + oneOf: + - enum: + - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + - items: + - enum: + - microchip,lan9698-pinctrl + - microchip,lan9696-pinctrl + - microchip,lan9694-pinctrl + - microchip,lan9693-pinctrl + - microchip,lan9692-pinctrl + - const: microchip,lan9691-pinctrl reg: items: @@ -85,6 +95,7 @@ allOf: contains: enum: - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl - microchip,sparx5-pinctrl then: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt deleted file mode 100644 index 2fa5edac7a35..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ /dev/null @@ -1,148 +0,0 @@ -Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for -8-/16-bit I/O expander with serial interface (I2C/SPI) - -Required properties: -- compatible : Should be - - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version - - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version - - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or - - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip - - - "microchip,mcp23s08" for 8 GPIO SPI version - - "microchip,mcp23s17" for 16 GPIO SPI version - - "microchip,mcp23s18" for 16 GPIO SPI version - - "microchip,mcp23008" for 8 GPIO I2C version or - - "microchip,mcp23017" for 16 GPIO I2C version of the chip - - "microchip,mcp23018" for 16 GPIO I2C version - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags as described in - 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by - 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW). -- gpio-controller : Marks the device node as a GPIO controller. -- reg : For an address on its bus. I2C uses this a the I2C address of the chip. - SPI uses this to specify the chipselect line which the chip is - connected to. The driver and the SPI variant of the chip support - multiple chips on the same chipselect. Have a look at - microchip,spi-present-mask below. - -Required device specific properties (only for SPI chips): -- mcp,spi-present-mask (DEPRECATED) -- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI - chips - as the name suggests. Multiple SPI chips can share the same - SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a - chip connected with the corresponding spi address set. For example if - you have a chip with address 3 connected, you have to set bit3 to 1, - which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not - possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at - least one bit to 1 for SPI chips. - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- spi-max-frequency = The maximum frequency this chip is able to handle - -Optional properties: -- #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as a interrupt controller. -- drive-open-drain: Sets the ODR flag in the IOCON register. This configures - the IRQ output as open drain active low. -- reset-gpios: Corresponds to the active-low RESET# pin for the chip - -Optional device specific properties: -- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices - with two interrupt outputs (these are the devices ending with 17 and - those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - IO 8-15 are bank 2. These chips have two different interrupt outputs: - One for bank 1 and another for bank 2. If irq-mirror is set, both - interrupts are generated regardless of the bank that an input change - occurred on. If it is not set, the interrupt are only generated for the - bank they belong to. - On devices with only one interrupt output this property is useless. -- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This - configures the IRQ output polarity as active high. - -Example I2C (with interrupt): -gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells=<2>; - microchip,irq-mirror; -}; - -Example SPI: -gpiom1: gpio@0 { - compatible = "microchip,mcp23s17"; - gpio-controller; - #gpio-cells = <2>; - microchip,spi-present-mask = <0x01>; - reg = <0>; - spi-max-frequency = <1000000>; -}; - -Pull-up configuration -===================== - -If pins are used as output, they can also be configured with pull-ups. This is -done with pinctrl. - -Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt> -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>. -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - <pinctrl-bindings.txt>. - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0 ... gpio7 for the devices with 8 GPIO pins and - gpio0 ... gpio15 for the devices with 16 GPIO pins. - -Optional properties: -------------------- -The following optional property is defined in the pinmux DT binding document -<pinctrl-bindings.txt>. Absence of this property will leave the configuration -in its default state. - bias-pull-up - -Example with pinctrl to pull-up output pins: -gpio21: gpio@21 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <0x2>; - reg = <0x21>; - interrupt-parent = <&socgpio>; - interrupts = <0x17 0x8>; - interrupt-names = "mcp23017@21 irq"; - interrupt-controller; - #interrupt-cells = <0x2>; - microchip,irq-mirror; - pinctrl-names = "default"; - pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - - gpio21pullups: pinmux { - pins = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15"; - bias-pull-up; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index e02595316c9f..f83dbf32ad18 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -33,6 +33,10 @@ properties: - ti,omap5-padconf - ti,j7200-padconf - const: pinctrl-single + - items: + - enum: + - marvell,pxa1908-padconf + - const: pinconf-single reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml new file mode 100644 index 000000000000..5e64a232fc7a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5424 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5424-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 25 + + gpio-line-names: + maxItems: 50 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5424-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5424-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5424-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9])$" + minItems: 1 + maxItems: 50 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1, + cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest, + gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11, + mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk, + pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, + pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11, + pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk, + qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd, + sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1, + wci_txd, wci_rxd, wsi_clk, wsi_data ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5424-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 50>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + uart1_pins: uart1-state { + pins = "gpio43", "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index c1b799167d81..055cea5452eb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -48,6 +48,7 @@ properties: - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio + - qcom,pm8937-gpio - qcom,pm8941-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio @@ -184,6 +185,7 @@ allOf: - qcom,pm8226-gpio - qcom,pm8350b-gpio - qcom,pm8550ve-gpio + - qcom,pm8937-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio @@ -468,6 +470,7 @@ $defs: - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 + - gpio1-gpio8 for pm8937 (hole on gpio3, gpio4 and gpio6) - gpio1-gpio36 for pm8941 - gpio1-gpio8 for pm8950 (hole on gpio3) - gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 43146709e204..9364ae05f3e6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -22,6 +22,7 @@ properties: - qcom,pm8226-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp + - qcom,pm8937-mpp - qcom,pm8941-mpp - qcom,pm8950-mpp - qcom,pmi8950-mpp @@ -92,6 +93,7 @@ $defs: this subnode. Valid pins are - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 + - mpp1-mpp4 for pm8937 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml new file mode 100644 index 000000000000..1ce4b5df584a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS615 TLMM block + +maintainers: + - Lijuan Gao <quic_lijuang@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs615-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: east + - const: west + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 62 + + gpio-line-names: + maxItems: 123 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs615-tlmm-state" + - type: object + patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs615-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs615-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_gp, + copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, + edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc_gp, + gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, + mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out, + pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pll_bist, + pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio, + qlink_enable, qlink_request, qspi, qup0, qup1, rgmii, + sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, usb0_hs, + usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, wsa_clk, + wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3000000 { + compatible = "qcom,qcs615-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03c00000 0x300000>; + reg-names = "east", "west", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup3-uart2-state { + pins ="gpio16", "gpio17"; + function = "qup0"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml new file mode 100644 index 000000000000..bb0d7132886a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 TLMM block + +maintainers: + - Jingyi Wang <quic_jingyw@quicinc.com> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm QCS8300 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 67 + + gpio-line-names: + maxItems: 133 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs8300-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs8300-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs8300-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" + - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest_char, atest_usb2, audio_ref, cam_mclk, + cci_async, cci_i2c_scl, cci_i2c_sda, cci_timer, cri_trng, + dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, + edp0_hot, edp0_lcd, edp1_lcd, egpio, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux, + emac0_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5, + gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, jitter_bist, + mdp0_vsync0, mdp0_vsync1, mdp0_vsync3, mdp0_vsync6, mdp0_vsync7, + mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, + mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, + pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, + qdss_cti, qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, + qup0_se4, qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, + qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, + qup2_se0, sailss_emac0, sailss_ospi, sail_top, sgmii_phy, + tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, usb2phy_ac, + vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,qcs8300-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio43", "gpio44"; + function = "qup0_se7"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml index e9abbf2c0689..749dbc563ac5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -17,7 +17,13 @@ allOf: properties: compatible: - const: qcom,sa8775p-tlmm + oneOf: + - items: + - enum: + - qcom,sa8255p-tlmm + - const: qcom,sa8775p-tlmm + - items: + - const: qcom,sa8775p-tlmm reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml new file mode 100644 index 000000000000..b388380b1ce0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SAR2130P TLMM block + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sar2130p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sar2130p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sar2130p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02, + atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk1, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkreqn, + pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, qup0, + qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup10, + qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sar2130p-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 156>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml index db7214362301..e90a5274647d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml @@ -16,7 +16,11 @@ description: properties: compatible: - const: qcom,sm8650-lpass-lpi-pinctrl + oneOf: + - const: qcom,sm8650-lpass-lpi-pinctrl + - items: + - const: qcom,sm8750-lpass-lpi-pinctrl + - const: qcom,sm8650-lpass-lpi-pinctrl reg: items: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml new file mode 100644 index 000000000000..7aecc97745a8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8750-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8750 TLMM block + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8750 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8750-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 108 + + gpio-line-names: + maxItems: 215 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8750-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8750-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8750-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, + sd_write_protect, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + tsense_pwm4, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8750-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 216>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio60"; + function = "qup1_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio61"; + function = "qup1_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 56d90c8e1fa3..a1805b6e3f63 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -119,6 +119,10 @@ additionalProperties: bias-disable: true bias-pull-down: true bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + drive-open-drain: true + drive-push-pull: true renesas,output-impedance: description: Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 4dfb49b0e07f..68ed714eb0a1 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -42,10 +42,13 @@ properties: - samsung,exynos5433-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos9810-wakeup-eint + - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint - const: samsung,exynos7-wakeup-eint @@ -91,14 +94,18 @@ allOf: - if: properties: compatible: - # Match without "contains", to skip newer variants which are still - # compatible with samsung,exynos7-wakeup-eint - enum: - - samsung,s5pv210-wakeup-eint - - samsung,exynos4210-wakeup-eint - - samsung,exynos5433-wakeup-eint - - samsung,exynos7-wakeup-eint - - samsung,exynos7885-wakeup-eint + oneOf: + # Match without "contains", to skip newer variants which are still + # compatible with samsung,exynos7-wakeup-eint + - enum: + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,s5pv210-wakeup-eint + - contains: + enum: + - samsung,exynos5433-wakeup-eint + - samsung,exynos7885-wakeup-eint + - samsung,exynos8895-wakeup-eint then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 242dd13c276b..5296a9e4faae 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -53,6 +53,9 @@ properties: - samsung,exynos7-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8895-pinctrl + - samsung,exynos9810-pinctrl + - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml index 4214d7311f6b..39d7dad3313b 100644 --- a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -26,6 +26,10 @@ properties: reg: maxItems: 1 + gpio-line-names: + minItems: 5 + maxItems: 17 + interrupts: maxItems: 1 @@ -88,6 +92,45 @@ required: allOf: - $ref: pinctrl.yaml# - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + - semtech,sx1507q + then: + properties: + gpio-line-names: + minItems: 5 + maxItems: 5 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + - semtech,sx1508q + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + - semtech,sx1509q + then: + properties: + gpio-line-names: + minItems: 17 + maxItems: 17 + - if: not: properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml index 1e6a55afe26a..feb4785a3fac 100644 --- a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml @@ -58,7 +58,7 @@ patternProperties: pinmux: description: | The list of GPIOs and their mux settings that properties in the - node apply to. This should be set using the GPIOMUX or GPIOMUX2 + node apply to. This should be set using the PINMUX or PINMUX2 macro. bias-pull-up: diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml new file mode 100644 index 000000000000..b01ecd83b71b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/spacemit,k1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC Pin Controller + +maintainers: + - Yixun Lan <dlan@gentoo.org> + +properties: + compatible: + const: spacemit,k1-pinctrl + + reg: + items: + - description: pinctrl io memory base + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + drive strength, input schmitt trigger, slew rate, power source. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the K1_PADCONF macro to + construct the value. + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: + description: | + typical value for selecting bias pull up or strong pull up. + 0: normal bias pull up + 1: strong bias pull up + enum: [ 0, 1 ] + + drive-strength: + description: | + typical current when output high level. + 1.8V output: 11, 21, 32, 42 (mA) + 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) + + input-schmitt: + description: | + typical threshold for schmitt trigger. + 0: buffer mode + 1: trigger mode + 2, 3: trigger mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + power-source: + description: external power supplies at 1.8v or 3.3v. + enum: [ 1800, 3300 ] + + slew-rate: + description: | + slew rate for output buffer. + 0: disable it + 1: enable it (via bundled value from drive strength) + 2: slow speed 0 + 3: slow speed 1 + 4: medium speed + 5: fast speed + enum: [ 0, 1, 2, 3, 4, 5 ] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define K1_PADCONF(pin, func) (((pin) << 16) | (func)) + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x400>; + + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { + pinmux = <K1_PADCONF(68, 2)>, + <K1_PADCONF(69, 2)>; + + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..21f86740a63d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing <emil.renner.berthing@canonical.com> + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ranges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For most + pads only a few of those 6 configurations are valid though, and a few pads in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either can't + be configured or has some special functions. The rest have configurable drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and + are then meant to be used by the audio co-processor. Each such pad can then + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is + also configured in different registers. All of this is done from a different + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-pinctrl + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + thead,pad-group: + description: | + Select the pad group that is associated with the pin controller instance. + + Base Address Name Group + 0xFF_FFF4_A000 PADCTRL_AOSYS 1 + 0xFF_E7F3_C000 PADCTRL1_APSYS 2 + 0xFF_EC00_7000 PADCTRL0_APSYS 3 + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + description: List of pads that properties in the node apply to. + + function: + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +additionalProperties: false + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xec007000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <3>; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xe7f3c000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <2>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins = "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml new file mode 100644 index 000000000000..55ece6a8be5e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal Pinctrl + +maintainers: + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + Versal's pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, slew rate, etc. + + Each configuration node can consist of multiple nodes describing the pinmux and + pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +properties: + compatible: + const: xlnx,versal-pinctrl + +patternProperties: + '^(.*-)?(default|gpio-grp)$': + type: object + patternProperties: + '^mux': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + $ref: pinmux-node.yaml# + + properties: + pins: + description: + List of pins to select (either this or "groups" must be specified) + $ref: "#/$defs/pins/properties/pins" + + groups: + description: + List of groups to select (either this or "pins" must be + specified), available groups for this subnode. + anyOf: + - pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + - $ref: "#/$defs/pins/properties/groups" + + function: + description: + Specify the alternative function to be configured for the + given pin groups. + enum: [spi0, spi0_ss, spi1, spi1_ss, can0, can1, i2c0, i2c1, i2c_pmc, ttc0_clk, + ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, ttc3_clk, ttc3_wav, wwdt0, + wwdt1, sysmon_i2c0, sysmon_i2c0_alrt, uart0, uart0_ctrl, uart1, uart1_ctrl, + gpio0, gpio1, gpio2, emio0, gem0, gem1, trace0, trace0_clk, mdio0, mdio1, gem_tsu0, + pcie0, smap0, usb0, sd0, sd0_pc, sd0_cd, sd0_wp, sd1, sd1_pc, sd1_wp, sd1_cd, + ospi0, ospi0_ss, qspi0, qspi0_fbclk, qspi0_ss, test_clk, test_scan, tamper_trigger] + + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + '^conf': + type: object + description: + Pinctrl node's client devices use subnodes for pin configurations, + which in turn use the standard properties below. + allOf: + - $ref: pincfg-node.yaml# + - $ref: "#/$defs/pins" + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +$defs: + pins: + properties: + groups: + description: + List of pin groups to select in this subnode. + items: + enum: [spi0_0_grp, spi0_1_grp, spi0_2_grp, spi0_3_grp, spi0_4_grp, spi0_5_grp, + spi0_ss_0_grp, spi0_ss_1_grp, spi0_ss_2_grp, spi0_ss_3_grp, spi0_ss_4_grp, + spi0_ss_5_grp, spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, spi0_ss_9_grp, + spi0_ss_10_grp, spi0_ss_11_grp, spi0_ss_12_grp, spi0_ss_13_grp, spi0_ss_14_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, spi1_0_grp, spi1_1_grp, + spi1_2_grp, spi1_3_grp, spi1_4_grp, spi1_5_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_ss_3_grp, spi1_ss_4_grp, spi1_ss_5_grp, spi1_ss_6_grp, + spi1_ss_7_grp, spi1_ss_8_grp, spi1_ss_9_grp, spi1_ss_10_grp, spi1_ss_11_grp, + spi1_ss_12_grp, spi1_ss_13_grp, spi1_ss_14_grp, spi1_ss_15_grp, spi1_ss_16_grp + spi1_ss_17_grp, can0_0_grp, can0_1_grp, can0_2_grp, can0_3_grp, can0_4_grp, + can0_5_grp, can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp, can0_10_grp, + can0_11_grp, can0_12_grp, can0_13_grp, can0_14_grp, can0_15_grp, can0_16_grp, + can0_17_grp, can1_0_grp, can1_1_grp, can1_2_grp, can1_3_grp, can1_4_grp, + can1_5_grp, can1_6_grp, can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp, + can1_11_grp, can1_12_grp, can1_13_grp, can1_14_grp, can1_15_grp, can1_16_grp, + can1_17_grp, can1_18_grp, i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp, + i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, i2c0_8_grp, i2c0_9_grp, + i2c0_10_grp, i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, i2c0_14_grp, i2c0_15_grp, + i2c0_16_grp, i2c0_17_grp, i2c1_0_grp, i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, i2c_pmc_0_grp, i2c_pmc_1_grp, + i2c_pmc_2_grp, i2c_pmc_3_grp, i2c_pmc_4_grp, i2c_pmc_5_grp, i2c_pmc_6_grp, + i2c_pmc_7_grp, i2c_pmc_8_grp, i2c_pmc_9_grp, i2c_pmc_10_grp, i2c_pmc_11_grp, + i2c_pmc_12_grp, ttc0_clk_0_grp, ttc0_clk_1_grp, ttc0_clk_2_grp, ttc0_clk_3_grp, + ttc0_clk_4_grp, ttc0_clk_5_grp, ttc0_clk_6_grp, ttc0_clk_7_grp, ttc0_clk_8_grp, + ttc0_wav_0_grp, ttc0_wav_1_grp, ttc0_wav_2_grp, ttc0_wav_3_grp, ttc0_wav_4_grp, + ttc0_wav_5_grp, ttc0_wav_6_grp, ttc0_wav_7_grp, ttc0_wav_8_grp, ttc1_clk_0_grp, + ttc1_clk_1_grp, ttc1_clk_2_grp, ttc1_clk_3_grp, ttc1_clk_4_grp, ttc1_clk_5_grp, + ttc1_clk_6_grp, ttc1_clk_7_grp, ttc1_clk_8_grp, ttc1_wav_0_grp, ttc1_wav_1_grp, + ttc1_wav_2_grp, ttc1_wav_3_grp, ttc1_wav_4_grp, ttc1_wav_5_grp, ttc1_wav_6_grp, + ttc1_wav_7_grp, ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_clk_1_grp, ttc2_clk_2_grp, + ttc2_clk_3_grp, ttc2_clk_4_grp, ttc2_clk_5_grp, ttc2_clk_6_grp, ttc2_clk_7_grp, + ttc2_clk_8_grp, ttc2_wav_0_grp, ttc2_wav_1_grp, ttc2_wav_2_grp, ttc2_wav_3_grp, + ttc2_wav_4_grp, ttc2_wav_5_grp, ttc2_wav_6_grp, ttc2_wav_7_grp, ttc2_wav_8_grp, + ttc3_clk_0_grp, ttc3_clk_1_grp, ttc3_clk_2_grp, ttc3_clk_3_grp, ttc3_clk_4_grp, + ttc3_clk_5_grp, ttc3_clk_6_grp, ttc3_clk_7_grp, ttc3_clk_8_grp, ttc3_wav_0_grp, + ttc3_wav_1_grp, ttc3_wav_2_grp, ttc3_wav_3_grp, ttc3_wav_4_grp, ttc3_wav_5_grp, + ttc3_wav_6_grp, ttc3_wav_7_grp, ttc3_wav_8_grp, wwdt0_0_grp, wwdt0_1_grp, + wwdt0_2_grp, wwdt0_3_grp, wwdt0_4_grp, wwdt0_5_grp, wwdt1_0_grp, wwdt1_1_grp, + wwdt1_2_grp, wwdt1_3_grp, wwdt1_4_grp, wwdt1_5_grp, sysmon_i2c0_0_grp, + sysmon_i2c0_1_grp, sysmon_i2c0_2_grp, sysmon_i2c0_3_grp, sysmon_i2c0_4_grp, + sysmon_i2c0_5_grp, sysmon_i2c0_6_grp, sysmon_i2c0_7_grp, sysmon_i2c0_8_grp, + sysmon_i2c0_9_grp, sysmon_i2c0_10_grp, sysmon_i2c0_11_grp, sysmon_i2c0_12_grp, + sysmon_i2c0_13_grp, sysmon_i2c0_14_grp, sysmon_i2c0_15_grp, + sysmon_i2c0_16_grp, sysmon_i2c0_17_grp, sysmon_i2c0_alrt_0_grp, + sysmon_i2c0_alrt_1_grp, sysmon_i2c0_alrt_2_grp, sysmon_i2c0_alrt_3_grp, + sysmon_i2c0_alrt_4_grp, sysmon_i2c0_alrt_5_grp, sysmon_i2c0_alrt_6_grp, + sysmon_i2c0_alrt_7_grp, sysmon_i2c0_alrt_8_grp, sysmon_i2c0_alrt_9_grp, + sysmon_i2c0_alrt_10_grp, sysmon_i2c0_alrt_11_grp, sysmon_i2c0_alrt_12_grp, + sysmon_i2c0_alrt_13_grp, sysmon_i2c0_alrt_14_grp, sysmon_i2c0_alrt_15_grp, + sysmon_i2c0_alrt_16_grp, sysmon_i2c0_alrt_17_grp, uart0_0_grp, uart0_1_grp, + uart0_2_grp, uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp, uart0_7_grp, + uart0_8_grp, uart0_ctrl_0_grp, uart0_ctrl_1_grp, uart0_ctrl_2_grp, + uart0_ctrl_3_grp, uart0_ctrl_4_grp, uart0_ctrl_5_grp, uart0_ctrl_6_grp, + uart0_ctrl_7_grp, uart0_ctrl_8_grp, uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_ctrl_0_grp, uart1_ctrl_1_grp, uart1_ctrl_2_grp, uart1_ctrl_3_grp, + uart1_ctrl_4_grp, uart1_ctrl_5_grp, uart1_ctrl_6_grp, uart1_ctrl_7_grp, + uart1_ctrl_8_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp, + gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, gpio0_19_grp, + gpio0_20_grp, gpio0_21_grp, gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio1_0_grp, gpio1_1_grp, gpio1_2_grp, gpio1_3_grp, gpio1_4_grp, + gpio1_5_grp, gpio1_6_grp, gpio1_7_grp, gpio1_8_grp, gpio1_9_grp, + gpio1_10_grp, gpio1_11_grp, gpio1_12_grp, gpio1_13_grp, gpio1_14_grp, + gpio1_15_grp, gpio1_16_grp, gpio1_17_grp, gpio1_18_grp, gpio1_19_grp, + gpio1_20_grp, gpio1_21_grp, gpio1_22_grp, gpio1_23_grp, gpio1_24_grp, + gpio1_25_grp, gpio2_0_grp, gpio2_1_grp, gpio2_2_grp, gpio2_3_grp, gpio2_4_grp, + gpio2_5_grp, gpio2_6_grp, gpio2_7_grp, gpio2_8_grp, gpio2_9_grp, gpio2_10_grp, + gpio2_11_grp, gpio2_12_grp, gpio2_13_grp, gpio2_14_grp, gpio2_15_grp, + gpio2_16_grp, gpio2_17_grp, gpio2_18_grp, gpio2_19_grp, gpio2_20_grp, + gpio2_21_grp, gpio2_22_grp, gpio2_23_grp, gpio2_24_grp, gpio2_25_grp, + emio0_0_grp, emio0_1_grp, emio0_2_grp, emio0_3_grp, emio0_4_grp, emio0_5_grp, + emio0_6_grp, emio0_7_grp, emio0_8_grp, emio0_9_grp, emio0_10_grp, + emio0_11_grp, emio0_12_grp, emio0_13_grp, emio0_14_grp, emio0_15_grp, + emio0_16_grp, emio0_17_grp, emio0_18_grp, emio0_19_grp, emio0_20_grp, + emio0_21_grp, emio0_22_grp, emio0_23_grp, emio0_24_grp, emio0_25_grp, + emio0_26_grp, emio0_27_grp, emio0_28_grp, emio0_29_grp, emio0_30_grp, + emio0_31_grp, emio0_32_grp, emio0_33_grp, emio0_34_grp, emio0_35_grp, + emio0_36_grp, emio0_37_grp, emio0_38_grp, emio0_39_grp, emio0_40_grp, + emio0_41_grp, emio0_42_grp, emio0_43_grp, emio0_44_grp, emio0_45_grp, + emio0_46_grp, emio0_47_grp, emio0_48_grp, emio0_49_grp, emio0_50_grp, + emio0_51_grp, emio0_52_grp, emio0_53_grp, emio0_54_grp, emio0_55_grp, + emio0_56_grp, emio0_57_grp, emio0_58_grp, emio0_59_grp, emio0_60_grp, + emio0_61_grp, emio0_62_grp, emio0_63_grp, emio0_64_grp, emio0_65_grp, + emio0_66_grp, emio0_67_grp, emio0_68_grp, emio0_69_grp, emio0_70_grp, + emio0_71_grp, emio0_72_grp, emio0_73_grp, emio0_74_grp, emio0_75_grp, + emio0_76_grp, emio0_77_grp, gem0_0_grp, gem0_1_grp, gem1_0_grp, gem1_1_grp, + trace0_0_grp, trace0_1_grp, trace0_2_grp, trace0_clk_0_grp, trace0_clk_1_grp, + trace0_clk_2_grp, mdio0_0_grp, mdio0_1_grp, mdio1_0_grp, mdio1_1_grp, + gem_tsu0_0_grp, gem_tsu0_1_grp, gem_tsu0_2_grp, gem_tsu0_3_grp, pcie0_0_grp, + pcie0_1_grp, pcie0_2_grp, smap0_0_grp, usb0_0_grp, sd0_0_grp, sd0_1_grp, + sd0_2_grp, sd0_3_grp, sd0_4_grp, sd0_5_grp, sd0_6_grp, sd0_7_grp, sd0_8_grp, + sd0_9_grp, sd0_10_grp, sd0_11_grp, sd0_12_grp, sd0_13_grp, sd0_14_grp, + sd0_15_grp, sd0_16_grp, sd0_17_grp, sd0_18_grp, sd0_19_grp, sd0_20_grp, + sd0_21_grp, sd0_pc_0_grp, sd0_pc_1_grp, sd0_cd_0_grp, sd0_cd_1_grp, + sd0_wp_0_grp, sd0_wp_1_grp, sd1_0_grp, sd1_1_grp, sd1_2_grp, sd1_3_grp, + sd1_4_grp, sd1_5_grp, sd1_6_grp, sd1_7_grp, sd1_8_grp, sd1_9_grp, sd1_10_grp, + sd1_11_grp, sd1_12_grp, sd1_13_grp, sd1_14_grp, sd1_15_grp, sd1_16_grp, + sd1_17_grp, sd1_18_grp, sd1_19_grp, sd1_20_grp, sd1_21_grp, sd1_pc_0_grp, + sd1_pc_1_grp, sd1_cd_0_grp, sd1_cd_1_grp, sd1_wp_0_grp, sd1_wp_1_grp, + ospi0_0_grp, ospi0_ss_0_grp, qspi0_0_grp, qspi0_fbclk_0_grp, qspi0_ss_0_grp, + test_clk_0_grp, test_scan_0_grp, tamper_trigger_0_grp] + minItems: 1 + maxItems: 78 + + pins: + description: + List of pin names to select in this subnode. + items: + pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + minItems: 1 + maxItems: 78 + + bias-pull-up: true + bias-pull-down: true + bias-disable: true + input-schmitt-enable: true + input-schmitt-disable: true + bias-high-impedance: true + low-power-enable: true + low-power-disable: true + + slew-rate: + enum: [0, 1] + + output-enable: + description: + This will internally disable the tri-state for MIO pins. + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 8, 12] + + power-source: + enum: [0, 1] + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + pinctrl { + compatible = "xlnx,versal-pinctrl"; + + uart0-default { + mux { + groups = "uart0_4_grp", "uart0_5_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "PMC_MIO42"; + bias-pull-up; + }; + + conf-tx { + pins = "PMC_MIO43"; + bias-disable; + input-schmitt-disable; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml b/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml new file mode 100644 index 000000000000..f36387572a97 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/airoha,en7581-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 PWM Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: airoha,en7581-pwm + + "#pwm-cells": + const: 3 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + pwm { + compatible = "airoha,en7581-pwm"; + + #pwm-cells = <3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 39319bed3116..1403c5e6ca02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18315,6 +18315,13 @@ F: drivers/pinctrl/ F: include/dt-bindings/pinctrl/ F: include/linux/pinctrl/ +PIN CONTROLLER - AIROHA +M: Lorenzo Bianconi <lorenzo@kernel.org> +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-airoha.c + PIN CONTROLLER - AMD M: Basavaraj Natikar <Basavaraj.Natikar@amd.com> M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> @@ -20073,9 +20080,11 @@ S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml +F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c +F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h RNBD BLOCK DRIVERS diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ab767f059929..e4fe059cd861 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -6,7 +6,6 @@ menuconfig ARCH_MXC select CLKSRC_IMX_GPT select GENERIC_IRQ_CHIP select GPIOLIB - select PINCTRL select PM_OPP if PM select SOC_BUS select SRAM @@ -49,7 +48,6 @@ config SOC_IMX31 config SOC_IMX35 bool "i.MX35 support" select MXC_AVIC - select PINCTRL_IMX35 help This enables support for Freescale i.MX35 processor @@ -61,7 +59,6 @@ config SOC_IMX1 bool "i.MX1 support" select CPU_ARM920T select MXC_AVIC - select PINCTRL_IMX1 help This enables support for Freescale i.MX1 processor @@ -73,7 +70,6 @@ config SOC_IMX25 bool "i.MX25 support" select CPU_ARM926T select MXC_AVIC - select PINCTRL_IMX25 help This enables support for Freescale i.MX25 processor @@ -81,7 +77,6 @@ config SOC_IMX27 bool "i.MX27 support" select CPU_ARM926T select MXC_AVIC - select PINCTRL_IMX27 help This enables support for Freescale i.MX27 processor @@ -98,7 +93,6 @@ config SOC_IMX5 config SOC_IMX50 bool "i.MX50 support" - select PINCTRL_IMX50 select SOC_IMX5 help @@ -106,14 +100,12 @@ config SOC_IMX50 config SOC_IMX51 bool "i.MX51 support" - select PINCTRL_IMX51 select SOC_IMX5 help This enables support for Freescale i.MX51 processor config SOC_IMX53 bool "i.MX53 support" - select PINCTRL_IMX53 select SOC_IMX5 help @@ -137,7 +129,6 @@ config SOC_IMX6Q select ARM_ERRATA_775420 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD - select PINCTRL_IMX6Q select SOC_IMX6 help @@ -147,7 +138,6 @@ config SOC_IMX6SL bool "i.MX6 SoloLite support" select ARM_ERRATA_754322 select ARM_ERRATA_775420 - select PINCTRL_IMX6SL select SOC_IMX6 help @@ -157,7 +147,6 @@ config SOC_IMX6SLL bool "i.MX6 SoloLiteLite support" select ARM_ERRATA_754322 select ARM_ERRATA_775420 - select PINCTRL_IMX6SLL select SOC_IMX6 help @@ -167,7 +156,6 @@ config SOC_IMX6SX bool "i.MX6 SoloX support" select ARM_ERRATA_754322 select ARM_ERRATA_775420 - select PINCTRL_IMX6SX select SOC_IMX6 help @@ -175,7 +163,6 @@ config SOC_IMX6SX config SOC_IMX6UL bool "i.MX6 UltraLite support" - select PINCTRL_IMX6UL select SOC_IMX6 select ARM_ERRATA_814220 @@ -211,7 +198,6 @@ config SOC_IMX7D_CM4 config SOC_IMX7D bool "i.MX7 Dual support" - select PINCTRL_IMX7D select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M select ARM_ERRATA_814220 if ARCH_MULTI_V7 @@ -221,7 +207,6 @@ config SOC_IMX7D config SOC_IMX7ULP bool "i.MX7ULP support" select CLKSRC_IMX_TPM - select PINCTRL_IMX7ULP select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M help @@ -237,7 +222,6 @@ config SOC_IMXRT config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 - select PINCTRL_VF610 help This enables support for Freescale Vybrid VF610 processor. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 354536de564b..95a8e2b9a614 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -268,6 +268,17 @@ config PINCTRL_K210 Add support for the Canaan Kendryte K210 RISC-V SOC Field Programmable IO Array (FPIOA) controller. +config PINCTRL_K230 + bool "Pinctrl driver for the Canaan Kendryte K230 SoC" + depends on OF + depends on ARCH_CANAAN || COMPILE_TEST + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Add support for the Canaan Kendryte K230 RISC-V SOC pin controller. + config PINCTRL_KEEMBAY tristate "Pinctrl driver for Intel Keem Bay SoC" depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST) @@ -551,6 +562,20 @@ config PINCTRL_TPS6594 This driver can also be built as a module called tps6594-pinctrl. +config PINCTRL_TH1520 + tristate "Pinctrl driver for the T-Head TH1520 SoC" + depends on ARCH_THEAD || COMPILE_TEST + depends on OF + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINMUX + help + This is the driver for the pin controller blocks on the + T-Head TH1520 SoC. + + This driver is needed for RISC-V development boards like + the BeagleV Ahead and the LicheePi 4A. + config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" depends on ARCH_ZYNQ @@ -606,6 +631,7 @@ source "drivers/pinctrl/realtek/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sophgo/Kconfig" +source "drivers/pinctrl/spacemit/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/starfive/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 97823f52b972..fba1c56624c0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o +obj-$(CONFIG_PINCTRL_K230) += pinctrl-k230.o obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o @@ -54,6 +55,7 @@ obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_TPS6594) += pinctrl-tps6594.o +obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o @@ -76,6 +78,7 @@ obj-$(CONFIG_ARCH_REALTEK) += realtek/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-y += sophgo/ +obj-y += spacemit/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_SOC_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 6ecc656abc44..5a7cd0a88687 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -2607,6 +2607,10 @@ static struct aspeed_pin_config aspeed_g6_configs[] = { { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, /* LAD0 */ { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, + /* GPIOF */ + { PIN_CONFIG_DRIVE_STRENGTH, { D22, A23 }, SCU458, GENMASK(9, 8)}, + /* GPIOG */ + { PIN_CONFIG_DRIVE_STRENGTH, { E21, B21 }, SCU458, GENMASK(11, 10)}, /* MAC3 */ { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)}, diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index 2932d7aba725..73ec5b9beb49 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -1091,7 +1091,7 @@ static void madera_pin_remove(struct platform_device *pdev) static struct platform_driver madera_pin_driver = { .probe = madera_pin_probe, - .remove_new = madera_pin_remove, + .remove = madera_pin_remove, .driver = { .name = "madera-pinctrl", }, diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 4061890a1748..b3eec63c00ba 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -220,6 +220,9 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, /* Set owner */ pindesc->pctldev = pctldev; +#ifdef CONFIG_PINMUX + mutex_init(&pindesc->mux_lock); +#endif /* Copy basic pin info */ if (pin->name) { diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 4e07707d2435..d6c24978e708 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -177,6 +177,7 @@ struct pin_desc { const char *mux_owner; const struct pinctrl_setting_mux *mux_setting; const char *gpio_owner; + struct mutex mux_lock; #endif }; diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 3b59d7189004..4c420b21b804 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -9,7 +9,7 @@ config PINCTRL_IMX config PINCTRL_IMX_SCMI tristate "i.MX95 pinctrl driver using SCMI protocol interface" - depends on ARM_SCMI_PROTOCOL && OF || COMPILE_TEST + depends on ARM_SCMI_PROTOCOL && OF select PINMUX select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS @@ -20,7 +20,7 @@ config PINCTRL_IMX_SCMI config PINCTRL_IMX_SCU tristate - depends on IMX_SCU + depends on IMX_SCU || COMPILE_TEST select PINCTRL_IMX config PINCTRL_IMX1_CORE @@ -30,14 +30,18 @@ config PINCTRL_IMX1_CORE config PINCTRL_IMX1 bool "IMX1 pinctrl driver" - depends on SOC_IMX1 + depends on OF + depends on SOC_IMX1 || COMPILE_TEST + default SOC_IMX1 select PINCTRL_IMX1_CORE help Say Y here to enable the imx1 pinctrl driver config PINCTRL_IMX27 bool "IMX27 pinctrl driver" - depends on SOC_IMX27 + depends on OF + depends on SOC_IMX27 || COMPILE_TEST + default SOC_IMX27 select PINCTRL_IMX1_CORE help Say Y here to enable the imx27 pinctrl driver @@ -46,84 +50,107 @@ config PINCTRL_IMX27 config PINCTRL_IMX25 bool "IMX25 pinctrl driver" depends on OF - depends on SOC_IMX25 + depends on SOC_IMX25 || COMPILE_TEST + default SOC_IMX25 select PINCTRL_IMX help Say Y here to enable the imx25 pinctrl driver config PINCTRL_IMX35 bool "IMX35 pinctrl driver" - depends on SOC_IMX35 + depends on OF + depends on SOC_IMX35 || COMPILE_TEST + default SOC_IMX35 select PINCTRL_IMX help Say Y here to enable the imx35 pinctrl driver config PINCTRL_IMX50 bool "IMX50 pinctrl driver" - depends on SOC_IMX50 + depends on OF + depends on SOC_IMX50 || COMPILE_TEST + default SOC_IMX50 select PINCTRL_IMX help Say Y here to enable the imx50 pinctrl driver config PINCTRL_IMX51 bool "IMX51 pinctrl driver" - depends on SOC_IMX51 + depends on OF + depends on SOC_IMX51 || COMPILE_TEST + default SOC_IMX51 select PINCTRL_IMX help Say Y here to enable the imx51 pinctrl driver config PINCTRL_IMX53 bool "IMX53 pinctrl driver" - depends on SOC_IMX53 + depends on OF + depends on SOC_IMX53 || COMPILE_TEST + default SOC_IMX53 select PINCTRL_IMX help Say Y here to enable the imx53 pinctrl driver config PINCTRL_IMX6Q bool "IMX6Q/DL pinctrl driver" - depends on SOC_IMX6Q + depends on OF + depends on SOC_IMX6Q || COMPILE_TEST + default SOC_IMX6Q select PINCTRL_IMX help Say Y here to enable the imx6q/dl pinctrl driver config PINCTRL_IMX6SL bool "IMX6SL pinctrl driver" - depends on SOC_IMX6SL + depends on OF + depends on SOC_IMX6SL || COMPILE_TEST + default SOC_IMX6SL select PINCTRL_IMX help Say Y here to enable the imx6sl pinctrl driver config PINCTRL_IMX6SLL bool "IMX6SLL pinctrl driver" - depends on SOC_IMX6SLL + depends on OF + depends on SOC_IMX6SLL || COMPILE_TEST + default SOC_IMX6SLL select PINCTRL_IMX help Say Y here to enable the imx6sll pinctrl driver config PINCTRL_IMX6SX bool "IMX6SX pinctrl driver" - depends on SOC_IMX6SX + depends on OF + depends on SOC_IMX6SX || COMPILE_TEST + default SOC_IMX6SX select PINCTRL_IMX help Say Y here to enable the imx6sx pinctrl driver config PINCTRL_IMX6UL bool "IMX6UL pinctrl driver" - depends on SOC_IMX6UL + depends on OF + depends on SOC_IMX6UL || COMPILE_TEST + default SOC_IMX6UL select PINCTRL_IMX help Say Y here to enable the imx6ul pinctrl driver config PINCTRL_IMX7D bool "IMX7D pinctrl driver" - depends on SOC_IMX7D + depends on OF + depends on SOC_IMX7D || COMPILE_TEST + default SOC_IMX7D select PINCTRL_IMX help Say Y here to enable the imx7d pinctrl driver config PINCTRL_IMX7ULP bool "IMX7ULP pinctrl driver" - depends on SOC_IMX7ULP + depends on OF + depends on SOC_IMX7ULP || COMPILE_TEST + default SOC_IMX7ULP select PINCTRL_IMX help Say Y here to enable the imx7ulp pinctrl driver @@ -131,7 +158,7 @@ config PINCTRL_IMX7ULP config PINCTRL_IMX8MM tristate "IMX8MM pinctrl driver" depends on OF - depends on SOC_IMX8M + depends on SOC_IMX8M || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx8mm pinctrl driver @@ -139,7 +166,7 @@ config PINCTRL_IMX8MM config PINCTRL_IMX8MN tristate "IMX8MN pinctrl driver" depends on OF - depends on SOC_IMX8M + depends on SOC_IMX8M || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx8mn pinctrl driver @@ -147,7 +174,7 @@ config PINCTRL_IMX8MN config PINCTRL_IMX8MP tristate "IMX8MP pinctrl driver" depends on OF - depends on SOC_IMX8M + depends on SOC_IMX8M || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx8mp pinctrl driver @@ -155,42 +182,48 @@ config PINCTRL_IMX8MP config PINCTRL_IMX8MQ tristate "IMX8MQ pinctrl driver" depends on OF - depends on SOC_IMX8M + depends on SOC_IMX8M || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx8mq pinctrl driver config PINCTRL_IMX8QM tristate "IMX8QM pinctrl driver" - depends on IMX_SCU && ARCH_MXC && ARM64 + depends on OF + depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST select PINCTRL_IMX_SCU help Say Y here to enable the imx8qm pinctrl driver config PINCTRL_IMX8QXP tristate "IMX8QXP pinctrl driver" - depends on IMX_SCU && ARCH_MXC && ARM64 + depends on OF + depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST select PINCTRL_IMX_SCU help Say Y here to enable the imx8qxp pinctrl driver config PINCTRL_IMX8DXL tristate "IMX8DXL pinctrl driver" - depends on IMX_SCU && ARCH_MXC && ARM64 + depends on OF + depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST select PINCTRL_IMX_SCU help Say Y here to enable the imx8dxl pinctrl driver config PINCTRL_IMX8ULP tristate "IMX8ULP pinctrl driver" - depends on ARCH_MXC + depends on OF + depends on ARCH_MXC || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx8ulp pinctrl driver config PINCTRL_IMXRT1050 bool "IMXRT1050 pinctrl driver" - depends on ARCH_MXC + depends on OF + depends on SOC_IMXRT || COMPILE_TEST + default SOC_IMXRT select PINCTRL_IMX help Say Y here to enable the imxrt1050 pinctrl driver @@ -204,14 +237,17 @@ config PINCTRL_IMX91 config PINCTRL_IMX93 tristate "IMX93 pinctrl driver" - depends on ARCH_MXC + depends on OF + depends on ARCH_MXC || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imx93 pinctrl driver config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" - depends on SOC_VF610 + depends on OF + depends on SOC_VF610 || COMPILE_TEST + default SOC_VF610 select PINCTRL_IMX help Say Y here to enable the Freescale Vybrid VF610 pinctrl driver @@ -231,7 +267,8 @@ config PINCTRL_IMX28 config PINCTRL_IMXRT1170 bool "IMXRT1170 pinctrl driver" - depends on ARCH_MXC + depends on OF + depends on SOC_IMXRT || COMPILE_TEST select PINCTRL_IMX help Say Y here to enable the imxrt1170 pinctrl driver diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index d05c2c478e79..842a1e6cbfc4 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -633,11 +633,11 @@ static int imx_pinctrl_parse_functions(struct device_node *np, static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) { for_each_child_of_node_scoped(np, function_np) { - if (of_property_read_bool(function_np, "fsl,pins")) + if (of_property_present(function_np, "fsl,pins")) return true; for_each_child_of_node_scoped(function_np, pinctrl_np) { - if (of_property_read_bool(pinctrl_np, "fsl,pins")) + if (of_property_present(pinctrl_np, "fsl,pins")) return false; } } @@ -746,7 +746,7 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (IS_ERR(ipctl->base)) return PTR_ERR(ipctl->base); - if (of_property_read_bool(dev_np, "fsl,input-sel")) { + if (of_property_present(dev_np, "fsl,input-sel")) { np = of_parse_phandle(dev_np, "fsl,input-sel", 0); if (!np) { dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c index 1e2b0fe9ffd6..bd39cadf1f34 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1.c @@ -12,122 +12,122 @@ #include "pinctrl-imx1.h" #define PAD_ID(port, pin) ((port) * 32 + (pin)) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 +#define IMX1_PA 0 +#define IMX1_PB 1 +#define IMX1_PC 2 +#define IMX1_PD 3 enum imx1_pads { - MX1_PAD_A24 = PAD_ID(PA, 0), - MX1_PAD_TIN = PAD_ID(PA, 1), - MX1_PAD_PWMO = PAD_ID(PA, 2), - MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), - MX1_PAD_CSI_D0 = PAD_ID(PA, 4), - MX1_PAD_CSI_D1 = PAD_ID(PA, 5), - MX1_PAD_CSI_D2 = PAD_ID(PA, 6), - MX1_PAD_CSI_D3 = PAD_ID(PA, 7), - MX1_PAD_CSI_D4 = PAD_ID(PA, 8), - MX1_PAD_CSI_D5 = PAD_ID(PA, 9), - MX1_PAD_CSI_D6 = PAD_ID(PA, 10), - MX1_PAD_CSI_D7 = PAD_ID(PA, 11), - MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), - MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), - MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), - MX1_PAD_I2C_SDA = PAD_ID(PA, 15), - MX1_PAD_I2C_SCL = PAD_ID(PA, 16), - MX1_PAD_DTACK = PAD_ID(PA, 17), - MX1_PAD_BCLK = PAD_ID(PA, 18), - MX1_PAD_LBA = PAD_ID(PA, 19), - MX1_PAD_ECB = PAD_ID(PA, 20), - MX1_PAD_A0 = PAD_ID(PA, 21), - MX1_PAD_CS4 = PAD_ID(PA, 22), - MX1_PAD_CS5 = PAD_ID(PA, 23), - MX1_PAD_A16 = PAD_ID(PA, 24), - MX1_PAD_A17 = PAD_ID(PA, 25), - MX1_PAD_A18 = PAD_ID(PA, 26), - MX1_PAD_A19 = PAD_ID(PA, 27), - MX1_PAD_A20 = PAD_ID(PA, 28), - MX1_PAD_A21 = PAD_ID(PA, 29), - MX1_PAD_A22 = PAD_ID(PA, 30), - MX1_PAD_A23 = PAD_ID(PA, 31), - MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), - MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), - MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), - MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), - MX1_PAD_SD_SCLK = PAD_ID(PB, 12), - MX1_PAD_SD_CMD = PAD_ID(PB, 13), - MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), - MX1_PAD_SIM_PD = PAD_ID(PB, 15), - MX1_PAD_SIM_TX = PAD_ID(PB, 16), - MX1_PAD_SIM_RX = PAD_ID(PB, 17), - MX1_PAD_SIM_RST = PAD_ID(PB, 18), - MX1_PAD_SIM_CLK = PAD_ID(PB, 19), - MX1_PAD_USBD_AFE = PAD_ID(PB, 20), - MX1_PAD_USBD_OE = PAD_ID(PB, 21), - MX1_PAD_USBD_RCV = PAD_ID(PB, 22), - MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), - MX1_PAD_USBD_VP = PAD_ID(PB, 24), - MX1_PAD_USBD_VM = PAD_ID(PB, 25), - MX1_PAD_USBD_VPO = PAD_ID(PB, 26), - MX1_PAD_USBD_VMO = PAD_ID(PB, 27), - MX1_PAD_UART2_CTS = PAD_ID(PB, 28), - MX1_PAD_UART2_RTS = PAD_ID(PB, 29), - MX1_PAD_UART2_TXD = PAD_ID(PB, 30), - MX1_PAD_UART2_RXD = PAD_ID(PB, 31), - MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), - MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), - MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), - MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), - MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), - MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), - MX1_PAD_UART1_CTS = PAD_ID(PC, 9), - MX1_PAD_UART1_RTS = PAD_ID(PC, 10), - MX1_PAD_UART1_TXD = PAD_ID(PC, 11), - MX1_PAD_UART1_RXD = PAD_ID(PC, 12), - MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), - MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), - MX1_PAD_SPI1_SS = PAD_ID(PC, 15), - MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), - MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), - MX1_PAD_BT13 = PAD_ID(PC, 19), - MX1_PAD_BT12 = PAD_ID(PC, 20), - MX1_PAD_BT11 = PAD_ID(PC, 21), - MX1_PAD_BT10 = PAD_ID(PC, 22), - MX1_PAD_BT9 = PAD_ID(PC, 23), - MX1_PAD_BT8 = PAD_ID(PC, 24), - MX1_PAD_BT7 = PAD_ID(PC, 25), - MX1_PAD_BT6 = PAD_ID(PC, 26), - MX1_PAD_BT5 = PAD_ID(PC, 27), - MX1_PAD_BT4 = PAD_ID(PC, 28), - MX1_PAD_BT3 = PAD_ID(PC, 29), - MX1_PAD_BT2 = PAD_ID(PC, 30), - MX1_PAD_BT1 = PAD_ID(PC, 31), - MX1_PAD_LSCLK = PAD_ID(PD, 6), - MX1_PAD_REV = PAD_ID(PD, 7), - MX1_PAD_CLS = PAD_ID(PD, 8), - MX1_PAD_PS = PAD_ID(PD, 9), - MX1_PAD_SPL_SPR = PAD_ID(PD, 10), - MX1_PAD_CONTRAST = PAD_ID(PD, 11), - MX1_PAD_ACD_OE = PAD_ID(PD, 12), - MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), - MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), - MX1_PAD_LD0 = PAD_ID(PD, 15), - MX1_PAD_LD1 = PAD_ID(PD, 16), - MX1_PAD_LD2 = PAD_ID(PD, 17), - MX1_PAD_LD3 = PAD_ID(PD, 18), - MX1_PAD_LD4 = PAD_ID(PD, 19), - MX1_PAD_LD5 = PAD_ID(PD, 20), - MX1_PAD_LD6 = PAD_ID(PD, 21), - MX1_PAD_LD7 = PAD_ID(PD, 22), - MX1_PAD_LD8 = PAD_ID(PD, 23), - MX1_PAD_LD9 = PAD_ID(PD, 24), - MX1_PAD_LD10 = PAD_ID(PD, 25), - MX1_PAD_LD11 = PAD_ID(PD, 26), - MX1_PAD_LD12 = PAD_ID(PD, 27), - MX1_PAD_LD13 = PAD_ID(PD, 28), - MX1_PAD_LD14 = PAD_ID(PD, 29), - MX1_PAD_LD15 = PAD_ID(PD, 30), - MX1_PAD_TMR2OUT = PAD_ID(PD, 31), + MX1_PAD_A24 = PAD_ID(IMX1_PA, 0), + MX1_PAD_TIN = PAD_ID(IMX1_PA, 1), + MX1_PAD_PWMO = PAD_ID(IMX1_PA, 2), + MX1_PAD_CSI_MCLK = PAD_ID(IMX1_PA, 3), + MX1_PAD_CSI_D0 = PAD_ID(IMX1_PA, 4), + MX1_PAD_CSI_D1 = PAD_ID(IMX1_PA, 5), + MX1_PAD_CSI_D2 = PAD_ID(IMX1_PA, 6), + MX1_PAD_CSI_D3 = PAD_ID(IMX1_PA, 7), + MX1_PAD_CSI_D4 = PAD_ID(IMX1_PA, 8), + MX1_PAD_CSI_D5 = PAD_ID(IMX1_PA, 9), + MX1_PAD_CSI_D6 = PAD_ID(IMX1_PA, 10), + MX1_PAD_CSI_D7 = PAD_ID(IMX1_PA, 11), + MX1_PAD_CSI_VSYNC = PAD_ID(IMX1_PA, 12), + MX1_PAD_CSI_HSYNC = PAD_ID(IMX1_PA, 13), + MX1_PAD_CSI_PIXCLK = PAD_ID(IMX1_PA, 14), + MX1_PAD_I2C_SDA = PAD_ID(IMX1_PA, 15), + MX1_PAD_I2C_SCL = PAD_ID(IMX1_PA, 16), + MX1_PAD_DTACK = PAD_ID(IMX1_PA, 17), + MX1_PAD_BCLK = PAD_ID(IMX1_PA, 18), + MX1_PAD_LBA = PAD_ID(IMX1_PA, 19), + MX1_PAD_ECB = PAD_ID(IMX1_PA, 20), + MX1_PAD_A0 = PAD_ID(IMX1_PA, 21), + MX1_PAD_CS4 = PAD_ID(IMX1_PA, 22), + MX1_PAD_CS5 = PAD_ID(IMX1_PA, 23), + MX1_PAD_A16 = PAD_ID(IMX1_PA, 24), + MX1_PAD_A17 = PAD_ID(IMX1_PA, 25), + MX1_PAD_A18 = PAD_ID(IMX1_PA, 26), + MX1_PAD_A19 = PAD_ID(IMX1_PA, 27), + MX1_PAD_A20 = PAD_ID(IMX1_PA, 28), + MX1_PAD_A21 = PAD_ID(IMX1_PA, 29), + MX1_PAD_A22 = PAD_ID(IMX1_PA, 30), + MX1_PAD_A23 = PAD_ID(IMX1_PA, 31), + MX1_PAD_SD_DAT0 = PAD_ID(IMX1_PB, 8), + MX1_PAD_SD_DAT1 = PAD_ID(IMX1_PB, 9), + MX1_PAD_SD_DAT2 = PAD_ID(IMX1_PB, 10), + MX1_PAD_SD_DAT3 = PAD_ID(IMX1_PB, 11), + MX1_PAD_SD_SCLK = PAD_ID(IMX1_PB, 12), + MX1_PAD_SD_CMD = PAD_ID(IMX1_PB, 13), + MX1_PAD_SIM_SVEN = PAD_ID(IMX1_PB, 14), + MX1_PAD_SIM_PD = PAD_ID(IMX1_PB, 15), + MX1_PAD_SIM_TX = PAD_ID(IMX1_PB, 16), + MX1_PAD_SIM_RX = PAD_ID(IMX1_PB, 17), + MX1_PAD_SIM_RST = PAD_ID(IMX1_PB, 18), + MX1_PAD_SIM_CLK = PAD_ID(IMX1_PB, 19), + MX1_PAD_USBD_AFE = PAD_ID(IMX1_PB, 20), + MX1_PAD_USBD_OE = PAD_ID(IMX1_PB, 21), + MX1_PAD_USBD_RCV = PAD_ID(IMX1_PB, 22), + MX1_PAD_USBD_SUSPND = PAD_ID(IMX1_PB, 23), + MX1_PAD_USBD_VP = PAD_ID(IMX1_PB, 24), + MX1_PAD_USBD_VM = PAD_ID(IMX1_PB, 25), + MX1_PAD_USBD_VPO = PAD_ID(IMX1_PB, 26), + MX1_PAD_USBD_VMO = PAD_ID(IMX1_PB, 27), + MX1_PAD_UART2_CTS = PAD_ID(IMX1_PB, 28), + MX1_PAD_UART2_RTS = PAD_ID(IMX1_PB, 29), + MX1_PAD_UART2_TXD = PAD_ID(IMX1_PB, 30), + MX1_PAD_UART2_RXD = PAD_ID(IMX1_PB, 31), + MX1_PAD_SSI_RXFS = PAD_ID(IMX1_PC, 3), + MX1_PAD_SSI_RXCLK = PAD_ID(IMX1_PC, 4), + MX1_PAD_SSI_RXDAT = PAD_ID(IMX1_PC, 5), + MX1_PAD_SSI_TXDAT = PAD_ID(IMX1_PC, 6), + MX1_PAD_SSI_TXFS = PAD_ID(IMX1_PC, 7), + MX1_PAD_SSI_TXCLK = PAD_ID(IMX1_PC, 8), + MX1_PAD_UART1_CTS = PAD_ID(IMX1_PC, 9), + MX1_PAD_UART1_RTS = PAD_ID(IMX1_PC, 10), + MX1_PAD_UART1_TXD = PAD_ID(IMX1_PC, 11), + MX1_PAD_UART1_RXD = PAD_ID(IMX1_PC, 12), + MX1_PAD_SPI1_RDY = PAD_ID(IMX1_PC, 13), + MX1_PAD_SPI1_SCLK = PAD_ID(IMX1_PC, 14), + MX1_PAD_SPI1_SS = PAD_ID(IMX1_PC, 15), + MX1_PAD_SPI1_MISO = PAD_ID(IMX1_PC, 16), + MX1_PAD_SPI1_MOSI = PAD_ID(IMX1_PC, 17), + MX1_PAD_BT13 = PAD_ID(IMX1_PC, 19), + MX1_PAD_BT12 = PAD_ID(IMX1_PC, 20), + MX1_PAD_BT11 = PAD_ID(IMX1_PC, 21), + MX1_PAD_BT10 = PAD_ID(IMX1_PC, 22), + MX1_PAD_BT9 = PAD_ID(IMX1_PC, 23), + MX1_PAD_BT8 = PAD_ID(IMX1_PC, 24), + MX1_PAD_BT7 = PAD_ID(IMX1_PC, 25), + MX1_PAD_BT6 = PAD_ID(IMX1_PC, 26), + MX1_PAD_BT5 = PAD_ID(IMX1_PC, 27), + MX1_PAD_BT4 = PAD_ID(IMX1_PC, 28), + MX1_PAD_BT3 = PAD_ID(IMX1_PC, 29), + MX1_PAD_BT2 = PAD_ID(IMX1_PC, 30), + MX1_PAD_BT1 = PAD_ID(IMX1_PC, 31), + MX1_PAD_LSCLK = PAD_ID(IMX1_PD, 6), + MX1_PAD_REV = PAD_ID(IMX1_PD, 7), + MX1_PAD_CLS = PAD_ID(IMX1_PD, 8), + MX1_PAD_PS = PAD_ID(IMX1_PD, 9), + MX1_PAD_SPL_SPR = PAD_ID(IMX1_PD, 10), + MX1_PAD_CONTRAST = PAD_ID(IMX1_PD, 11), + MX1_PAD_ACD_OE = PAD_ID(IMX1_PD, 12), + MX1_PAD_LP_HSYNC = PAD_ID(IMX1_PD, 13), + MX1_PAD_FLM_VSYNC = PAD_ID(IMX1_PD, 14), + MX1_PAD_LD0 = PAD_ID(IMX1_PD, 15), + MX1_PAD_LD1 = PAD_ID(IMX1_PD, 16), + MX1_PAD_LD2 = PAD_ID(IMX1_PD, 17), + MX1_PAD_LD3 = PAD_ID(IMX1_PD, 18), + MX1_PAD_LD4 = PAD_ID(IMX1_PD, 19), + MX1_PAD_LD5 = PAD_ID(IMX1_PD, 20), + MX1_PAD_LD6 = PAD_ID(IMX1_PD, 21), + MX1_PAD_LD7 = PAD_ID(IMX1_PD, 22), + MX1_PAD_LD8 = PAD_ID(IMX1_PD, 23), + MX1_PAD_LD9 = PAD_ID(IMX1_PD, 24), + MX1_PAD_LD10 = PAD_ID(IMX1_PD, 25), + MX1_PAD_LD11 = PAD_ID(IMX1_PD, 26), + MX1_PAD_LD12 = PAD_ID(IMX1_PD, 27), + MX1_PAD_LD13 = PAD_ID(IMX1_PD, 28), + MX1_PAD_LD14 = PAD_ID(IMX1_PD, 29), + MX1_PAD_LD15 = PAD_ID(IMX1_PD, 30), + MX1_PAD_TMR2OUT = PAD_ID(IMX1_PD, 31), }; /* Pad names for the pinmux subsystem */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c index 1738df461235..afeb39957203 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx27.c +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -16,188 +16,188 @@ #include "pinctrl-imx1.h" #define PAD_ID(port, pin) (port*32 + pin) -#define PA 0 -#define PB 1 -#define PC 2 -#define PD 3 -#define PE 4 -#define PF 5 +#define MX27_PA 0 +#define MX27_PB 1 +#define MX27_PC 2 +#define MX27_PD 3 +#define MX27_PE 4 +#define MX27_PF 5 enum imx27_pads { - MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), - MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), - MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), - MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), - MX27_PAD_USBH2_STP = PAD_ID(PA, 4), - MX27_PAD_LSCLK = PAD_ID(PA, 5), - MX27_PAD_LD0 = PAD_ID(PA, 6), - MX27_PAD_LD1 = PAD_ID(PA, 7), - MX27_PAD_LD2 = PAD_ID(PA, 8), - MX27_PAD_LD3 = PAD_ID(PA, 9), - MX27_PAD_LD4 = PAD_ID(PA, 10), - MX27_PAD_LD5 = PAD_ID(PA, 11), - MX27_PAD_LD6 = PAD_ID(PA, 12), - MX27_PAD_LD7 = PAD_ID(PA, 13), - MX27_PAD_LD8 = PAD_ID(PA, 14), - MX27_PAD_LD9 = PAD_ID(PA, 15), - MX27_PAD_LD10 = PAD_ID(PA, 16), - MX27_PAD_LD11 = PAD_ID(PA, 17), - MX27_PAD_LD12 = PAD_ID(PA, 18), - MX27_PAD_LD13 = PAD_ID(PA, 19), - MX27_PAD_LD14 = PAD_ID(PA, 20), - MX27_PAD_LD15 = PAD_ID(PA, 21), - MX27_PAD_LD16 = PAD_ID(PA, 22), - MX27_PAD_LD17 = PAD_ID(PA, 23), - MX27_PAD_REV = PAD_ID(PA, 24), - MX27_PAD_CLS = PAD_ID(PA, 25), - MX27_PAD_PS = PAD_ID(PA, 26), - MX27_PAD_SPL_SPR = PAD_ID(PA, 27), - MX27_PAD_HSYNC = PAD_ID(PA, 28), - MX27_PAD_VSYNC = PAD_ID(PA, 29), - MX27_PAD_CONTRAST = PAD_ID(PA, 30), - MX27_PAD_OE_ACD = PAD_ID(PA, 31), + MX27_PAD_USBH2_CLK = PAD_ID(MX27_PA, 0), + MX27_PAD_USBH2_DIR = PAD_ID(MX27_PA, 1), + MX27_PAD_USBH2_DATA7 = PAD_ID(MX27_PA, 2), + MX27_PAD_USBH2_NXT = PAD_ID(MX27_PA, 3), + MX27_PAD_USBH2_STP = PAD_ID(MX27_PA, 4), + MX27_PAD_LSCLK = PAD_ID(MX27_PA, 5), + MX27_PAD_LD0 = PAD_ID(MX27_PA, 6), + MX27_PAD_LD1 = PAD_ID(MX27_PA, 7), + MX27_PAD_LD2 = PAD_ID(MX27_PA, 8), + MX27_PAD_LD3 = PAD_ID(MX27_PA, 9), + MX27_PAD_LD4 = PAD_ID(MX27_PA, 10), + MX27_PAD_LD5 = PAD_ID(MX27_PA, 11), + MX27_PAD_LD6 = PAD_ID(MX27_PA, 12), + MX27_PAD_LD7 = PAD_ID(MX27_PA, 13), + MX27_PAD_LD8 = PAD_ID(MX27_PA, 14), + MX27_PAD_LD9 = PAD_ID(MX27_PA, 15), + MX27_PAD_LD10 = PAD_ID(MX27_PA, 16), + MX27_PAD_LD11 = PAD_ID(MX27_PA, 17), + MX27_PAD_LD12 = PAD_ID(MX27_PA, 18), + MX27_PAD_LD13 = PAD_ID(MX27_PA, 19), + MX27_PAD_LD14 = PAD_ID(MX27_PA, 20), + MX27_PAD_LD15 = PAD_ID(MX27_PA, 21), + MX27_PAD_LD16 = PAD_ID(MX27_PA, 22), + MX27_PAD_LD17 = PAD_ID(MX27_PA, 23), + MX27_PAD_REV = PAD_ID(MX27_PA, 24), + MX27_PAD_CLS = PAD_ID(MX27_PA, 25), + MX27_PAD_PS = PAD_ID(MX27_PA, 26), + MX27_PAD_SPL_SPR = PAD_ID(MX27_PA, 27), + MX27_PAD_HSYNC = PAD_ID(MX27_PA, 28), + MX27_PAD_VSYNC = PAD_ID(MX27_PA, 29), + MX27_PAD_CONTRAST = PAD_ID(MX27_PA, 30), + MX27_PAD_OE_ACD = PAD_ID(MX27_PA, 31), - MX27_PAD_SD2_D0 = PAD_ID(PB, 4), - MX27_PAD_SD2_D1 = PAD_ID(PB, 5), - MX27_PAD_SD2_D2 = PAD_ID(PB, 6), - MX27_PAD_SD2_D3 = PAD_ID(PB, 7), - MX27_PAD_SD2_CMD = PAD_ID(PB, 8), - MX27_PAD_SD2_CLK = PAD_ID(PB, 9), - MX27_PAD_CSI_D0 = PAD_ID(PB, 10), - MX27_PAD_CSI_D1 = PAD_ID(PB, 11), - MX27_PAD_CSI_D2 = PAD_ID(PB, 12), - MX27_PAD_CSI_D3 = PAD_ID(PB, 13), - MX27_PAD_CSI_D4 = PAD_ID(PB, 14), - MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), - MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), - MX27_PAD_CSI_D5 = PAD_ID(PB, 17), - MX27_PAD_CSI_D6 = PAD_ID(PB, 18), - MX27_PAD_CSI_D7 = PAD_ID(PB, 19), - MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), - MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), - MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), - MX27_PAD_USB_PWR = PAD_ID(PB, 23), - MX27_PAD_USB_OC_B = PAD_ID(PB, 24), - MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), - MX27_PAD_USBH1_FS = PAD_ID(PB, 26), - MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), - MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), - MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), - MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), - MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), + MX27_PAD_SD2_D0 = PAD_ID(MX27_PB, 4), + MX27_PAD_SD2_D1 = PAD_ID(MX27_PB, 5), + MX27_PAD_SD2_D2 = PAD_ID(MX27_PB, 6), + MX27_PAD_SD2_D3 = PAD_ID(MX27_PB, 7), + MX27_PAD_SD2_CMD = PAD_ID(MX27_PB, 8), + MX27_PAD_SD2_CLK = PAD_ID(MX27_PB, 9), + MX27_PAD_CSI_D0 = PAD_ID(MX27_PB, 10), + MX27_PAD_CSI_D1 = PAD_ID(MX27_PB, 11), + MX27_PAD_CSI_D2 = PAD_ID(MX27_PB, 12), + MX27_PAD_CSI_D3 = PAD_ID(MX27_PB, 13), + MX27_PAD_CSI_D4 = PAD_ID(MX27_PB, 14), + MX27_PAD_CSI_MCLK = PAD_ID(MX27_PB, 15), + MX27_PAD_CSI_PIXCLK = PAD_ID(MX27_PB, 16), + MX27_PAD_CSI_D5 = PAD_ID(MX27_PB, 17), + MX27_PAD_CSI_D6 = PAD_ID(MX27_PB, 18), + MX27_PAD_CSI_D7 = PAD_ID(MX27_PB, 19), + MX27_PAD_CSI_VSYNC = PAD_ID(MX27_PB, 20), + MX27_PAD_CSI_HSYNC = PAD_ID(MX27_PB, 21), + MX27_PAD_USBH1_SUSP = PAD_ID(MX27_PB, 22), + MX27_PAD_USB_PWR = PAD_ID(MX27_PB, 23), + MX27_PAD_USB_OC_B = PAD_ID(MX27_PB, 24), + MX27_PAD_USBH1_RCV = PAD_ID(MX27_PB, 25), + MX27_PAD_USBH1_FS = PAD_ID(MX27_PB, 26), + MX27_PAD_USBH1_OE_B = PAD_ID(MX27_PB, 27), + MX27_PAD_USBH1_TXDM = PAD_ID(MX27_PB, 28), + MX27_PAD_USBH1_TXDP = PAD_ID(MX27_PB, 29), + MX27_PAD_USBH1_RXDM = PAD_ID(MX27_PB, 30), + MX27_PAD_USBH1_RXDP = PAD_ID(MX27_PB, 31), - MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), - MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), - MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), - MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), - MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), - MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), - MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), - MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), - MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), - MX27_PAD_TOUT = PAD_ID(PC, 14), - MX27_PAD_TIN = PAD_ID(PC, 15), - MX27_PAD_SSI4_FS = PAD_ID(PC, 16), - MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), - MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), - MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), - MX27_PAD_SSI1_FS = PAD_ID(PC, 20), - MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), - MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), - MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), - MX27_PAD_SSI2_FS = PAD_ID(PC, 24), - MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), - MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), - MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), - MX27_PAD_SSI3_FS = PAD_ID(PC, 28), - MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), - MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), - MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), + MX27_PAD_I2C2_SDA = PAD_ID(MX27_PC, 5), + MX27_PAD_I2C2_SCL = PAD_ID(MX27_PC, 6), + MX27_PAD_USBOTG_DATA5 = PAD_ID(MX27_PC, 7), + MX27_PAD_USBOTG_DATA6 = PAD_ID(MX27_PC, 8), + MX27_PAD_USBOTG_DATA0 = PAD_ID(MX27_PC, 9), + MX27_PAD_USBOTG_DATA2 = PAD_ID(MX27_PC, 10), + MX27_PAD_USBOTG_DATA1 = PAD_ID(MX27_PC, 11), + MX27_PAD_USBOTG_DATA4 = PAD_ID(MX27_PC, 12), + MX27_PAD_USBOTG_DATA3 = PAD_ID(MX27_PC, 13), + MX27_PAD_TOUT = PAD_ID(MX27_PC, 14), + MX27_PAD_TIN = PAD_ID(MX27_PC, 15), + MX27_PAD_SSI4_FS = PAD_ID(MX27_PC, 16), + MX27_PAD_SSI4_RXDAT = PAD_ID(MX27_PC, 17), + MX27_PAD_SSI4_TXDAT = PAD_ID(MX27_PC, 18), + MX27_PAD_SSI4_CLK = PAD_ID(MX27_PC, 19), + MX27_PAD_SSI1_FS = PAD_ID(MX27_PC, 20), + MX27_PAD_SSI1_RXDAT = PAD_ID(MX27_PC, 21), + MX27_PAD_SSI1_TXDAT = PAD_ID(MX27_PC, 22), + MX27_PAD_SSI1_CLK = PAD_ID(MX27_PC, 23), + MX27_PAD_SSI2_FS = PAD_ID(MX27_PC, 24), + MX27_PAD_SSI2_RXDAT = PAD_ID(MX27_PC, 25), + MX27_PAD_SSI2_TXDAT = PAD_ID(MX27_PC, 26), + MX27_PAD_SSI2_CLK = PAD_ID(MX27_PC, 27), + MX27_PAD_SSI3_FS = PAD_ID(MX27_PC, 28), + MX27_PAD_SSI3_RXDAT = PAD_ID(MX27_PC, 29), + MX27_PAD_SSI3_TXDAT = PAD_ID(MX27_PC, 30), + MX27_PAD_SSI3_CLK = PAD_ID(MX27_PC, 31), - MX27_PAD_SD3_CMD = PAD_ID(PD, 0), - MX27_PAD_SD3_CLK = PAD_ID(PD, 1), - MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), - MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), - MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), - MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), - MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), - MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), - MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), - MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), - MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), - MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), - MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), - MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), - MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), - MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), - MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), - MX27_PAD_I2C_DATA = PAD_ID(PD, 17), - MX27_PAD_I2C_CLK = PAD_ID(PD, 18), - MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), - MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), - MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), - MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), - MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), - MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), - MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), - MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), - MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), - MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), - MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), - MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), - MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + MX27_PAD_SD3_CMD = PAD_ID(MX27_PD, 0), + MX27_PAD_SD3_CLK = PAD_ID(MX27_PD, 1), + MX27_PAD_ATA_DATA0 = PAD_ID(MX27_PD, 2), + MX27_PAD_ATA_DATA1 = PAD_ID(MX27_PD, 3), + MX27_PAD_ATA_DATA2 = PAD_ID(MX27_PD, 4), + MX27_PAD_ATA_DATA3 = PAD_ID(MX27_PD, 5), + MX27_PAD_ATA_DATA4 = PAD_ID(MX27_PD, 6), + MX27_PAD_ATA_DATA5 = PAD_ID(MX27_PD, 7), + MX27_PAD_ATA_DATA6 = PAD_ID(MX27_PD, 8), + MX27_PAD_ATA_DATA7 = PAD_ID(MX27_PD, 9), + MX27_PAD_ATA_DATA8 = PAD_ID(MX27_PD, 10), + MX27_PAD_ATA_DATA9 = PAD_ID(MX27_PD, 11), + MX27_PAD_ATA_DATA10 = PAD_ID(MX27_PD, 12), + MX27_PAD_ATA_DATA11 = PAD_ID(MX27_PD, 13), + MX27_PAD_ATA_DATA12 = PAD_ID(MX27_PD, 14), + MX27_PAD_ATA_DATA13 = PAD_ID(MX27_PD, 15), + MX27_PAD_ATA_DATA14 = PAD_ID(MX27_PD, 16), + MX27_PAD_I2C_DATA = PAD_ID(MX27_PD, 17), + MX27_PAD_I2C_CLK = PAD_ID(MX27_PD, 18), + MX27_PAD_CSPI2_SS2 = PAD_ID(MX27_PD, 19), + MX27_PAD_CSPI2_SS1 = PAD_ID(MX27_PD, 20), + MX27_PAD_CSPI2_SS0 = PAD_ID(MX27_PD, 21), + MX27_PAD_CSPI2_SCLK = PAD_ID(MX27_PD, 22), + MX27_PAD_CSPI2_MISO = PAD_ID(MX27_PD, 23), + MX27_PAD_CSPI2_MOSI = PAD_ID(MX27_PD, 24), + MX27_PAD_CSPI1_RDY = PAD_ID(MX27_PD, 25), + MX27_PAD_CSPI1_SS2 = PAD_ID(MX27_PD, 26), + MX27_PAD_CSPI1_SS1 = PAD_ID(MX27_PD, 27), + MX27_PAD_CSPI1_SS0 = PAD_ID(MX27_PD, 28), + MX27_PAD_CSPI1_SCLK = PAD_ID(MX27_PD, 29), + MX27_PAD_CSPI1_MISO = PAD_ID(MX27_PD, 30), + MX27_PAD_CSPI1_MOSI = PAD_ID(MX27_PD, 31), - MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), - MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), - MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), - MX27_PAD_UART2_CTS = PAD_ID(PE, 3), - MX27_PAD_UART2_RTS = PAD_ID(PE, 4), - MX27_PAD_PWMO = PAD_ID(PE, 5), - MX27_PAD_UART2_TXD = PAD_ID(PE, 6), - MX27_PAD_UART2_RXD = PAD_ID(PE, 7), - MX27_PAD_UART3_TXD = PAD_ID(PE, 8), - MX27_PAD_UART3_RXD = PAD_ID(PE, 9), - MX27_PAD_UART3_CTS = PAD_ID(PE, 10), - MX27_PAD_UART3_RTS = PAD_ID(PE, 11), - MX27_PAD_UART1_TXD = PAD_ID(PE, 12), - MX27_PAD_UART1_RXD = PAD_ID(PE, 13), - MX27_PAD_UART1_CTS = PAD_ID(PE, 14), - MX27_PAD_UART1_RTS = PAD_ID(PE, 15), - MX27_PAD_RTCK = PAD_ID(PE, 16), - MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), - MX27_PAD_SD1_D0 = PAD_ID(PE, 18), - MX27_PAD_SD1_D1 = PAD_ID(PE, 19), - MX27_PAD_SD1_D2 = PAD_ID(PE, 20), - MX27_PAD_SD1_D3 = PAD_ID(PE, 21), - MX27_PAD_SD1_CMD = PAD_ID(PE, 22), - MX27_PAD_SD1_CLK = PAD_ID(PE, 23), - MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), - MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), + MX27_PAD_USBOTG_NXT = PAD_ID(MX27_PE, 0), + MX27_PAD_USBOTG_STP = PAD_ID(MX27_PE, 1), + MX27_PAD_USBOTG_DIR = PAD_ID(MX27_PE, 2), + MX27_PAD_UART2_CTS = PAD_ID(MX27_PE, 3), + MX27_PAD_UART2_RTS = PAD_ID(MX27_PE, 4), + MX27_PAD_PWMO = PAD_ID(MX27_PE, 5), + MX27_PAD_UART2_TXD = PAD_ID(MX27_PE, 6), + MX27_PAD_UART2_RXD = PAD_ID(MX27_PE, 7), + MX27_PAD_UART3_TXD = PAD_ID(MX27_PE, 8), + MX27_PAD_UART3_RXD = PAD_ID(MX27_PE, 9), + MX27_PAD_UART3_CTS = PAD_ID(MX27_PE, 10), + MX27_PAD_UART3_RTS = PAD_ID(MX27_PE, 11), + MX27_PAD_UART1_TXD = PAD_ID(MX27_PE, 12), + MX27_PAD_UART1_RXD = PAD_ID(MX27_PE, 13), + MX27_PAD_UART1_CTS = PAD_ID(MX27_PE, 14), + MX27_PAD_UART1_RTS = PAD_ID(MX27_PE, 15), + MX27_PAD_RTCK = PAD_ID(MX27_PE, 16), + MX27_PAD_RESET_OUT_B = PAD_ID(MX27_PE, 17), + MX27_PAD_SD1_D0 = PAD_ID(MX27_PE, 18), + MX27_PAD_SD1_D1 = PAD_ID(MX27_PE, 19), + MX27_PAD_SD1_D2 = PAD_ID(MX27_PE, 20), + MX27_PAD_SD1_D3 = PAD_ID(MX27_PE, 21), + MX27_PAD_SD1_CMD = PAD_ID(MX27_PE, 22), + MX27_PAD_SD1_CLK = PAD_ID(MX27_PE, 23), + MX27_PAD_USBOTG_CLK = PAD_ID(MX27_PE, 24), + MX27_PAD_USBOTG_DATA7 = PAD_ID(MX27_PE, 25), - MX27_PAD_NFRB = PAD_ID(PF, 0), - MX27_PAD_NFCLE = PAD_ID(PF, 1), - MX27_PAD_NFWP_B = PAD_ID(PF, 2), - MX27_PAD_NFCE_B = PAD_ID(PF, 3), - MX27_PAD_NFALE = PAD_ID(PF, 4), - MX27_PAD_NFRE_B = PAD_ID(PF, 5), - MX27_PAD_NFWE_B = PAD_ID(PF, 6), - MX27_PAD_PC_POE = PAD_ID(PF, 7), - MX27_PAD_PC_RW_B = PAD_ID(PF, 8), - MX27_PAD_IOIS16 = PAD_ID(PF, 9), - MX27_PAD_PC_RST = PAD_ID(PF, 10), - MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), - MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), - MX27_PAD_PC_VS2 = PAD_ID(PF, 13), - MX27_PAD_PC_VS1 = PAD_ID(PF, 14), - MX27_PAD_CLKO = PAD_ID(PF, 15), - MX27_PAD_PC_PWRON = PAD_ID(PF, 16), - MX27_PAD_PC_READY = PAD_ID(PF, 17), - MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), - MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), - MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), - MX27_PAD_CS4_B = PAD_ID(PF, 21), - MX27_PAD_CS5_B = PAD_ID(PF, 22), - MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), + MX27_PAD_NFRB = PAD_ID(MX27_PF, 0), + MX27_PAD_NFCLE = PAD_ID(MX27_PF, 1), + MX27_PAD_NFWP_B = PAD_ID(MX27_PF, 2), + MX27_PAD_NFCE_B = PAD_ID(MX27_PF, 3), + MX27_PAD_NFALE = PAD_ID(MX27_PF, 4), + MX27_PAD_NFRE_B = PAD_ID(MX27_PF, 5), + MX27_PAD_NFWE_B = PAD_ID(MX27_PF, 6), + MX27_PAD_PC_POE = PAD_ID(MX27_PF, 7), + MX27_PAD_PC_RW_B = PAD_ID(MX27_PF, 8), + MX27_PAD_IOIS16 = PAD_ID(MX27_PF, 9), + MX27_PAD_PC_RST = PAD_ID(MX27_PF, 10), + MX27_PAD_PC_BVD2 = PAD_ID(MX27_PF, 11), + MX27_PAD_PC_BVD1 = PAD_ID(MX27_PF, 12), + MX27_PAD_PC_VS2 = PAD_ID(MX27_PF, 13), + MX27_PAD_PC_VS1 = PAD_ID(MX27_PF, 14), + MX27_PAD_CLKO = PAD_ID(MX27_PF, 15), + MX27_PAD_PC_PWRON = PAD_ID(MX27_PF, 16), + MX27_PAD_PC_READY = PAD_ID(MX27_PF, 17), + MX27_PAD_PC_WAIT_B = PAD_ID(MX27_PF, 18), + MX27_PAD_PC_CD2_B = PAD_ID(MX27_PF, 19), + MX27_PAD_PC_CD1_B = PAD_ID(MX27_PF, 20), + MX27_PAD_CS4_B = PAD_ID(MX27_PF, 21), + MX27_PAD_CS5_B = PAD_ID(MX27_PF, 22), + MX27_PAD_ATA_DATA15 = PAD_ID(MX27_PF, 23), }; /* Pad names for the pinmux subsystem */ diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 067b0d344f0e..9f938718927b 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1792,7 +1792,7 @@ MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); static struct platform_driver chv_pinctrl_driver = { .probe = chv_pinctrl_probe, - .remove_new = chv_pinctrl_remove, + .remove = chv_pinctrl_remove, .driver = { .name = "cherryview-pinctrl", .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index 1678634ebc06..3e45d7fb003a 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -264,6 +264,43 @@ static const struct intel_pinctrl_soc_data ehl_community1_soc_data = { .ncommunities = ARRAY_SIZE(ehl_community1), }; +static const struct pinctrl_pin_desc ehl_community2_pins[] = { + /* DSW */ + PINCTRL_PIN(0, "BATLOWB"), + PINCTRL_PIN(1, "ACPRESENT"), + PINCTRL_PIN(2, "LAN_WAKEB"), + PINCTRL_PIN(3, "PWRBTNB"), + PINCTRL_PIN(4, "SLP_S3B"), + PINCTRL_PIN(5, "SLP_S4B"), + PINCTRL_PIN(6, "SLP_AB"), + PINCTRL_PIN(7, "GPD_7"), + PINCTRL_PIN(8, "SUSCLK"), + PINCTRL_PIN(9, "SLP_WLANB"), + PINCTRL_PIN(10, "SLP_S5B"), + PINCTRL_PIN(11, "LANPHYPC"), + PINCTRL_PIN(12, "INPUT3VSEL"), + PINCTRL_PIN(13, "SLP_LANB"), + PINCTRL_PIN(14, "SLP_SUSB"), + PINCTRL_PIN(15, "WAKEB"), + PINCTRL_PIN(16, "DRAM_RESETB"), +}; + +static const struct intel_padgroup ehl_community2_gpps[] = { + EHL_GPP(0, 0, 16), /* DSW */ +}; + +static const struct intel_community ehl_community2[] = { + EHL_COMMUNITY(0, 0, 16, ehl_community2_gpps), +}; + +static const struct intel_pinctrl_soc_data ehl_community2_soc_data = { + .uid = "2", + .pins = ehl_community2_pins, + .npins = ARRAY_SIZE(ehl_community2_pins), + .communities = ehl_community2, + .ncommunities = ARRAY_SIZE(ehl_community2), +}; + static const struct pinctrl_pin_desc ehl_community3_pins[] = { /* CPU */ PINCTRL_PIN(0, "HDACPU_SDI"), @@ -474,6 +511,7 @@ static const struct intel_pinctrl_soc_data ehl_community5_soc_data = { static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = { &ehl_community0_soc_data, &ehl_community1_soc_data, + &ehl_community2_soc_data, &ehl_community3_soc_data, &ehl_community4_soc_data, &ehl_community5_soc_data, diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 928607a21d36..04b438f63ccb 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -85,6 +85,18 @@ #define PADCFG1_TERM_UP BIT(13) #define PADCFG1_TERM_SHIFT 10 #define PADCFG1_TERM_MASK GENMASK(12, 10) +/* + * Bit 0 Bit 1 Bit 2 Value, Ohms + * + * 0 0 0 - + * 0 0 1 20000 + * 0 1 0 5000 + * 0 1 1 ~4000 + * 1 0 0 1000 (if supported) + * 1 0 1 ~952 (if supported) + * 1 1 0 ~833 (if supported) + * 1 1 1 ~800 (if supported) + */ #define PADCFG1_TERM_20K BIT(2) #define PADCFG1_TERM_5K BIT(1) #define PADCFG1_TERM_4K (BIT(2) | BIT(1)) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 7af287252834..a417a031659c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST + depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -126,6 +126,21 @@ config PINCTRL_MT8127 select PINCTRL_MTK # For ARMv8 SoCs +config PINCTRL_AIROHA + tristate "Airoha EN7581 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP_MMIO + help + Say yes here to support pin controller and gpio driver + on Airoha EN7581 SoC. + config PINCTRL_MT2712 bool "MediaTek MT2712 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 680f7e8526e0..1405d434218e 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers +obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c new file mode 100644 index 000000000000..547a798b71c8 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -0,0 +1,2971 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + */ + +#include <dt-bindings/pinctrl/mt65xx.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define PINCTRL_PIN_GROUP(id) \ + PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins)) + +#define PINCTRL_FUNC_DESC(id) \ + { \ + .desc = { \ + .func = { \ + .name = #id, \ + .groups = id##_groups, \ + .ngroups = ARRAY_SIZE(id##_groups), \ + } \ + }, \ + .groups = id##_func_group, \ + .group_size = ARRAY_SIZE(id##_func_group), \ + } + +#define PINCTRL_CONF_DESC(p, offset, mask) \ + { \ + .pin = p, \ + .reg = { offset, mask }, \ + } + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_PCIE_RESET2_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY4_LED_MAP BIT(18) +#define LAN4_PHY2_LED_MAP BIT(17) +#define LAN4_PHY1_LED_MAP BIT(16) +#define LAN4_PHY0_LED_MAP 0 +#define LAN4_PHY3_LED_MAP GENMASK(17, 16) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY4_LED_MAP BIT(14) +#define LAN3_PHY2_LED_MAP BIT(13) +#define LAN3_PHY1_LED_MAP BIT(12) +#define LAN3_PHY0_LED_MAP 0 +#define LAN3_PHY3_LED_MAP GENMASK(13, 12) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY4_LED_MAP BIT(12) +#define LAN2_PHY2_LED_MAP BIT(11) +#define LAN2_PHY1_LED_MAP BIT(10) +#define LAN2_PHY0_LED_MAP 0 +#define LAN2_PHY3_LED_MAP GENMASK(11, 10) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY4_LED_MAP BIT(6) +#define LAN1_PHY2_LED_MAP BIT(5) +#define LAN1_PHY1_LED_MAP BIT(4) +#define LAN1_PHY0_LED_MAP 0 +#define LAN1_PHY3_LED_MAP GENMASK(5, 4) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY4_LED_MAP BIT(3) +#define LAN0_PHY2_LED_MAP BIT(2) +#define LAN0_PHY1_LED_MAP BIT(1) +#define LAN0_PHY0_LED_MAP 0 +#define LAN0_PHY3_LED_MAP GENMASK(2, 1) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE2_RESET_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE2_RESET_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE2_RESET_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE2_RESET_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE2_RESET_OD_MASK BIT(2) +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* GPIOs */ +#define REG_GPIO_CTRL 0x0000 +#define REG_GPIO_DATA 0x0004 +#define REG_GPIO_INT 0x0008 +#define REG_GPIO_INT_EDGE 0x000c +#define REG_GPIO_INT_LEVEL 0x0010 +#define REG_GPIO_OE 0x0014 +#define REG_GPIO_CTRL1 0x0020 + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_DATA1 0x0070 +#define REG_GPIO_OE1 0x0078 +#define REG_GPIO_INT1 0x007c +#define REG_GPIO_INT_EDGE1 0x0080 +#define REG_GPIO_INT_EDGE2 0x0084 +#define REG_GPIO_INT_EDGE3 0x0088 +#define REG_GPIO_INT_LEVEL1 0x008c +#define REG_GPIO_INT_LEVEL2 0x0090 +#define REG_GPIO_INT_LEVEL3 0x0094 + +#define AIROHA_NUM_PINS 64 +#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) +#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) + +static const u32 gpio_data_regs[] = { + REG_GPIO_DATA, + REG_GPIO_DATA1 +}; + +static const u32 gpio_out_regs[] = { + REG_GPIO_OE, + REG_GPIO_OE1 +}; + +static const u32 gpio_dir_regs[] = { + REG_GPIO_CTRL, + REG_GPIO_CTRL1, + REG_GPIO_CTRL2, + REG_GPIO_CTRL3 +}; + +static const u32 irq_status_regs[] = { + REG_GPIO_INT, + REG_GPIO_INT1 +}; + +static const u32 irq_level_regs[] = { + REG_GPIO_INT_LEVEL, + REG_GPIO_INT_LEVEL1, + REG_GPIO_INT_LEVEL2, + REG_GPIO_INT_LEVEL3 +}; + +static const u32 irq_edge_regs[] = { + REG_GPIO_INT_EDGE, + REG_GPIO_INT_EDGE1, + REG_GPIO_INT_EDGE2, + REG_GPIO_INT_EDGE3 +}; + +struct airoha_pinctrl_reg { + u32 offset; + u32 mask; +}; + +enum airoha_pinctrl_mux_func { + AIROHA_FUNC_MUX, + AIROHA_FUNC_PWM_MUX, + AIROHA_FUNC_PWM_EXT_MUX, +}; + +struct airoha_pinctrl_func_group { + const char *name; + struct { + enum airoha_pinctrl_mux_func mux; + u32 offset; + u32 mask; + u32 val; + } regmap[2]; + int regmap_size; +}; + +struct airoha_pinctrl_func { + const struct function_desc desc; + const struct airoha_pinctrl_func_group *groups; + u8 group_size; +}; + +struct airoha_pinctrl_conf { + u32 pin; + struct airoha_pinctrl_reg reg; +}; + +struct airoha_pinctrl_gpiochip { + struct gpio_chip chip; + + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; + + u32 irq_type[AIROHA_NUM_PINS]; +}; + +struct airoha_pinctrl { + struct pinctrl_dev *ctrl; + + struct regmap *chip_scu; + struct regmap *regmap; + + struct airoha_pinctrl_gpiochip gpiochip; +}; + +static struct pinctrl_pin_desc airoha_pinctrl_pins[] = { + PINCTRL_PIN(0, "uart1_txd"), + PINCTRL_PIN(1, "uart1_rxd"), + PINCTRL_PIN(2, "i2c_scl"), + PINCTRL_PIN(3, "i2c_sda"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(13, "gpio0"), + PINCTRL_PIN(14, "gpio1"), + PINCTRL_PIN(15, "gpio2"), + PINCTRL_PIN(16, "gpio3"), + PINCTRL_PIN(17, "gpio4"), + PINCTRL_PIN(18, "gpio5"), + PINCTRL_PIN(19, "gpio6"), + PINCTRL_PIN(20, "gpio7"), + PINCTRL_PIN(21, "gpio8"), + PINCTRL_PIN(22, "gpio9"), + PINCTRL_PIN(23, "gpio10"), + PINCTRL_PIN(24, "gpio11"), + PINCTRL_PIN(25, "gpio12"), + PINCTRL_PIN(26, "gpio13"), + PINCTRL_PIN(27, "gpio14"), + PINCTRL_PIN(28, "gpio15"), + PINCTRL_PIN(29, "gpio16"), + PINCTRL_PIN(30, "gpio17"), + PINCTRL_PIN(31, "gpio18"), + PINCTRL_PIN(32, "gpio19"), + PINCTRL_PIN(33, "gpio20"), + PINCTRL_PIN(34, "gpio21"), + PINCTRL_PIN(35, "gpio22"), + PINCTRL_PIN(36, "gpio23"), + PINCTRL_PIN(37, "gpio24"), + PINCTRL_PIN(38, "gpio25"), + PINCTRL_PIN(39, "gpio26"), + PINCTRL_PIN(40, "gpio27"), + PINCTRL_PIN(41, "gpio28"), + PINCTRL_PIN(42, "gpio29"), + PINCTRL_PIN(43, "gpio30"), + PINCTRL_PIN(44, "gpio31"), + PINCTRL_PIN(45, "gpio32"), + PINCTRL_PIN(46, "gpio33"), + PINCTRL_PIN(47, "gpio34"), + PINCTRL_PIN(48, "gpio35"), + PINCTRL_PIN(49, "gpio36"), + PINCTRL_PIN(50, "gpio37"), + PINCTRL_PIN(51, "gpio38"), + PINCTRL_PIN(52, "gpio39"), + PINCTRL_PIN(53, "gpio40"), + PINCTRL_PIN(54, "gpio41"), + PINCTRL_PIN(55, "gpio42"), + PINCTRL_PIN(56, "gpio43"), + PINCTRL_PIN(57, "gpio44"), + PINCTRL_PIN(58, "gpio45"), + PINCTRL_PIN(59, "gpio46"), + PINCTRL_PIN(61, "pcie_reset0"), + PINCTRL_PIN(62, "pcie_reset1"), + PINCTRL_PIN(63, "pcie_reset2"), +}; + +static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int pon_tod_1pps_pins[] = { 46 }; +static const int gsw_tod_1pps_pins[] = { 46 }; +static const int sipo_pins[] = { 16, 17 }; +static const int sipo_rclk_pins[] = { 16, 17, 43 }; +static const int mdio_pins[] = { 14, 15 }; +static const int uart2_pins[] = { 48, 55 }; +static const int uart2_cts_rts_pins[] = { 46, 47 }; +static const int hsuart_pins[] = { 28, 29 }; +static const int hsuart_cts_rts_pins[] = { 26, 27 }; +static const int uart4_pins[] = { 38, 39 }; +static const int uart5_pins[] = { 18, 19 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int i2s_pins[] = { 26, 27, 28, 29 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 18, 19, 20, 21 }; +static const int spi_quad_pins[] = { 32, 33 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_cs1_pins[] = { 34 }; +static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int pcm_spi_int_pins[] = { 14 }; +static const int pcm_spi_rst_pins[] = { 15 }; +static const int pcm_spi_cs1_pins[] = { 43 }; +static const int pcm_spi_cs2_pins[] = { 40 }; +static const int pcm_spi_cs2_p128_pins[] = { 40 }; +static const int pcm_spi_cs2_p156_pins[] = { 40 }; +static const int pcm_spi_cs3_pins[] = { 41 }; +static const int pcm_spi_cs4_pins[] = { 42 }; +static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; +static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; +static const int gpio0_pins[] = { 13 }; +static const int gpio1_pins[] = { 14 }; +static const int gpio2_pins[] = { 15 }; +static const int gpio3_pins[] = { 16 }; +static const int gpio4_pins[] = { 17 }; +static const int gpio5_pins[] = { 18 }; +static const int gpio6_pins[] = { 19 }; +static const int gpio7_pins[] = { 20 }; +static const int gpio8_pins[] = { 21 }; +static const int gpio9_pins[] = { 22 }; +static const int gpio10_pins[] = { 23 }; +static const int gpio11_pins[] = { 24 }; +static const int gpio12_pins[] = { 25 }; +static const int gpio13_pins[] = { 26 }; +static const int gpio14_pins[] = { 27 }; +static const int gpio15_pins[] = { 28 }; +static const int gpio16_pins[] = { 29 }; +static const int gpio17_pins[] = { 30 }; +static const int gpio18_pins[] = { 31 }; +static const int gpio19_pins[] = { 32 }; +static const int gpio20_pins[] = { 33 }; +static const int gpio21_pins[] = { 34 }; +static const int gpio22_pins[] = { 35 }; +static const int gpio23_pins[] = { 36 }; +static const int gpio24_pins[] = { 37 }; +static const int gpio25_pins[] = { 38 }; +static const int gpio26_pins[] = { 39 }; +static const int gpio27_pins[] = { 40 }; +static const int gpio28_pins[] = { 41 }; +static const int gpio29_pins[] = { 42 }; +static const int gpio30_pins[] = { 43 }; +static const int gpio31_pins[] = { 44 }; +static const int gpio33_pins[] = { 46 }; +static const int gpio34_pins[] = { 47 }; +static const int gpio35_pins[] = { 48 }; +static const int gpio36_pins[] = { 49 }; +static const int gpio37_pins[] = { 50 }; +static const int gpio38_pins[] = { 51 }; +static const int gpio39_pins[] = { 52 }; +static const int gpio40_pins[] = { 53 }; +static const int gpio41_pins[] = { 54 }; +static const int gpio42_pins[] = { 55 }; +static const int gpio43_pins[] = { 56 }; +static const int gpio44_pins[] = { 57 }; +static const int gpio45_pins[] = { 58 }; +static const int gpio46_pins[] = { 59 }; +static const int pcie_reset0_pins[] = { 61 }; +static const int pcie_reset1_pins[] = { 62 }; +static const int pcie_reset2_pins[] = { 63 }; + +static const struct pingroup airoha_pinctrl_groups[] = { + PINCTRL_PIN_GROUP(pon), + PINCTRL_PIN_GROUP(pon_tod_1pps), + PINCTRL_PIN_GROUP(gsw_tod_1pps), + PINCTRL_PIN_GROUP(sipo), + PINCTRL_PIN_GROUP(sipo_rclk), + PINCTRL_PIN_GROUP(mdio), + PINCTRL_PIN_GROUP(uart2), + PINCTRL_PIN_GROUP(uart2_cts_rts), + PINCTRL_PIN_GROUP(hsuart), + PINCTRL_PIN_GROUP(hsuart_cts_rts), + PINCTRL_PIN_GROUP(uart4), + PINCTRL_PIN_GROUP(uart5), + PINCTRL_PIN_GROUP(i2c0), + PINCTRL_PIN_GROUP(i2c1), + PINCTRL_PIN_GROUP(jtag_udi), + PINCTRL_PIN_GROUP(jtag_dfd), + PINCTRL_PIN_GROUP(i2s), + PINCTRL_PIN_GROUP(pcm1), + PINCTRL_PIN_GROUP(pcm2), + PINCTRL_PIN_GROUP(spi), + PINCTRL_PIN_GROUP(spi_quad), + PINCTRL_PIN_GROUP(spi_cs1), + PINCTRL_PIN_GROUP(pcm_spi), + PINCTRL_PIN_GROUP(pcm_spi_int), + PINCTRL_PIN_GROUP(pcm_spi_rst), + PINCTRL_PIN_GROUP(pcm_spi_cs1), + PINCTRL_PIN_GROUP(pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP(pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP(pcm_spi_cs2), + PINCTRL_PIN_GROUP(pcm_spi_cs3), + PINCTRL_PIN_GROUP(pcm_spi_cs4), + PINCTRL_PIN_GROUP(emmc), + PINCTRL_PIN_GROUP(pnand), + PINCTRL_PIN_GROUP(gpio0), + PINCTRL_PIN_GROUP(gpio1), + PINCTRL_PIN_GROUP(gpio2), + PINCTRL_PIN_GROUP(gpio3), + PINCTRL_PIN_GROUP(gpio4), + PINCTRL_PIN_GROUP(gpio5), + PINCTRL_PIN_GROUP(gpio6), + PINCTRL_PIN_GROUP(gpio7), + PINCTRL_PIN_GROUP(gpio8), + PINCTRL_PIN_GROUP(gpio9), + PINCTRL_PIN_GROUP(gpio10), + PINCTRL_PIN_GROUP(gpio11), + PINCTRL_PIN_GROUP(gpio12), + PINCTRL_PIN_GROUP(gpio13), + PINCTRL_PIN_GROUP(gpio14), + PINCTRL_PIN_GROUP(gpio15), + PINCTRL_PIN_GROUP(gpio16), + PINCTRL_PIN_GROUP(gpio17), + PINCTRL_PIN_GROUP(gpio18), + PINCTRL_PIN_GROUP(gpio19), + PINCTRL_PIN_GROUP(gpio20), + PINCTRL_PIN_GROUP(gpio21), + PINCTRL_PIN_GROUP(gpio22), + PINCTRL_PIN_GROUP(gpio23), + PINCTRL_PIN_GROUP(gpio24), + PINCTRL_PIN_GROUP(gpio25), + PINCTRL_PIN_GROUP(gpio26), + PINCTRL_PIN_GROUP(gpio27), + PINCTRL_PIN_GROUP(gpio28), + PINCTRL_PIN_GROUP(gpio29), + PINCTRL_PIN_GROUP(gpio30), + PINCTRL_PIN_GROUP(gpio31), + PINCTRL_PIN_GROUP(gpio33), + PINCTRL_PIN_GROUP(gpio34), + PINCTRL_PIN_GROUP(gpio35), + PINCTRL_PIN_GROUP(gpio36), + PINCTRL_PIN_GROUP(gpio37), + PINCTRL_PIN_GROUP(gpio38), + PINCTRL_PIN_GROUP(gpio39), + PINCTRL_PIN_GROUP(gpio40), + PINCTRL_PIN_GROUP(gpio41), + PINCTRL_PIN_GROUP(gpio42), + PINCTRL_PIN_GROUP(gpio43), + PINCTRL_PIN_GROUP(gpio44), + PINCTRL_PIN_GROUP(gpio45), + PINCTRL_PIN_GROUP(gpio46), + PINCTRL_PIN_GROUP(pcie_reset0), + PINCTRL_PIN_GROUP(pcie_reset1), + PINCTRL_PIN_GROUP(pcie_reset2), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", + "hsuart_cts_rts", "uart4", + "uart5" }; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", + "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", + "pcm_spi_cs2_p128", + "pcm_spi_cs3", "pcm_spi_cs4" }; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", + "pcie_reset2" }; +static const char *const pwm_groups[] = { "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio4", "gpio5", + "gpio6", "gpio7", + "gpio8", "gpio9", + "gpio10", "gpio11", + "gpio12", "gpio13", + "gpio14", "gpio15", + "gpio16", "gpio17", + "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio22", "gpio23", + "gpio24", "gpio25", + "gpio26", "gpio27", + "gpio28", "gpio29", + "gpio30", "gpio31", + "gpio36", "gpio37", + "gpio38", "gpio39", + "gpio40", "gpio41", + "gpio42", "gpio43", + "gpio44", "gpio45", + "gpio46", "gpio47" }; +static const char *const phy1_led0_groups[] = { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy2_led0_groups[] = { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy3_led0_groups[] = { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy4_led0_groups[] = { "gpio33", "gpio34", + "gpio35", "gpio42" }; +static const char *const phy1_led1_groups[] = { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy2_led1_groups[] = { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy3_led1_groups[] = { "gpio43", "gpio44", + "gpio45", "gpio46" }; +static const char *const phy4_led1_groups[] = { "gpio43", "gpio44", + "gpio45", "gpio46" }; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE, + GPIO_MDC_IO_MASTER_MODE_MODE + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + GPIO_PCIE_RESET0_MASK + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + GPIO_PCIE_RESET1_MASK + }, + .regmap_size = 1, + }, { + .name = "pcie_reset2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET2_MASK, + GPIO_PCIE_RESET2_MASK + }, + .regmap_size = 1, + }, +}; + +/* PWM */ +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + { + .name = "gpio0", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO0_FLASH_MODE_CFG, + GPIO0_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio1", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO1_FLASH_MODE_CFG, + GPIO1_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio2", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO2_FLASH_MODE_CFG, + GPIO2_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio3", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO3_FLASH_MODE_CFG, + GPIO3_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio4", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO4_FLASH_MODE_CFG, + GPIO4_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio5", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO5_FLASH_MODE_CFG, + GPIO5_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio6", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO6_FLASH_MODE_CFG, + GPIO6_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio7", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO7_FLASH_MODE_CFG, + GPIO7_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio8", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO8_FLASH_MODE_CFG, + GPIO8_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio9", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO9_FLASH_MODE_CFG, + GPIO9_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio10", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO10_FLASH_MODE_CFG, + GPIO10_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio11", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO11_FLASH_MODE_CFG, + GPIO11_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio12", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO12_FLASH_MODE_CFG, + GPIO12_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio13", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO13_FLASH_MODE_CFG, + GPIO13_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio14", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO14_FLASH_MODE_CFG, + GPIO14_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio15", + .regmap[0] = { + AIROHA_FUNC_PWM_MUX, + REG_GPIO_FLASH_MODE_CFG, + GPIO15_FLASH_MODE_CFG, + GPIO15_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio16", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO16_FLASH_MODE_CFG, + GPIO16_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio17", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO17_FLASH_MODE_CFG, + GPIO17_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio18", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO18_FLASH_MODE_CFG, + GPIO18_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio19", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO19_FLASH_MODE_CFG, + GPIO19_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio20", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO20_FLASH_MODE_CFG, + GPIO20_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio21", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO21_FLASH_MODE_CFG, + GPIO21_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio22", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO22_FLASH_MODE_CFG, + GPIO22_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio23", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO23_FLASH_MODE_CFG, + GPIO23_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio24", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO24_FLASH_MODE_CFG, + GPIO24_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio25", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO25_FLASH_MODE_CFG, + GPIO25_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio26", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO26_FLASH_MODE_CFG, + GPIO26_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio27", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO27_FLASH_MODE_CFG, + GPIO27_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio28", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO28_FLASH_MODE_CFG, + GPIO28_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio29", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO29_FLASH_MODE_CFG, + GPIO29_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio30", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO30_FLASH_MODE_CFG, + GPIO30_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio31", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO31_FLASH_MODE_CFG, + GPIO31_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio36", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO36_FLASH_MODE_CFG, + GPIO36_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio37", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO37_FLASH_MODE_CFG, + GPIO37_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio38", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO38_FLASH_MODE_CFG, + GPIO38_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio39", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO39_FLASH_MODE_CFG, + GPIO39_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio40", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO40_FLASH_MODE_CFG, + GPIO40_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio41", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO41_FLASH_MODE_CFG, + GPIO41_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio42", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO42_FLASH_MODE_CFG, + GPIO42_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio43", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO43_FLASH_MODE_CFG, + GPIO43_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio44", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO44_FLASH_MODE_CFG, + GPIO44_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio45", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO45_FLASH_MODE_CFG, + GPIO45_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio46", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO46_FLASH_MODE_CFG, + GPIO46_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, { + .name = "gpio47", + .regmap[0] = { + AIROHA_FUNC_PWM_EXT_MUX, + REG_GPIO_FLASH_MODE_CFG_EXT, + GPIO47_FLASH_MODE_CFG, + GPIO47_FLASH_MODE_CFG + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + { + .name = "gpio33", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED0_MODE_MASK, + GPIO_LAN0_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio34", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED0_MODE_MASK, + GPIO_LAN1_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio35", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED0_MODE_MASK, + GPIO_LAN2_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio42", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY1_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + { + .name = "gpio33", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED0_MODE_MASK, + GPIO_LAN0_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio34", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED0_MODE_MASK, + GPIO_LAN1_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio35", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED0_MODE_MASK, + GPIO_LAN2_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio42", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY2_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + { + .name = "gpio33", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED0_MODE_MASK, + GPIO_LAN0_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio34", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED0_MODE_MASK, + GPIO_LAN1_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio35", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED0_MODE_MASK, + GPIO_LAN2_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio42", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY3_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + { + .name = "gpio33", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED0_MODE_MASK, + GPIO_LAN0_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio34", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED0_MODE_MASK, + GPIO_LAN1_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio35", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED0_MODE_MASK, + GPIO_LAN2_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio42", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED0_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY4_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + { + .name = "gpio43", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED1_MODE_MASK, + GPIO_LAN0_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio44", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED1_MODE_MASK, + GPIO_LAN1_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio45", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED1_MODE_MASK, + GPIO_LAN2_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY1_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio46", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY1_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + { + .name = "gpio43", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED1_MODE_MASK, + GPIO_LAN0_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio44", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED1_MODE_MASK, + GPIO_LAN1_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio45", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED1_MODE_MASK, + GPIO_LAN2_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY2_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio46", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY2_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + { + .name = "gpio43", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED1_MODE_MASK, + GPIO_LAN0_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio44", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED1_MODE_MASK, + GPIO_LAN1_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio45", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED1_MODE_MASK, + GPIO_LAN2_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY3_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio46", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY3_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + { + .name = "gpio43", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN0_LED1_MODE_MASK, + GPIO_LAN0_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN1_LED_MAPPING_MASK, + LAN1_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio44", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN1_LED1_MODE_MASK, + GPIO_LAN1_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN2_LED_MAPPING_MASK, + LAN2_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio45", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN2_LED1_MODE_MASK, + GPIO_LAN2_LED1_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN3_LED_MAPPING_MASK, + LAN3_PHY4_LED_MAP + }, + .regmap_size = 2, + }, { + .name = "gpio46", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_LAN3_LED0_MODE_MASK, + GPIO_LAN3_LED0_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_LAN_LED1_MAPPING, + LAN4_LED_MAPPING_MASK, + LAN4_PHY4_LED_MAP + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = { + PINCTRL_FUNC_DESC(pon), + PINCTRL_FUNC_DESC(tod_1pps), + PINCTRL_FUNC_DESC(sipo), + PINCTRL_FUNC_DESC(mdio), + PINCTRL_FUNC_DESC(uart), + PINCTRL_FUNC_DESC(i2c), + PINCTRL_FUNC_DESC(jtag), + PINCTRL_FUNC_DESC(pcm), + PINCTRL_FUNC_DESC(spi), + PINCTRL_FUNC_DESC(pcm_spi), + PINCTRL_FUNC_DESC(i2s), + PINCTRL_FUNC_DESC(emmc), + PINCTRL_FUNC_DESC(pnand), + PINCTRL_FUNC_DESC(pcie_reset), + PINCTRL_FUNC_DESC(pwm), + PINCTRL_FUNC_DESC(phy1_led0), + PINCTRL_FUNC_DESC(phy2_led0), + PINCTRL_FUNC_DESC(phy3_led0), + PINCTRL_FUNC_DESC(phy4_led0), + PINCTRL_FUNC_DESC(phy1_led1), + PINCTRL_FUNC_DESC(phy2_led1), + PINCTRL_FUNC_DESC(phy3_led1), + PINCTRL_FUNC_DESC(phy4_led1), +}; + +static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), +}; + +static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + int pin) +{ + if (!range) + range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, + pin); + if (!range) + return -EINVAL; + + return pin - range->pin_base; +} + +/* gpio callbacks */ +static void airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 offset = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + + regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.data[index], + BIT(offset), value ? BIT(offset) : 0); +} + +static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + int err; + + err = regmap_read(pinctrl->regmap, + pinctrl->gpiochip.data[index], &val); + + return err ? err : !!(val & BIT(pin)); +} + +static int airoha_gpio_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + int err; + + err = pinctrl_gpio_direction_output(chip, gpio); + if (err) + return err; + + airoha_gpio_set(chip, gpio, value); + + return 0; +} + +/* irq callbacks */ +static void airoha_irq_unmask(struct irq_data *data) +{ + u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; + u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; + u32 mask = GENMASK(2 * offset + 1, 2 * offset); + struct airoha_pinctrl_gpiochip *gpiochip; + struct airoha_pinctrl *pinctrl; + u32 val = BIT(2 * offset); + + gpiochip = irq_data_get_irq_chip_data(data); + if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) + return; + + pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); + switch (gpiochip->irq_type[data->hwirq]) { + case IRQ_TYPE_LEVEL_LOW: + val = val << 1; + fallthrough; + case IRQ_TYPE_LEVEL_HIGH: + regmap_update_bits(pinctrl->regmap, gpiochip->level[index], + mask, val); + break; + case IRQ_TYPE_EDGE_FALLING: + val = val << 1; + fallthrough; + case IRQ_TYPE_EDGE_RISING: + regmap_update_bits(pinctrl->regmap, gpiochip->edge[index], + mask, val); + break; + case IRQ_TYPE_EDGE_BOTH: + regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask); + break; + default: + break; + } +} + +static void airoha_irq_mask(struct irq_data *data) +{ + u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; + u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; + u32 mask = GENMASK(2 * offset + 1, 2 * offset); + struct airoha_pinctrl_gpiochip *gpiochip; + struct airoha_pinctrl *pinctrl; + + gpiochip = irq_data_get_irq_chip_data(data); + pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); + + regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); + regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); +} + +static int airoha_irq_type(struct irq_data *data, unsigned int type) +{ + struct airoha_pinctrl_gpiochip *gpiochip; + + gpiochip = irq_data_get_irq_chip_data(data); + if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) + return -EINVAL; + + if (type == IRQ_TYPE_PROBE) { + if (gpiochip->irq_type[data->hwirq]) + return 0; + + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + } + gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static irqreturn_t airoha_irq_handler(int irq, void *data) +{ + struct airoha_pinctrl *pinctrl = data; + bool handled = false; + int i; + + for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { + struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq; + u32 regmap; + unsigned long status; + int irq; + + if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i], + ®map)) + continue; + + status = regmap; + for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) { + u32 offset = irq + i * AIROHA_PIN_BANK_SIZE; + + generic_handle_irq(irq_find_mapping(girq->domain, + offset)); + regmap_write(pinctrl->regmap, + pinctrl->gpiochip.status[i], BIT(irq)); + } + handled |= !!status; + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static const struct irq_chip airoha_gpio_irq_chip = { + .name = "airoha-gpio-irq", + .irq_unmask = airoha_irq_unmask, + .irq_mask = airoha_irq_mask, + .irq_mask_ack = airoha_irq_mask, + .irq_set_type = airoha_irq_type, + .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, +}; + +static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, + struct platform_device *pdev) +{ + struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip; + struct gpio_chip *gc = &chip->chip; + struct gpio_irq_chip *girq = &gc->irq; + struct device *dev = &pdev->dev; + int irq, err; + + chip->data = gpio_data_regs; + chip->dir = gpio_dir_regs; + chip->out = gpio_out_regs; + chip->status = irq_status_regs; + chip->level = irq_level_regs; + chip->edge = irq_edge_regs; + + gc->parent = dev; + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->direction_input = pinctrl_gpio_direction_input; + gc->direction_output = airoha_gpio_direction_output; + gc->set = airoha_gpio_set; + gc->get = airoha_gpio_get; + gc->base = -1; + gc->ngpio = AIROHA_NUM_PINS; + + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, + dev_name(dev), pinctrl); + if (err) { + dev_err(dev, "error requesting irq %d: %d\n", irq, err); + return err; + } + + return devm_gpiochip_add_data(dev, gc, pinctrl); +} + +/* pinmux callbacks */ +static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int selector, + unsigned int group) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct airoha_pinctrl_func *func; + struct function_desc *desc; + struct group_desc *grp; + int i; + + desc = pinmux_generic_get_function(pctrl_dev, selector); + if (!desc) + return -EINVAL; + + grp = pinctrl_generic_get_group(pctrl_dev, group); + if (!grp) + return -EINVAL; + + dev_dbg(pctrl_dev->dev, "enable function %s group %s\n", + desc->func.name, grp->grp.name); + + func = desc->data; + for (i = 0; i < func->group_size; i++) { + const struct airoha_pinctrl_func_group *group; + int j; + + group = &func->groups[i]; + if (strcmp(group->name, grp->grp.name)) + continue; + + for (j = 0; j < group->regmap_size; j++) { + switch (group->regmap[j].mux) { + case AIROHA_FUNC_PWM_EXT_MUX: + case AIROHA_FUNC_PWM_MUX: + regmap_update_bits(pinctrl->regmap, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + default: + regmap_update_bits(pinctrl->chip_scu, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + } + } + return 0; + } + + return -EINVAL; +} + +static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + unsigned int p, bool input) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + u32 mask, index; + int err, pin; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p); + if (pin < 0) + return pin; + + /* set output enable */ + mask = BIT(pin % AIROHA_PIN_BANK_SIZE); + index = pin / AIROHA_PIN_BANK_SIZE; + err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], + mask, !input ? mask : 0); + if (err) + return err; + + /* set direction */ + mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); + index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpiochip.dir[index], mask, + !input ? mask : 0); +} + +static const struct pinmux_ops airoha_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .gpio_set_direction = airoha_pinmux_set_direction, + .set_mux = airoha_pinmux_set_mux, + .strict = true, +}; + +/* pinconf callbacks */ +static const struct airoha_pinctrl_reg * +airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, + int conf_size, int pin) +{ + int i; + + for (i = 0; i < conf_size; i++) { + if (conf[i].pin == pin) + return &conf[i].reg; + } + + return NULL; +} + +static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, + const struct airoha_pinctrl_conf *conf, + int conf_size, int pin, u32 *val) +{ + const struct airoha_pinctrl_reg *reg; + + reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin); + if (!reg) + return -EINVAL; + + if (regmap_read(pinctrl->chip_scu, reg->offset, val)) + return -EINVAL; + + *val = (*val & reg->mask) >> __ffs(reg->mask); + + return 0; +} + +static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, + const struct airoha_pinctrl_conf *conf, + int conf_size, int pin, u32 val) +{ + const struct airoha_pinctrl_reg *reg = NULL; + + reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin); + if (!reg) + return -EINVAL; + + + if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, + val << __ffs(reg->mask))) + return -EINVAL; + + return 0; +} + +#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \ + ARRAY_SIZE(airoha_pinctrl_pullup_conf), \ + (pin), (val)) +#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \ + ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \ + ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \ + ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \ + (pin), (val)) +#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \ + ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \ + (pin), (val)) +#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \ + ARRAY_SIZE(airoha_pinctrl_pullup_conf), \ + (pin), (val)) +#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \ + ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \ + ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \ + ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \ + (pin), (val)) +#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \ + ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \ + (pin), (val)) + +static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + u32 val, mask; + int err, pin; + u8 index; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); + if (pin < 0) + return pin; + + index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; + err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); + if (err) + return err; + + mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); + return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; +} + +static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev, + unsigned int pin, unsigned long *config) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: { + u32 pull_up, pull_down; + + if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) || + airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down)) + return -EINVAL; + + if (param == PIN_CONFIG_BIAS_PULL_UP && + !(pull_up && !pull_down)) + return -EINVAL; + else if (param == PIN_CONFIG_BIAS_PULL_DOWN && + !(pull_down && !pull_up)) + return -EINVAL; + else if (pull_up || pull_down) + return -EINVAL; + + arg = 1; + break; + } + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2, e4; + + if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) || + airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4)) + return -EINVAL; + + arg = e4 << 1 | e2; + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg)) + return -EINVAL; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + arg = airoha_pinconf_get_direction(pctrl_dev, pin); + if (arg != param) + return -EINVAL; + + arg = 1; + break; + default: + return -EOPNOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, + unsigned int p, bool value) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int pin; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); + if (pin < 0) + return pin; + + airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); + + return 0; +} + +static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int i; + + for (i = 0; i < num_configs; i++) { + u32 param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + break; + case PIN_CONFIG_BIAS_PULL_UP: + airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); + airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + break; + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2 = 0, e4 = 0; + + switch (arg) { + case MTK_DRIVE_2mA: + break; + case MTK_DRIVE_4mA: + e2 = 1; + break; + case MTK_DRIVE_6mA: + e4 = 1; + break; + case MTK_DRIVE_8mA: + e2 = 1; + e4 = 1; + break; + default: + return -EINVAL; + } + + airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2); + airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4); + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: { + bool input = param == PIN_CONFIG_INPUT_ENABLE; + int err; + + err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin, + input); + if (err) + return err; + + if (param == PIN_CONFIG_OUTPUT) { + err = airoha_pinconf_set_pin_value(pctrl_dev, + pin, !!arg); + if (err) + return err; + } + break; + } + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, + unsigned int group, unsigned long *config) +{ + u32 cur_config = 0; + int i; + + for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) { + if (airoha_pinconf_get(pctrl_dev, + airoha_pinctrl_groups[group].pins[i], + config)) + return -EOPNOTSUPP; + + if (i && cur_config != *config) + return -EOPNOTSUPP; + + cur_config = *config; + } + + return 0; +} + +static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + int i; + + for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) { + int err; + + err = airoha_pinconf_set(pctrl_dev, + airoha_pinctrl_groups[group].pins[i], + configs, num_configs); + if (err) + return err; + } + + return 0; +} + +static const struct pinconf_ops airoha_confops = { + .is_generic = true, + .pin_config_get = airoha_pinconf_get, + .pin_config_set = airoha_pinconf_set, + .pin_config_group_get = airoha_pinconf_group_get, + .pin_config_group_set = airoha_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static const struct pinctrl_ops airoha_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static struct pinctrl_desc airoha_pinctrl_desc = { + .name = KBUILD_MODNAME, + .owner = THIS_MODULE, + .pctlops = &airoha_pctlops, + .pmxops = &airoha_pmxops, + .confops = &airoha_confops, + .pins = airoha_pinctrl_pins, + .npins = ARRAY_SIZE(airoha_pinctrl_pins), +}; + +static int airoha_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct airoha_pinctrl *pinctrl; + struct regmap *map; + int err, i; + + pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); + if (!pinctrl) + return -ENOMEM; + + pinctrl->regmap = device_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pinctrl->regmap)) + return PTR_ERR(pinctrl->regmap); + + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + pinctrl->chip_scu = map; + + err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc, + pinctrl, &pinctrl->ctrl); + if (err) + return err; + + /* build pin groups */ + for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) { + const struct pingroup *grp = &airoha_pinctrl_groups[i]; + + err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name, + grp->pins, grp->npins, + (void *)grp); + if (err < 0) { + dev_err(&pdev->dev, "Failed to register group %s\n", + grp->name); + return err; + } + } + + /* build functions */ + for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) { + const struct airoha_pinctrl_func *func; + + func = &airoha_pinctrl_funcs[i]; + err = pinmux_generic_add_function(pinctrl->ctrl, + func->desc.func.name, + func->desc.func.groups, + func->desc.func.ngroups, + (void *)func); + if (err < 0) { + dev_err(dev, "Failed to register function %s\n", + func->desc.func.name); + return err; + } + } + + err = pinctrl_enable(pinctrl->ctrl); + if (err) + return err; + + /* build gpio-chip */ + return airoha_pinctrl_add_gpiochip(pinctrl, pdev); +} + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,en7581-pinctrl" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC"); diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 68750b6f8e57..4ce2e35a6373 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -1089,7 +1089,7 @@ static struct platform_driver abx500_gpio_driver = { .of_match_table = abx500_gpio_match, }, .probe = abx500_gpio_probe, - .remove_new = abx500_gpio_remove, + .remove = abx500_gpio_remove, }; static int __init abx500_gpio_init(void) diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index 440ff1879424..c49d28793b69 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -216,6 +216,12 @@ enum s32_pins { S32G_IMCR_CAN1_RXD = 631, S32G_IMCR_CAN2_RXD = 632, S32G_IMCR_CAN3_RXD = 633, + + /* JTAG IMCRs */ + S32G_IMCR_JTAG_TMS = 562, + S32G_IMCR_JTAG_TCK = 572, + S32G_IMCR_JTAG_TDI = 573, + /* GMAC0 */ S32G_IMCR_Ethernet_MDIO = 527, S32G_IMCR_Ethernet_CRS = 526, @@ -229,7 +235,21 @@ enum s32_pins { S32G_IMCR_Ethernet_RX_DV = 530, S32G_IMCR_Ethernet_TX_CLK = 538, S32G_IMCR_Ethernet_REF_CLK = 535, + /* PFE EMAC 0 MII */ + S32G_IMCR_PFE_EMAC_0_MDIO = 837, + S32G_IMCR_PFE_EMAC_0_CRS = 836, + S32G_IMCR_PFE_EMAC_0_COL = 835, + S32G_IMCR_PFE_EMAC_0_RX_D0 = 841, + S32G_IMCR_PFE_EMAC_0_RX_D1 = 842, + S32G_IMCR_PFE_EMAC_0_RX_D2 = 843, + S32G_IMCR_PFE_EMAC_0_RX_D3 = 844, + S32G_IMCR_PFE_EMAC_0_RX_ER = 840, + S32G_IMCR_PFE_EMAC_0_RX_CLK = 839, + S32G_IMCR_PFE_EMAC_0_RX_DV = 845, + S32G_IMCR_PFE_EMAC_0_TX_CLK = 846, + S32G_IMCR_PFE_EMAC_0_REF_CLK = 838, + /* PFE EMAC 1 MII */ S32G_IMCR_PFE_EMAC_1_MDIO = 857, S32G_IMCR_PFE_EMAC_1_CRS = 856, @@ -317,6 +337,13 @@ enum s32_pins { S32G_IMCR_LLCE_CAN13_RXD = 758, S32G_IMCR_LLCE_CAN14_RXD = 759, S32G_IMCR_LLCE_CAN15_RXD = 760, + S32G_IMCR_LLCE_UART0_RXD = 790, + S32G_IMCR_LLCE_UART1_RXD = 791, + S32G_IMCR_LLCE_UART2_RXD = 792, + S32G_IMCR_LLCE_UART3_RXD = 793, + S32G_IMCR_LLCE_LPSPI2_PCS0 = 811, + S32G_IMCR_LLCE_LPSPI2_SCK = 816, + S32G_IMCR_LLCE_LPSPI2_SIN = 817, S32G_IMCR_USB_CLK = 895, S32G_IMCR_USB_DATA0 = 896, S32G_IMCR_USB_DATA1 = 897, @@ -503,6 +530,12 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), + + /* JTAG IMCRs */ + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TMS), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TCK), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TDI), + /* GMAC0 */ S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), @@ -638,6 +671,13 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART0_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART1_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART2_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART3_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SCK), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SIN), S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), @@ -652,6 +692,18 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_CRS), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_COL), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_REF_CLK), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 7f66ec73199a..fff6d4209ad5 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -506,7 +506,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_BOTH: pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); - pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; + pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; irq_set_handler_locked(d, handle_edge_irq); break; @@ -1204,7 +1204,7 @@ static struct platform_driver amd_gpio_driver = { #endif }, .probe = amd_gpio_probe, - .remove_new = amd_gpio_remove, + .remove = amd_gpio_remove, }; module_platform_driver(amd_gpio_driver); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index cf59089f2776..667be49c3f48 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -60,12 +60,12 @@ #define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL #define DB_TYPE_REMOVE_GLITCH 0x3UL -#define EDGE_TRAGGER 0x0UL +#define EDGE_TRIGGER 0x0UL #define LEVEL_TRIGGER 0x1UL #define ACTIVE_HIGH 0x0UL #define ACTIVE_LOW 0x1UL -#define BOTH_EADGE 0x2UL +#define BOTH_EDGES 0x2UL #define ENABLE_INTERRUPT 0x1UL #define DISABLE_INTERRUPT 0x0UL diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c index dd93f124e0a0..717f9592b28b 100644 --- a/drivers/pinctrl/pinctrl-artpec6.c +++ b/drivers/pinctrl/pinctrl-artpec6.c @@ -988,7 +988,7 @@ static struct platform_driver artpec6_pmx_driver = { .of_match_table = artpec6_pinctrl_match, }, .probe = artpec6_pmx_probe, - .remove_new = artpec6_pmx_remove, + .remove = artpec6_pmx_remove, }; static int __init artpec6_pmx_init(void) diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c index 1374f30166bc..9bf53de20be8 100644 --- a/drivers/pinctrl/pinctrl-aw9523.c +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -80,7 +80,7 @@ struct aw9523 { struct regmap *regmap; struct mutex i2c_lock; struct gpio_desc *reset_gpio; - struct regulator *vio_vreg; + int vio_vreg; struct pinctrl_dev *pctl; struct gpio_chip gpio; struct aw9523_irq *irq; @@ -550,10 +550,10 @@ static int aw9523_gpio_get(struct gpio_chip *chip, unsigned int offset) /** * _aw9523_gpio_get_multiple - Get I/O state for an entire port - * @regmap: Regmap structure - * @pin: gpiolib pin number + * @awi: Controller data * @regbit: hw pin index, used to retrieve port number * @state: returned port I/O state + * @mask: lines to read values for * * Return: Zero for success or negative number for error */ @@ -972,29 +972,23 @@ static int aw9523_probe(struct i2c_client *client) if (IS_ERR(awi->regmap)) return PTR_ERR(awi->regmap); - awi->vio_vreg = devm_regulator_get_optional(dev, "vio"); - if (IS_ERR(awi->vio_vreg)) { - if (PTR_ERR(awi->vio_vreg) == -EPROBE_DEFER) - return -EPROBE_DEFER; - awi->vio_vreg = NULL; - } else { - ret = regulator_enable(awi->vio_vreg); - if (ret) - return ret; - } + awi->vio_vreg = devm_regulator_get_enable_optional(dev, "vio"); + if (awi->vio_vreg && awi->vio_vreg != -ENODEV) + return awi->vio_vreg; + + ret = devm_mutex_init(dev, &awi->i2c_lock); + if (ret) + return ret; - mutex_init(&awi->i2c_lock); lockdep_set_subclass(&awi->i2c_lock, i2c_adapter_depth(client->adapter)); pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL); - if (!pdesc) { - ret = -ENOMEM; - goto err_disable_vregs; - } + if (!pdesc) + return -ENOMEM; ret = aw9523_hw_init(awi); if (ret) - goto err_disable_vregs; + return ret; pdesc->name = dev_name(dev); pdesc->owner = THIS_MODULE; @@ -1006,31 +1000,20 @@ static int aw9523_probe(struct i2c_client *client) ret = aw9523_init_gpiochip(awi, pdesc->npins); if (ret) - goto err_disable_vregs; + return ret; if (client->irq) { ret = aw9523_init_irq(awi, client->irq); if (ret) - goto err_disable_vregs; + return ret; } awi->pctl = devm_pinctrl_register(dev, pdesc, awi); - if (IS_ERR(awi->pctl)) { - ret = dev_err_probe(dev, PTR_ERR(awi->pctl), "Cannot register pinctrl"); - goto err_disable_vregs; - } - - ret = devm_gpiochip_add_data(dev, &awi->gpio, awi); - if (ret) - goto err_disable_vregs; - - return ret; + if (IS_ERR(awi->pctl)) + return dev_err_probe(dev, PTR_ERR(awi->pctl), + "Cannot register pinctrl"); -err_disable_vregs: - if (awi->vio_vreg) - regulator_disable(awi->vio_vreg); - mutex_destroy(&awi->i2c_lock); - return ret; + return devm_gpiochip_add_data(dev, &awi->gpio, awi); } static void aw9523_remove(struct i2c_client *client) @@ -1043,19 +1026,15 @@ static void aw9523_remove(struct i2c_client *client) * set the pins to hardware defaults before removing the driver * to leave it in a clean, safe and predictable state. */ - if (awi->vio_vreg) { - regulator_disable(awi->vio_vreg); - } else { + if (awi->vio_vreg == -ENODEV) { mutex_lock(&awi->i2c_lock); aw9523_hw_init(awi); mutex_unlock(&awi->i2c_lock); } - - mutex_destroy(&awi->i2c_lock); } static const struct i2c_device_id aw9523_i2c_id_table[] = { - { "aw9523_i2c", 0 }, + { "aw9523_i2c" }, { } }; MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table); diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 5096ccdd459e..0d6c2027d4c1 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -141,7 +141,6 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip * @driver_data: private driver data - * @regulator: Pointer to the regulator for the IC * @dev: struct device * @pctldev: pin controller device * @pinctrl_desc: pin controller description @@ -160,10 +159,9 @@ struct cy8c95x0_pinctrl { DECLARE_BITMAP(irq_trig_high, MAX_LINE); DECLARE_BITMAP(push_pull, MAX_LINE); DECLARE_BITMAP(shiftmask, MAX_LINE); - int nport; + unsigned int nport; struct gpio_chip gpio_chip; unsigned long driver_data; - struct regulator *regulator; struct device *dev; struct pinctrl_dev *pctldev; struct pinctrl_desc pinctrl_desc; @@ -612,9 +610,8 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); int write_val; - int ret = 0; - int i; u8 bits; + int ret; /* Add the 4 bit gap of Gport2 */ bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); @@ -625,7 +622,7 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, bitmap_shift_left(tval, tval, 4, MAX_LINE); bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); - for (i = 0; i < chip->nport; i++) { + for (unsigned int i = 0; i < chip->nport; i++) { /* Skip over unused banks */ bits = bitmap_get_value8(tmask, i * BANK_SZ); if (!bits) @@ -634,15 +631,13 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, write_val = bitmap_get_value8(tval, i * BANK_SZ); ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); - if (ret < 0) - goto out; + if (ret < 0) { + dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret); + return ret; + } } -out: - if (ret < 0) - dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret); - - return ret; + return 0; } static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, @@ -652,9 +647,8 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, DECLARE_BITMAP(tval, MAX_LINE); DECLARE_BITMAP(tmp, MAX_LINE); int read_val; - int ret = 0; - int i; u8 bits; + int ret; /* Add the 4 bit gap of Gport2 */ bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); @@ -665,15 +659,17 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, bitmap_shift_left(tval, tval, 4, MAX_LINE); bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); - for (i = 0; i < chip->nport; i++) { + for (unsigned int i = 0; i < chip->nport; i++) { /* Skip over unused banks */ bits = bitmap_get_value8(tmask, i * BANK_SZ); if (!bits) continue; ret = cy8c95x0_regmap_read(chip, reg, i, &read_val); - if (ret < 0) - goto out; + if (ret < 0) { + dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); + return ret; + } read_val &= bits; read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; @@ -684,11 +680,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, bitmap_shift_right(tmp, tval, 4, MAX_LINE); bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); -out: - if (ret < 0) - dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret); - - return ret; + return 0; } static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) @@ -754,14 +746,12 @@ static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val); if (ret < 0) - goto out; + return ret; if (reg_val & bit) return GPIO_LINE_DIRECTION_IN; return GPIO_LINE_DIRECTION_OUT; -out: - return ret; } static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, @@ -823,8 +813,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, case PIN_CONFIG_SLEEP_HARDWARE_STATE: case PIN_CONFIG_SLEW_RATE: default: - ret = -ENOTSUPP; - goto out; + return -ENOTSUPP; } /* * Writing 1 to one of the drive mode registers will automatically @@ -832,7 +821,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, */ ret = cy8c95x0_regmap_read(chip, reg, port, ®_val); if (ret < 0) - goto out; + return ret; if (reg_val & bit) arg = 1; @@ -840,8 +829,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, arg = !arg; *config = pinconf_to_config_packed(param, (u16)arg); -out: - return ret; + return 0; } static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, @@ -853,7 +841,6 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, unsigned long param = pinconf_to_config_param(config); unsigned long arg = pinconf_to_config_argument(config); unsigned int reg; - int ret; switch (param) { case PIN_CONFIG_BIAS_PULL_UP: @@ -884,22 +871,17 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, reg = CY8C95X0_PWMSEL; break; case PIN_CONFIG_OUTPUT_ENABLE: - ret = cy8c95x0_pinmux_direction(chip, off, !arg); - goto out; + return cy8c95x0_pinmux_direction(chip, off, !arg); case PIN_CONFIG_INPUT_ENABLE: - ret = cy8c95x0_pinmux_direction(chip, off, arg); - goto out; + return cy8c95x0_pinmux_direction(chip, off, arg); default: - ret = -ENOTSUPP; - goto out; + return -ENOTSUPP; } /* * Writing 1 to one of the drive mode registers will automatically * clear conflicting set bits in the other drive mode registers. */ - ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); -out: - return ret; + return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); } static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, @@ -1424,32 +1406,30 @@ static int cy8c95x0_detect(struct i2c_client *client, } dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); - strscpy(info->type, name, I2C_NAME_SIZE); + strscpy(info->type, name); return 0; } static int cy8c95x0_probe(struct i2c_client *client) { + struct device *dev = &client->dev; struct cy8c95x0_pinctrl *chip; struct regmap_config regmap_conf; struct regmap_range_cfg regmap_range_conf; - struct regulator *reg; int ret; - chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; - chip->dev = &client->dev; + chip->dev = dev; /* Set the device type */ chip->driver_data = (uintptr_t)i2c_get_match_data(client); if (!chip->driver_data) return -ENODEV; - i2c_set_clientdata(client, chip); - chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); @@ -1457,46 +1437,34 @@ static int cy8c95x0_probe(struct i2c_client *client) switch (chip->tpin) { case 20: - strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE); + strscpy(chip->name, cy8c95x0_id[0].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE; break; case 40: - strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE); + strscpy(chip->name, cy8c95x0_id[1].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE; break; case 60: - strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE); + strscpy(chip->name, cy8c95x0_id[2].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE; break; default: return -ENODEV; } - reg = devm_regulator_get(&client->dev, "vdd"); - if (IS_ERR(reg)) { - if (PTR_ERR(reg) == -EPROBE_DEFER) - return -EPROBE_DEFER; - } else { - ret = regulator_enable(reg); - if (ret) { - dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret); - return ret; - } - chip->regulator = reg; - } + ret = devm_regulator_get_enable(dev, "vdd"); + if (ret) + return dev_err_probe(dev, ret, "failed to enable regulator vdd\n"); /* bring the chip out of reset if reset pin is provided */ - chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(chip->gpio_reset)) { - ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), - "Failed to get GPIO 'reset'\n"); - goto err_exit; - } else if (chip->gpio_reset) { - usleep_range(1000, 2000); + chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(chip->gpio_reset)) + return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n"); + gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); + if (chip->gpio_reset) { + fsleep(1000); gpiod_set_value_cansleep(chip->gpio_reset, 0); - usleep_range(250000, 300000); - - gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); + fsleep(250000); } /* Regmap for direct and paged registers */ @@ -1506,10 +1474,8 @@ static int cy8c95x0_probe(struct i2c_client *client) regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max; chip->regmap = devm_regmap_init_i2c(client, ®map_conf); - if (IS_ERR(chip->regmap)) { - ret = PTR_ERR(chip->regmap); - goto err_exit; - } + if (IS_ERR(chip->regmap)) + return PTR_ERR(chip->regmap); bitmap_zero(chip->push_pull, MAX_LINE); bitmap_zero(chip->shiftmask, MAX_LINE); @@ -1525,31 +1491,14 @@ static int cy8c95x0_probe(struct i2c_client *client) if (client->irq) { ret = cy8c95x0_irq_setup(chip, client->irq); if (ret) - goto err_exit; + return ret; } ret = cy8c95x0_setup_pinctrl(chip); if (ret) - goto err_exit; - - ret = cy8c95x0_setup_gpiochip(chip); - if (ret) - goto err_exit; - - return 0; - -err_exit: - if (!IS_ERR_OR_NULL(chip->regulator)) - regulator_disable(chip->regulator); - return ret; -} - -static void cy8c95x0_remove(struct i2c_client *client) -{ - struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client); + return ret; - if (!IS_ERR_OR_NULL(chip->regulator)) - regulator_disable(chip->regulator); + return cy8c95x0_setup_gpiochip(chip); } static const struct acpi_device_id cy8c95x0_acpi_ids[] = { @@ -1565,7 +1514,6 @@ static struct i2c_driver cy8c95x0_driver = { .acpi_match_table = cy8c95x0_acpi_ids, }, .probe = cy8c95x0_probe, - .remove = cy8c95x0_remove, .id_table = cy8c95x0_id, .detect = cy8c95x0_detect, }; diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 0f6b55fec31d..eddb01796a83 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -96,8 +96,6 @@ struct k210_fpioa_data { struct k210_fpioa __iomem *fpioa; struct regmap *sysctl_map; u32 power_offset; - struct clk *clk; - struct clk *pclk; }; #define K210_PIN_NAME(i) ("IO_" #i) @@ -183,7 +181,7 @@ static const u32 k210_pinconf_mode_id_to_mode[] = { [K210_PC_DEFAULT_INT13] = K210_PC_MODE_IN | K210_PC_PU, }; -#undef DEFAULT +#undef K210_PC_DEFAULT /* * Pin functions configuration information. @@ -925,6 +923,7 @@ static int k210_fpioa_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct k210_fpioa_data *pdata; + struct clk *clk, *pclk; dev_info(dev, "K210 FPIOA pin controller\n"); @@ -939,13 +938,13 @@ static int k210_fpioa_probe(struct platform_device *pdev) if (IS_ERR(pdata->fpioa)) return PTR_ERR(pdata->fpioa); - pdata->clk = devm_clk_get_enabled(dev, "ref"); - if (IS_ERR(pdata->clk)) - return PTR_ERR(pdata->clk); + clk = devm_clk_get_enabled(dev, "ref"); + if (IS_ERR(clk)) + return PTR_ERR(clk); - pdata->pclk = devm_clk_get_optional_enabled(dev, "pclk"); - if (IS_ERR(pdata->pclk)) - return PTR_ERR(pdata->pclk); + pclk = devm_clk_get_optional_enabled(dev, "pclk"); + if (IS_ERR(pclk)) + return PTR_ERR(pclk); pdata->sysctl_map = syscon_regmap_lookup_by_phandle_args(np, diff --git a/drivers/pinctrl/pinctrl-k230.c b/drivers/pinctrl/pinctrl-k230.c new file mode 100644 index 000000000000..a9b4627b46b0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-k230.c @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ +#include <linux/module.h> +#include <linux/device.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> + +#include "core.h" +#include "pinconf.h" + +#define K230_NPINS 64 + +#define K230_SHIFT_ST (0) +#define K230_SHIFT_DS (1) +#define K230_SHIFT_BIAS (5) +#define K230_SHIFT_PD (5) +#define K230_SHIFT_PU (6) +#define K230_SHIFT_OE (7) +#define K230_SHIFT_IE (8) +#define K230_SHIFT_MSC (9) +#define K230_SHIFT_SL (10) +#define K230_SHIFT_SEL (11) + +#define K230_PC_ST BIT(0) +#define K230_PC_DS GENMASK(4, 1) +#define K230_PC_PD BIT(5) +#define K230_PC_PU BIT(6) +#define K230_PC_BIAS GENMASK(6, 5) +#define K230_PC_OE BIT(7) +#define K230_PC_IE BIT(8) +#define K230_PC_MSC BIT(9) +#define K230_PC_SL BIT(10) +#define K230_PC_SEL GENMASK(13, 11) + +struct k230_pin_conf { + unsigned int func; + unsigned long *configs; + unsigned int nconfigs; +}; + +struct k230_pin_group { + const char *name; + unsigned int *pins; + unsigned int num_pins; + + struct k230_pin_conf *data; +}; + +struct k230_pmx_func { + const char *name; + const char **groups; + unsigned int *group_idx; + unsigned int ngroups; +}; + +struct k230_pinctrl { + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + struct regmap *regmap_base; + void __iomem *base; + struct k230_pin_group *groups; + unsigned int ngroups; + struct k230_pmx_func *functions; + unsigned int nfunctions; +}; + +static const struct regmap_config k230_regmap_config = { + .name = "canaan,pinctrl", + .reg_bits = 32, + .val_bits = 32, + .max_register = 0x100, + .reg_stride = 4, +}; + +static int k230_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *k230_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int k230_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *num_pins = info->groups[selector].num_pins; + + return 0; +} + +static inline const struct k230_pmx_func *k230_name_to_funtion( + const struct k230_pinctrl *info, const char *name) +{ + unsigned int i; + + for (i = 0; i < info->nfunctions; i++) { + if (!strcmp(info->functions[i].name, name)) + return &info->functions[i]; + } + + return NULL; +} + +static struct pinctrl_pin_desc k230_pins[] = { + PINCTRL_PIN(0, "IO0"), PINCTRL_PIN(1, "IO1"), PINCTRL_PIN(2, "IO2"), + PINCTRL_PIN(3, "IO3"), PINCTRL_PIN(4, "IO4"), PINCTRL_PIN(5, "IO5"), + PINCTRL_PIN(6, "IO6"), PINCTRL_PIN(7, "IO7"), PINCTRL_PIN(8, "IO8"), + PINCTRL_PIN(9, "IO9"), PINCTRL_PIN(10, "IO10"), PINCTRL_PIN(11, "IO11"), + PINCTRL_PIN(12, "IO12"), PINCTRL_PIN(13, "IO13"), PINCTRL_PIN(14, "IO14"), + PINCTRL_PIN(15, "IO15"), PINCTRL_PIN(16, "IO16"), PINCTRL_PIN(17, "IO17"), + PINCTRL_PIN(18, "IO18"), PINCTRL_PIN(19, "IO19"), PINCTRL_PIN(20, "IO20"), + PINCTRL_PIN(21, "IO21"), PINCTRL_PIN(22, "IO22"), PINCTRL_PIN(23, "IO23"), + PINCTRL_PIN(24, "IO24"), PINCTRL_PIN(25, "IO25"), PINCTRL_PIN(26, "IO26"), + PINCTRL_PIN(27, "IO27"), PINCTRL_PIN(28, "IO28"), PINCTRL_PIN(29, "IO29"), + PINCTRL_PIN(30, "IO30"), PINCTRL_PIN(31, "IO31"), PINCTRL_PIN(32, "IO32"), + PINCTRL_PIN(33, "IO33"), PINCTRL_PIN(34, "IO34"), PINCTRL_PIN(35, "IO35"), + PINCTRL_PIN(36, "IO36"), PINCTRL_PIN(37, "IO37"), PINCTRL_PIN(38, "IO38"), + PINCTRL_PIN(39, "IO39"), PINCTRL_PIN(40, "IO40"), PINCTRL_PIN(41, "IO41"), + PINCTRL_PIN(42, "IO42"), PINCTRL_PIN(43, "IO43"), PINCTRL_PIN(44, "IO44"), + PINCTRL_PIN(45, "IO45"), PINCTRL_PIN(46, "IO46"), PINCTRL_PIN(47, "IO47"), + PINCTRL_PIN(48, "IO48"), PINCTRL_PIN(49, "IO49"), PINCTRL_PIN(50, "IO50"), + PINCTRL_PIN(51, "IO51"), PINCTRL_PIN(52, "IO52"), PINCTRL_PIN(53, "IO53"), + PINCTRL_PIN(54, "IO54"), PINCTRL_PIN(55, "IO55"), PINCTRL_PIN(56, "IO56"), + PINCTRL_PIN(57, "IO57"), PINCTRL_PIN(58, "IO58"), PINCTRL_PIN(59, "IO59"), + PINCTRL_PIN(60, "IO60"), PINCTRL_PIN(61, "IO61"), PINCTRL_PIN(62, "IO62"), + PINCTRL_PIN(63, "IO63") +}; + +static void k230_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + u32 val, bias, drive, input, slew, schmitt, power; + struct k230_pin_group *grp = k230_pins[offset].drv_data; + static const char * const biasing[] = { + "pull none", "pull down", "pull up", "" }; + static const char * const enable[] = { + "disable", "enable" }; + static const char * const power_source[] = { + "3V3", "1V8" }; + + regmap_read(info->regmap_base, offset * 4, &val); + + drive = (val & K230_PC_DS) >> K230_SHIFT_DS; + bias = (val & K230_PC_BIAS) >> K230_SHIFT_BIAS; + input = (val & K230_PC_IE) >> K230_SHIFT_IE; + slew = (val & K230_PC_SL) >> K230_SHIFT_SL; + schmitt = (val & K230_PC_ST) >> K230_SHIFT_ST; + power = (val & K230_PC_MSC) >> K230_SHIFT_MSC; + + seq_printf(s, "%s - strength %d - %s - %s - slewrate %s - schmitt %s - %s", + grp ? grp->name : "unknown", + drive, + biasing[bias], + input ? "input" : "output", + enable[slew], + enable[schmitt], + power_source[power]); +} + +static int k230_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = info->pctl_dev->dev; + const struct k230_pmx_func *func; + const struct k230_pin_group *grp; + struct pinctrl_map *new_map; + int map_num, i, j, idx; + unsigned int grp_id; + + func = k230_name_to_funtion(info, np_config->name); + if (!func) { + dev_err(dev, "function %s not found\n", np_config->name); + return -EINVAL; + } + + map_num = 0; + for (i = 0; i < func->ngroups; ++i) { + grp_id = func->group_idx[i]; + /* npins of config map plus a mux map */ + map_num += info->groups[grp_id].num_pins + 1; + } + + new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); + if (!new_map) + return -ENOMEM; + *map = new_map; + *num_maps = map_num; + + idx = 0; + for (i = 0; i < func->ngroups; ++i) { + grp_id = func->group_idx[i]; + grp = &info->groups[grp_id]; + new_map[idx].type = PIN_MAP_TYPE_MUX_GROUP; + new_map[idx].data.mux.group = grp->name; + new_map[idx].data.mux.function = np_config->name; + idx++; + + for (j = 0; j < grp->num_pins; ++j) { + new_map[idx].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[idx].data.configs.group_or_pin = + pin_get_name(pctldev, grp->pins[j]); + new_map[idx].data.configs.configs = + grp->data[j].configs; + new_map[idx].data.configs.num_configs = + grp->data[j].nconfigs; + idx++; + } + } + + return 0; +} + +static void k230_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops k230_pctrl_ops = { + .get_groups_count = k230_get_groups_count, + .get_group_name = k230_get_group_name, + .get_group_pins = k230_get_group_pins, + .pin_dbg_show = k230_pinctrl_pin_dbg_show, + .dt_node_to_map = k230_dt_node_to_map, + .dt_free_map = k230_dt_free_map, +}; + +static int k230_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int val, arg; + + regmap_read(info->regmap_base, pin * 4, &val); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = (val & K230_PC_ST) ? 1 : 0; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = (val & K230_PC_DS) >> K230_SHIFT_DS; + break; + case PIN_CONFIG_BIAS_DISABLE: + arg = (val & K230_PC_BIAS) ? 0 : 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = (val & K230_PC_PD) ? 1 : 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = (val & K230_PC_PU) ? 1 : 0; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = (val & K230_PC_OE) ? 1 : 0; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = (val & K230_PC_IE) ? 1 : 0; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = (val & K230_PC_MSC) ? 1 : 0; + break; + case PIN_CONFIG_SLEW_RATE: + arg = (val & K230_PC_SL) ? 1 : 0; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int k230_pinconf_set_param(struct pinctrl_dev *pctldev, unsigned int pin, + enum pin_config_param param, unsigned int arg) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + unsigned int val; + + regmap_read(info->regmap_base, pin * 4, &val); + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg) + val |= K230_PC_ST; + else + val &= ~K230_PC_ST; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ~K230_PC_DS; + val |= (arg << K230_SHIFT_DS) & K230_PC_DS; + break; + case PIN_CONFIG_BIAS_DISABLE: + val &= ~K230_PC_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!arg) + return -EINVAL; + val |= K230_PC_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (!arg) + return -EINVAL; + val |= K230_PC_PU; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + if (!arg) + return -EINVAL; + val |= K230_PC_OE; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!arg) + return -EINVAL; + val |= K230_PC_IE; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg) + val |= K230_PC_MSC; + else + val &= ~K230_PC_MSC; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + val |= K230_PC_SL; + else + val &= ~K230_PC_SL; + break; + default: + return -EINVAL; + } + + regmap_write(info->regmap_base, pin * 4, val); + + return 0; +} + +static int k230_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = info->pctl_dev->dev; + enum pin_config_param param; + unsigned int arg, i; + int ret; + + if (pin >= K230_NPINS) { + dev_err(dev, "pin number out of range\n"); + return -EINVAL; + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + ret = k230_pinconf_set_param(pctldev, pin, param, arg); + if (ret) + return ret; + } + + return 0; +} + +static void k230_pconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + unsigned int val; + + regmap_read(info->regmap_base, pin * 4, &val); + + seq_printf(s, " 0x%08x", val); +} + +static const struct pinconf_ops k230_pinconf_ops = { + .is_generic = true, + .pin_config_get = k230_pinconf_get, + .pin_config_set = k230_pinconf_set, + .pin_config_dbg_show = k230_pconf_dbg_show, +}; + +static int k230_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *k230_get_fname(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int k230_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + *groups = info->functions[selector].groups; + *num_groups = info->functions[selector].ngroups; + + return 0; +} + +static int k230_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct k230_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const struct k230_pin_conf *data = info->groups[group].data; + struct k230_pin_group *grp = &info->groups[group]; + const unsigned int *pins = grp->pins; + struct regmap *regmap; + unsigned int value, mask; + int cnt, reg; + + regmap = info->regmap_base; + + for (cnt = 0; cnt < grp->num_pins; cnt++) { + reg = pins[cnt] * 4; + value = data[cnt].func << K230_SHIFT_SEL; + mask = K230_PC_SEL; + regmap_update_bits(regmap, reg, mask, value); + k230_pins[pins[cnt]].drv_data = grp; + } + + return 0; +} + +static const struct pinmux_ops k230_pmxops = { + .get_functions_count = k230_get_functions_count, + .get_function_name = k230_get_fname, + .get_function_groups = k230_get_groups, + .set_mux = k230_set_mux, + .strict = true, +}; + +static int k230_pinctrl_parse_groups(struct device_node *np, + struct k230_pin_group *grp, + struct k230_pinctrl *info, + unsigned int index) +{ + struct device *dev = info->pctl_dev->dev; + const __be32 *list; + int size, i, ret; + + grp->name = np->name; + + list = of_get_property(np, "pinmux", &size); + size /= sizeof(*list); + + grp->num_pins = size; + grp->pins = devm_kcalloc(dev, grp->num_pins, sizeof(*grp->pins), + GFP_KERNEL); + grp->data = devm_kcalloc(dev, grp->num_pins, sizeof(*grp->data), + GFP_KERNEL); + if (!grp->pins || !grp->data) + return -ENOMEM; + + for (i = 0; i < size; i++) { + unsigned int mux_data = be32_to_cpu(*list++); + + grp->pins[i] = (mux_data >> 8); + grp->data[i].func = (mux_data & 0xff); + + ret = pinconf_generic_parse_dt_config(np, NULL, + &grp->data[i].configs, + &grp->data[i].nconfigs); + if (ret) + return ret; + } + + return 0; +} + +static int k230_pinctrl_parse_functions(struct device_node *np, + struct k230_pinctrl *info, + unsigned int index) +{ + struct device *dev = info->pctl_dev->dev; + struct k230_pmx_func *func; + struct k230_pin_group *grp; + static unsigned int idx, i; + int ret; + + func = &info->functions[index]; + + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups <= 0) + return 0; + + func->groups = devm_kcalloc(dev, func->ngroups, + sizeof(*func->groups), GFP_KERNEL); + func->group_idx = devm_kcalloc(dev, func->ngroups, + sizeof(*func->group_idx), GFP_KERNEL); + if (!func->groups || !func->group_idx) + return -ENOMEM; + + i = 0; + + for_each_child_of_node_scoped(np, child) { + func->groups[i] = child->name; + func->group_idx[i] = idx; + grp = &info->groups[idx]; + idx++; + ret = k230_pinctrl_parse_groups(child, grp, info, i++); + if (ret) + return ret; + } + + return 0; +} + +static void k230_pinctrl_child_count(struct k230_pinctrl *info, + struct device_node *np) +{ + for_each_child_of_node_scoped(np, child) { + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } +} + +static int k230_pinctrl_parse_dt(struct platform_device *pdev, + struct k230_pinctrl *info) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + unsigned int i; + int ret; + + k230_pinctrl_child_count(info, np); + + info->functions = devm_kcalloc(dev, info->nfunctions, + sizeof(*info->functions), GFP_KERNEL); + info->groups = devm_kcalloc(dev, info->ngroups, + sizeof(*info->groups), GFP_KERNEL); + if (!info->functions || !info->groups) + return -ENOMEM; + + i = 0; + + for_each_child_of_node_scoped(np, child) { + ret = k230_pinctrl_parse_functions(child, info, i++); + if (ret) { + dev_err(dev, "failed to parse function\n"); + return ret; + } + } + + return 0; +} + +static int k230_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct k230_pinctrl *info; + struct pinctrl_desc *pctl; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + pctl = &info->pctl; + + pctl->name = "k230-pinctrl"; + pctl->owner = THIS_MODULE; + pctl->pins = k230_pins; + pctl->npins = ARRAY_SIZE(k230_pins); + pctl->pctlops = &k230_pctrl_ops; + pctl->pmxops = &k230_pmxops; + pctl->confops = &k230_pinconf_ops; + + info->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + info->regmap_base = devm_regmap_init_mmio(dev, info->base, + &k230_regmap_config); + if (IS_ERR(info->regmap_base)) + return dev_err_probe(dev, PTR_ERR(info->regmap_base), + "failed to init regmap\n"); + + info->pctl_dev = devm_pinctrl_register(dev, pctl, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), + "devm_pinctrl_register failed\n"); + + k230_pinctrl_parse_dt(pdev, info); + + return 0; +} + +static const struct of_device_id k230_dt_ids[] = { + { .compatible = "canaan,k230-pinctrl", }, + { /* sintenel */ } +}; +MODULE_DEVICE_TABLE(of, k230_dt_ids); + +static struct platform_driver k230_pinctrl_driver = { + .probe = k230_pinctrl_probe, + .driver = { + .name = "k230-pinctrl", + .of_match_table = k230_dt_ids, + }, +}; +module_platform_driver(k230_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ze Huang <18771902331@163.com>"); +MODULE_DESCRIPTION("Canaan K230 pinctrl driver"); diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index d1ab8450ea93..61532a7a612a 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -57,6 +57,8 @@ enum { FUNC_CAN1, FUNC_CLKMON, FUNC_NONE, + FUNC_FAN, + FUNC_FC, FUNC_FC0_a, FUNC_FC0_b, FUNC_FC0_c, @@ -71,6 +73,7 @@ enum { FUNC_FC4_a, FUNC_FC4_b, FUNC_FC4_c, + FUNC_FC_SHRD, FUNC_FC_SHRD0, FUNC_FC_SHRD1, FUNC_FC_SHRD2, @@ -92,6 +95,7 @@ enum { FUNC_FC_SHRD18, FUNC_FC_SHRD19, FUNC_FC_SHRD20, + FUNC_FUSA, FUNC_GPIO, FUNC_IB_TRG_a, FUNC_IB_TRG_b, @@ -108,6 +112,8 @@ enum { FUNC_IRQ1, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, + FUNC_IRQ3, + FUNC_IRQ4, FUNC_EXT_IRQ, FUNC_MIIM, FUNC_MIIM_a, @@ -115,12 +121,14 @@ enum { FUNC_MIIM_c, FUNC_MIIM_Sa, FUNC_MIIM_Sb, + FUNC_MIIM_IRQ, FUNC_OB_TRG, FUNC_OB_TRG_a, FUNC_OB_TRG_b, FUNC_PHY_LED, FUNC_PCI_WAKE, FUNC_MD, + FUNC_PCIE_PERST, FUNC_PTP0, FUNC_PTP1, FUNC_PTP2, @@ -152,6 +160,7 @@ enum { FUNC_SGPIO_b, FUNC_SI, FUNC_SI2, + FUNC_SYNCE, FUNC_TACHO, FUNC_TACHO_a, FUNC_TACHO_b, @@ -170,6 +179,10 @@ enum { FUNC_USB_S_a, FUNC_USB_S_b, FUNC_USB_S_c, + FUNC_USB_POWER, + FUNC_USB2PHY_RST, + FUNC_USB_OVER_DETECT, + FUNC_USB_ULPI, FUNC_PLL_STAT, FUNC_EMMC, FUNC_EMMC_SD, @@ -184,6 +197,8 @@ static const char *const ocelot_function_names[] = { [FUNC_CAN1] = "can1", [FUNC_CLKMON] = "clkmon", [FUNC_NONE] = "none", + [FUNC_FAN] = "fan", + [FUNC_FC] = "fc", [FUNC_FC0_a] = "fc0_a", [FUNC_FC0_b] = "fc0_b", [FUNC_FC0_c] = "fc0_c", @@ -198,6 +213,7 @@ static const char *const ocelot_function_names[] = { [FUNC_FC4_a] = "fc4_a", [FUNC_FC4_b] = "fc4_b", [FUNC_FC4_c] = "fc4_c", + [FUNC_FC_SHRD] = "fc_shrd", [FUNC_FC_SHRD0] = "fc_shrd0", [FUNC_FC_SHRD1] = "fc_shrd1", [FUNC_FC_SHRD2] = "fc_shrd2", @@ -219,6 +235,7 @@ static const char *const ocelot_function_names[] = { [FUNC_FC_SHRD18] = "fc_shrd18", [FUNC_FC_SHRD19] = "fc_shrd19", [FUNC_FC_SHRD20] = "fc_shrd20", + [FUNC_FUSA] = "fusa", [FUNC_GPIO] = "gpio", [FUNC_IB_TRG_a] = "ib_trig_a", [FUNC_IB_TRG_b] = "ib_trig_b", @@ -235,6 +252,8 @@ static const char *const ocelot_function_names[] = { [FUNC_IRQ1] = "irq1", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", + [FUNC_IRQ3] = "irq3", + [FUNC_IRQ4] = "irq4", [FUNC_EXT_IRQ] = "ext_irq", [FUNC_MIIM] = "miim", [FUNC_MIIM_a] = "miim_a", @@ -242,8 +261,10 @@ static const char *const ocelot_function_names[] = { [FUNC_MIIM_c] = "miim_c", [FUNC_MIIM_Sa] = "miim_slave_a", [FUNC_MIIM_Sb] = "miim_slave_b", + [FUNC_MIIM_IRQ] = "miim_irq", [FUNC_PHY_LED] = "phy_led", [FUNC_PCI_WAKE] = "pci_wake", + [FUNC_PCIE_PERST] = "pcie_perst", [FUNC_MD] = "md", [FUNC_OB_TRG] = "ob_trig", [FUNC_OB_TRG_a] = "ob_trig_a", @@ -279,6 +300,7 @@ static const char *const ocelot_function_names[] = { [FUNC_SGPIO_b] = "sgpio_b", [FUNC_SI] = "si", [FUNC_SI2] = "si2", + [FUNC_SYNCE] = "synce", [FUNC_TACHO] = "tacho", [FUNC_TACHO_a] = "tacho_a", [FUNC_TACHO_b] = "tacho_b", @@ -294,6 +316,10 @@ static const char *const ocelot_function_names[] = { [FUNC_USB_S_a] = "usb_slave_a", [FUNC_USB_S_b] = "usb_slave_b", [FUNC_USB_S_c] = "usb_slave_c", + [FUNC_USB_POWER] = "usb_power", + [FUNC_USB2PHY_RST] = "usb2phy_rst", + [FUNC_USB_OVER_DETECT] = "usb_over_detect", + [FUNC_USB_ULPI] = "usb_ulpi", [FUNC_UART] = "uart", [FUNC_UART2] = "uart2", [FUNC_UART3] = "uart3", @@ -1136,6 +1162,165 @@ static const struct pinctrl_pin_desc lan966x_pins[] = { LAN966X_PIN(77), }; +#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ +static struct ocelot_pin_caps lan969x_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3 \ + }, \ + .a_functions = { \ + FUNC_##f4, FUNC_##f5, FUNC_##f6, \ + FUNC_##f7 \ + }, \ +} + +/* Pinmuxing table taken from data sheet */ +/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ +LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R); +LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R); +LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); +LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); +LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); +LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); +LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R); +LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R); +LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); +LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); +LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); +LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R); +LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R); +LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R); +LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R); +LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); +LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); +LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); +LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); +LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R); +LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R); +LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); +LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); +LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); +LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R); +LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); +LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); +LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); +LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); +LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R); +LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R); +LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R); +LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); +LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); +LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); +LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); +LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R); +LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R); +LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R); +LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R); +LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); +LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); +LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R); +LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); +LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); +LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); + +#define LAN969X_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &lan969x_pin_##n \ +} + +static const struct pinctrl_pin_desc lan969x_pins[] = { + LAN969X_PIN(0), + LAN969X_PIN(1), + LAN969X_PIN(2), + LAN969X_PIN(3), + LAN969X_PIN(4), + LAN969X_PIN(5), + LAN969X_PIN(6), + LAN969X_PIN(7), + LAN969X_PIN(8), + LAN969X_PIN(9), + LAN969X_PIN(10), + LAN969X_PIN(11), + LAN969X_PIN(12), + LAN969X_PIN(13), + LAN969X_PIN(14), + LAN969X_PIN(15), + LAN969X_PIN(16), + LAN969X_PIN(17), + LAN969X_PIN(18), + LAN969X_PIN(19), + LAN969X_PIN(20), + LAN969X_PIN(21), + LAN969X_PIN(22), + LAN969X_PIN(23), + LAN969X_PIN(24), + LAN969X_PIN(25), + LAN969X_PIN(26), + LAN969X_PIN(27), + LAN969X_PIN(28), + LAN969X_PIN(29), + LAN969X_PIN(30), + LAN969X_PIN(31), + LAN969X_PIN(32), + LAN969X_PIN(33), + LAN969X_PIN(34), + LAN969X_PIN(35), + LAN969X_PIN(36), + LAN969X_PIN(37), + LAN969X_PIN(38), + LAN969X_PIN(39), + LAN969X_PIN(40), + LAN969X_PIN(41), + LAN969X_PIN(42), + LAN969X_PIN(43), + LAN969X_PIN(44), + LAN969X_PIN(45), + LAN969X_PIN(46), + LAN969X_PIN(47), + LAN969X_PIN(48), + LAN969X_PIN(49), + LAN969X_PIN(50), + LAN969X_PIN(51), + LAN969X_PIN(52), + LAN969X_PIN(53), + LAN969X_PIN(54), + LAN969X_PIN(55), + LAN969X_PIN(56), + LAN969X_PIN(57), + LAN969X_PIN(58), + LAN969X_PIN(59), + LAN969X_PIN(60), + LAN969X_PIN(61), + LAN969X_PIN(62), + LAN969X_PIN(63), + LAN969X_PIN(64), + LAN969X_PIN(65), + LAN969X_PIN(66), +}; + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(ocelot_function_names); @@ -1682,6 +1867,23 @@ static struct ocelot_match_data lan966x_desc = { }, }; +static struct ocelot_match_data lan969x_desc = { + .desc = { + .name = "lan969x-pinctrl", + .pins = lan969x_pins, + .npins = ARRAY_SIZE(lan969x_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &lan966x_pmx_ops, + .confops = &ocelot_confops, + .owner = THIS_MODULE, + }, + .pincfg_data = { + .pd_bit = BIT(3), + .pu_bit = BIT(2), + .drive_bits = GENMASK(1, 0), + }, +}; + static int ocelot_create_group_func_map(struct device *dev, struct ocelot_pinctrl *info) { @@ -2014,6 +2216,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, + { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, {}, }; MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5c1bc4d5b662..36d4eaf0ebd1 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3227,7 +3227,9 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, /* we do not check return since it's safe node passed down */ size /= sizeof(*list); if (!size || size % 4) - return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); + return dev_err_probe(dev, -EINVAL, + "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n", + np, size); grp->npins = size / 4; @@ -4219,7 +4221,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { static struct platform_driver rockchip_pinctrl_driver = { .probe = rockchip_pinctrl_probe, - .remove_new = rockchip_pinctrl_remove, + .remove = rockchip_pinctrl_remove, .driver = { .name = "rockchip-pinctrl", .pm = &rockchip_pinctrl_dev_pm_ops, diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 2ec599e383e4..5be14dc979e2 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1966,6 +1966,7 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single }, { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, @@ -1981,7 +1982,7 @@ MODULE_DEVICE_TABLE(of, pcs_of_match); static struct platform_driver pcs_driver = { .probe = pcs_probe, - .remove_new = pcs_remove, + .remove = pcs_remove, .driver = { .name = DRIVER_NAME, .of_match_table = pcs_of_match, diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index d2c5321dd025..bfeb2edbeec5 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -855,7 +855,7 @@ static struct platform_driver stmfx_pinctrl_driver = { .pm = &stmfx_pinctrl_dev_pm_ops, }, .probe = stmfx_pinctrl_probe, - .remove_new = stmfx_pinctrl_remove, + .remove = stmfx_pinctrl_remove, }; module_platform_driver(stmfx_pinctrl_driver); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index fd0331a87cda..ab87de319ad8 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1105,7 +1105,7 @@ static const struct regmap_config sx150x_regmap_config = { .reg_bits = 8, .val_bits = 32, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, .reg_read = sx150x_regmap_reg_read, .reg_write = sx150x_regmap_reg_write, diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 4f98f72565f4..d6bb8f58978d 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -820,7 +820,7 @@ MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids); static struct platform_driver tb10x_pinctrl_pdrv = { .probe = tb10x_pinctrl_probe, - .remove_new = tb10x_pinctrl_remove, + .remove = tb10x_pinctrl_remove, .driver = { .name = "tb10x_pinctrl", .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids), diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c new file mode 100644 index 000000000000..e641bad6728c --- /dev/null +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -0,0 +1,918 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl driver for the T-Head TH1520 SoC + * + * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com> + */ + +#include <linux/array_size.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/of_address.h> +#include <linux/of_device.h> + +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "core.h" +#include "pinmux.h" +#include "pinconf.h" + +#define TH1520_PADCFG_IE BIT(9) +#define TH1520_PADCFG_SL BIT(8) +#define TH1520_PADCFG_ST BIT(7) +#define TH1520_PADCFG_SPU BIT(6) +#define TH1520_PADCFG_PS BIT(5) +#define TH1520_PADCFG_PE BIT(4) +#define TH1520_PADCFG_BIAS (TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_PADCFG_PE) +#define TH1520_PADCFG_DS GENMASK(3, 0) + +#define TH1520_PULL_DOWN_OHM 44000 /* typ. 44kOhm */ +#define TH1520_PULL_UP_OHM 48000 /* typ. 48kOhm */ +#define TH1520_PULL_STRONG_OHM 2100 /* typ. 2.1kOhm */ + +#define TH1520_PAD_NO_PADCFG BIT(30) +#define TH1520_PAD_MUXDATA GENMASK(29, 0) + +struct th1520_pad_group { + const char *name; + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +struct th1520_pinctrl { + struct pinctrl_desc desc; + struct mutex mutex; /* serialize adding functions */ + raw_spinlock_t lock; /* serialize register access */ + void __iomem *base; + struct pinctrl_dev *pctl; +}; + +static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 4 * (pin / 2); +} + +static unsigned int th1520_padcfg_shift(unsigned int pin) +{ + return 16 * (pin & BIT(0)); +} + +static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp, + unsigned int pin) +{ + return thp->base + 0x400 + 4 * (pin / 8); +} + +static unsigned int th1520_muxcfg_shift(unsigned int pin) +{ + return 4 * (pin & GENMASK(2, 0)); +} + +enum th1520_muxtype { + TH1520_MUX_____, + TH1520_MUX_GPIO, + TH1520_MUX_PWM, + TH1520_MUX_UART, + TH1520_MUX_IR, + TH1520_MUX_I2C, + TH1520_MUX_SPI, + TH1520_MUX_QSPI, + TH1520_MUX_SDIO, + TH1520_MUX_AUD, + TH1520_MUX_I2S, + TH1520_MUX_MAC0, + TH1520_MUX_MAC1, + TH1520_MUX_DPU0, + TH1520_MUX_DPU1, + TH1520_MUX_ISP, + TH1520_MUX_HDMI, + TH1520_MUX_BSEL, + TH1520_MUX_DBG, + TH1520_MUX_CLK, + TH1520_MUX_JTAG, + TH1520_MUX_ISO, + TH1520_MUX_FUSE, + TH1520_MUX_RST, +}; + +static const char *const th1520_muxtype_string[] = { + [TH1520_MUX_GPIO] = "gpio", + [TH1520_MUX_PWM] = "pwm", + [TH1520_MUX_UART] = "uart", + [TH1520_MUX_IR] = "ir", + [TH1520_MUX_I2C] = "i2c", + [TH1520_MUX_SPI] = "spi", + [TH1520_MUX_QSPI] = "qspi", + [TH1520_MUX_SDIO] = "sdio", + [TH1520_MUX_AUD] = "audio", + [TH1520_MUX_I2S] = "i2s", + [TH1520_MUX_MAC0] = "gmac0", + [TH1520_MUX_MAC1] = "gmac1", + [TH1520_MUX_DPU0] = "dpu0", + [TH1520_MUX_DPU1] = "dpu1", + [TH1520_MUX_ISP] = "isp", + [TH1520_MUX_HDMI] = "hdmi", + [TH1520_MUX_BSEL] = "bootsel", + [TH1520_MUX_DBG] = "debug", + [TH1520_MUX_CLK] = "clock", + [TH1520_MUX_JTAG] = "jtag", + [TH1520_MUX_ISO] = "iso7816", + [TH1520_MUX_FUSE] = "efuse", + [TH1520_MUX_RST] = "reset", +}; + +static enum th1520_muxtype th1520_muxtype_get(const char *str) +{ + enum th1520_muxtype mt; + + for (mt = TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++) { + if (!strcmp(str, th1520_muxtype_string[mt])) + return mt; + } + return TH1520_MUX_____; +} + +#define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ + { .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \ + (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \ + (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) } + +static unsigned long th1520_pad_muxdata(void *drv_data) +{ + return (uintptr_t)drv_data & TH1520_PAD_MUXDATA; +} + +static bool th1520_pad_no_padcfg(void *drv_data) +{ + return (uintptr_t)drv_data & TH1520_PAD_NO_PADCFG; +} + +static const struct pinctrl_pin_desc th1520_group1_pins[] = { + TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(2, SYS_RST_N, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(3, RTC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(4, RTC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + /* skip number 5 so we can calculate register offsets and shifts from the pin number */ + TH1520_PAD(6, TEST_MODE, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(7, DEBUG_MODE, DBG, ____, ____, GPIO, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(8, POR_SEL, ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG), + TH1520_PAD(9, I2C_AON_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C_AON_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, CPU_JTG_TCLK, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, CPU_JTG_TMS, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, CPU_JTG_TDI, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, CPU_JTG_TDO, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, CPU_JTG_TRST, JTAG, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0), + TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0), + TH1520_PAD(20, AOGPIO_11, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(21, AOGPIO_12, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(22, AOGPIO_13, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(23, AOGPIO_14, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(24, AOGPIO_15, GPIO, AUD, ____, ____, ____, ____, 0), + TH1520_PAD(25, AUDIO_PA0, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(26, AUDIO_PA1, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, AUDIO_PA2, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, AUDIO_PA3, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, AUDIO_PA4, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, AUDIO_PA5, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(31, AUDIO_PA6, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(32, AUDIO_PA7, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(33, AUDIO_PA8, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(34, AUDIO_PA9, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(35, AUDIO_PA10, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(36, AUDIO_PA11, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, AUDIO_PA12, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, AUDIO_PA13, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, AUDIO_PA14, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, AUDIO_PA15, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, AUDIO_PA16, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, AUDIO_PA17, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, AUDIO_PA27, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, AUDIO_PA28, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, AUDIO_PA29, AUD, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, AUDIO_PA30, AUD, RST, ____, GPIO, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group2_pins[] = { + TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0), + TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0), + TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0), + TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0), + TH1520_PAD(6, I2C0_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(7, I2C0_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(8, I2C1_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C1_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, DPU0, DPU1, 0), + TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0), + TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0), + TH1520_PAD(25, GPIO0_25, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(26, GPIO0_26, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(27, GPIO0_27, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(28, GPIO0_28, GPIO, ____, I2C, ____, DPU0, DPU1, 0), + TH1520_PAD(29, GPIO0_29, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(30, GPIO0_30, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(31, GPIO0_31, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(32, GPIO1_0, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(33, GPIO1_1, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(34, GPIO1_2, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(38, GPIO1_6, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(42, GPIO1_10, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(43, GPIO1_11, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(44, GPIO1_12, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(45, GPIO1_13, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(46, GPIO1_14, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(47, GPIO1_15, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(48, GPIO1_16, GPIO, UART, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0), + TH1520_PAD(53, GPIO1_21, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(54, GPIO1_22, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(55, GPIO1_23, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(56, GPIO1_24, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(57, GPIO1_25, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(61, GPIO1_29, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(62, GPIO1_30, GPIO, ____, ISP, ____, ____, ____, 0), +}; + +static const struct pinctrl_pin_desc th1520_group3_pins[] = { + TH1520_PAD(0, UART0_TXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(1, UART0_RXD, UART, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(12, I2C3_SDA, I2C, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(13, GPIO2_13, GPIO, SPI, ____, ____, ____, ____, 0), + TH1520_PAD(14, SPI_SCLK, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(15, SPI_CSN, SPI, UART, IR, GPIO, ____, ____, 0), + TH1520_PAD(16, SPI_MOSI, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(17, SPI_MISO, SPI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(18, GPIO2_18, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(19, GPIO2_19, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(20, GPIO2_20, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(21, GPIO2_21, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(22, GPIO2_22, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(23, GPIO2_23, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(24, GPIO2_24, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(25, GPIO2_25, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(26, SDIO0_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(27, SDIO0_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(28, SDIO1_WPRTN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(29, SDIO1_DETN, SDIO, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(30, GPIO2_30, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(31, GPIO2_31, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(32, GPIO3_0, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(33, GPIO3_1, GPIO, MAC1, ____, ____, ____, ____, 0), + TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0), + TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(38, HDMI_CEC, HDMI, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(39, GMAC0_TX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(40, GMAC0_RX_CLK, MAC0, ____, ____, GPIO, ____, ____, 0), + TH1520_PAD(41, GMAC0_TXEN, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(42, GMAC0_TXD0, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(43, GMAC0_TXD1, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(44, GMAC0_TXD2, MAC0, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(45, GMAC0_TXD3, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(46, GMAC0_RXDV, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(47, GMAC0_RXD0, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(48, GMAC0_RXD1, MAC0, I2C, ____, GPIO, ____, ____, 0), + TH1520_PAD(49, GMAC0_RXD2, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(50, GMAC0_RXD3, MAC0, SPI, ____, GPIO, ____, ____, 0), + TH1520_PAD(51, GMAC0_MDC, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(52, GMAC0_MDIO, MAC0, SPI, MAC1, GPIO, ____, ____, 0), + TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0), + TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0), +}; + +static const struct th1520_pad_group th1520_group1 = { + .name = "th1520-group1", + .pins = th1520_group1_pins, + .npins = ARRAY_SIZE(th1520_group1_pins), +}; + +static const struct th1520_pad_group th1520_group2 = { + .name = "th1520-group2", + .pins = th1520_group2_pins, + .npins = ARRAY_SIZE(th1520_group2_pins), +}; + +static const struct th1520_pad_group th1520_group3 = { + .name = "th1520-group3", + .pins = th1520_group3_pins, + .npins = ARRAY_SIZE(th1520_group3_pins), +}; + +static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.npins; +} + +static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int gsel) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return thp->desc.pins[gsel].name; +} + +static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int gsel, + const unsigned int **pins, + unsigned int *npins) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + *pins = &thp->desc.pins[gsel].number; + *npins = 1; + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg = th1520_padcfg(thp, pin); + void __iomem *muxcfg = th1520_muxcfg(thp, pin); + u32 pad; + u32 mux; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + pad = readl_relaxed(padcfg); + mux = readl_relaxed(muxcfg); + } + + seq_printf(s, "[PADCFG_%03u:0x%x=0x%07x MUXCFG_%03u:0x%x=0x%08x]", + 1 + pin / 2, 0x000 + 4 * (pin / 2), pad, + 1 + pin / 8, 0x400 + 4 * (pin / 8), mux); +} +#else +#define th1520_pin_dbg_show NULL +#endif + +static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int nmaps) +{ + unsigned long *seen = NULL; + unsigned int i; + + for (i = 0; i < nmaps; i++) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN && + map[i].data.configs.configs != seen) { + seen = map[i].data.configs.configs; + kfree(seen); + } + } + + kfree(map); +} + +static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + struct pinctrl_map *map; + unsigned long *configs; + unsigned int nconfigs; + unsigned int nmaps; + int ret; + + nmaps = 0; + for_each_available_child_of_node_scoped(np, child) { + int npins = of_property_count_strings(child, "pins"); + + if (npins <= 0) { + dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", + np, child); + return -EINVAL; + } + nmaps += npins; + if (of_property_present(child, "function")) + nmaps += npins; + } + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + guard(mutex)(&thp->mutex); + for_each_available_child_of_node_scoped(np, child) { + unsigned int rollback = nmaps; + enum th1520_muxtype muxtype; + struct property *prop; + const char *funcname; + const char **pgnames; + const char *pinname; + int npins; + + ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs); + if (ret) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", + np, child); + goto free_map; + } + + if (!of_property_read_string(child, "function", &funcname)) { + muxtype = th1520_muxtype_get(funcname); + if (!muxtype) { + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", + np, child, funcname); + ret = -EINVAL; + goto free_configs; + } + + funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!funcname) { + ret = -ENOMEM; + goto free_configs; + } + + npins = of_property_count_strings(child, "pins"); + pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) { + ret = -ENOMEM; + goto free_configs; + } + } else { + funcname = NULL; + } + + npins = 0; + of_property_for_each_string(child, "pins", prop, pinname) { + unsigned int i; + + for (i = 0; i < thp->desc.npins; i++) { + if (!strcmp(pinname, thp->desc.pins[i].name)) + break; + } + if (i == thp->desc.npins) { + nmaps = rollback; + dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", + np, child, pinname); + ret = -EINVAL; + goto free_configs; + } + + if (nconfigs) { + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN; + map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name; + map[nmaps].data.configs.configs = configs; + map[nmaps].data.configs.num_configs = nconfigs; + nmaps += 1; + } + if (funcname) { + pgnames[npins++] = thp->desc.pins[i].name; + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = funcname; + map[nmaps].data.mux.group = thp->desc.pins[i].name; + nmaps += 1; + } + } + + if (funcname) { + ret = pinmux_generic_add_function(pctldev, funcname, pgnames, + npins, (void *)muxtype); + if (ret < 0) { + dev_err(thp->pctl->dev, "error adding function %s\n", funcname); + goto free_map; + } + } + } + + *maps = map; + *num_maps = nmaps; + return 0; + +free_configs: + kfree(configs); +free_map: + th1520_pinctrl_dt_free_map(pctldev, map, nmaps); + return ret; +} + +static const struct pinctrl_ops th1520_pinctrl_ops = { + .get_groups_count = th1520_pinctrl_get_groups_count, + .get_group_name = th1520_pinctrl_get_group_name, + .get_group_pins = th1520_pinctrl_get_group_pins, + .pin_dbg_show = th1520_pin_dbg_show, + .dt_node_to_map = th1520_pinctrl_dt_node_to_map, + .dt_free_map = th1520_pinctrl_dt_free_map, +}; + +static const u8 th1520_drive_strength_in_ma[16] = { + 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25, +}; + +static u16 th1520_drive_strength_from_ma(u32 arg) +{ + u16 ds; + + for (ds = 0; ds < TH1520_PADCFG_DS; ds++) { + if (arg <= th1520_drive_strength_in_ma[ds]) + return ds; + } + return TH1520_PADCFG_DS; +} + +static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin, + u32 mask, u32 value) +{ + void __iomem *padcfg = th1520_padcfg(thp, pin); + unsigned int shift = th1520_padcfg_shift(pin); + u32 tmp; + + mask <<= shift; + value <<= shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp = readl_relaxed(padcfg); + tmp = (tmp & ~mask) | value; + writel_relaxed(tmp, padcfg); + } + return 0; +} + +static int th1520_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); + bool enabled; + int param; + u32 value; + u32 arg; + + if (th1520_pad_no_padcfg(desc->drv_data)) + return -ENOTSUPP; + + value = readl_relaxed(th1520_padcfg(thp, pin)); + value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + param = pinconf_to_config_param(*config); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE)); + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = (value & TH1520_PADCFG_BIAS) == TH1520_PADCFG_PE; + arg = enabled ? TH1520_PULL_DOWN_OHM : 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (value & TH1520_PADCFG_SPU) { + enabled = true; + arg = TH1520_PULL_STRONG_OHM; + } else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) == + (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) { + enabled = true; + arg = TH1520_PULL_UP_OHM; + } else { + enabled = false; + arg = 0; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = true; + arg = th1520_drive_strength_in_ma[value & TH1520_PADCFG_DS]; + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = value & TH1520_PADCFG_IE; + arg = enabled ? 1 : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = value & TH1520_PADCFG_ST; + arg = enabled ? 1 : 0; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = value & TH1520_PADCFG_SL; + arg = enabled ? 1 : 0; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, unsigned long *config) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + unsigned int pin = thp->desc.pins[gsel].number; + + return th1520_pinconf_get(pctldev, pin, config); +} + +static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); + unsigned int i; + u16 mask, value; + + if (th1520_pad_no_padcfg(desc->drv_data)) + return -ENOTSUPP; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + value |= TH1520_PADCFG_PE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= TH1520_PADCFG_BIAS; + value &= ~TH1520_PADCFG_BIAS; + if (arg == TH1520_PULL_STRONG_OHM) + value |= TH1520_PADCFG_SPU; + else + value |= TH1520_PADCFG_PE | TH1520_PADCFG_PS; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= TH1520_PADCFG_DS; + value &= ~TH1520_PADCFG_DS; + value |= th1520_drive_strength_from_ma(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= TH1520_PADCFG_IE; + if (arg) + value |= TH1520_PADCFG_IE; + else + value &= ~TH1520_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= TH1520_PADCFG_ST; + if (arg) + value |= TH1520_PADCFG_ST; + else + value &= ~TH1520_PADCFG_ST; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= TH1520_PADCFG_SL; + if (arg) + value |= TH1520_PADCFG_SL; + else + value &= ~TH1520_PADCFG_SL; + break; + default: + return -ENOTSUPP; + } + } + + return th1520_padcfg_rmw(thp, pin, mask, value); +} + +static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + unsigned int pin = thp->desc.pins[gsel].number; + + return th1520_pinconf_set(pctldev, pin, configs, num_configs); +} + +#ifdef CONFIG_DEBUG_FS +static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + u32 value = readl_relaxed(th1520_padcfg(thp, pin)); + + value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); + + seq_printf(s, " [0x%03x]", value); +} +#else +#define th1520_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops th1520_pinconf_ops = { + .pin_config_get = th1520_pinconf_get, + .pin_config_group_get = th1520_pinconf_group_get, + .pin_config_set = th1520_pinconf_set, + .pin_config_group_set = th1520_pinconf_group_set, + .pin_config_dbg_show = th1520_pinconf_dbg_show, + .is_generic = true, +}; + +static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin, + unsigned long muxdata, enum th1520_muxtype muxtype) +{ + void __iomem *muxcfg = th1520_muxcfg(thp, pin); + unsigned int shift = th1520_muxcfg_shift(pin); + u32 mask, value, tmp; + + for (value = 0; muxdata; muxdata >>= 5, value++) { + if ((muxdata & GENMASK(4, 0)) == muxtype) + break; + } + if (!muxdata) { + dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n", + th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin)); + return -EINVAL; + } + + mask = GENMASK(3, 0) << shift; + value = value << shift; + + scoped_guard(raw_spinlock_irqsave, &thp->lock) { + tmp = readl_relaxed(muxcfg); + tmp = (tmp & ~mask) | value; + writel_relaxed(tmp, muxcfg); + } + return 0; +} + +static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel); + enum th1520_muxtype muxtype; + + if (!func) + return -EINVAL; + + muxtype = (uintptr_t)func->data; + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, + th1520_pad_muxdata(thp->desc.pins[gsel].drv_data), + muxtype); +} + +static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, offset); + + return th1520_pinmux_set(thp, offset, + th1520_pad_muxdata(desc->drv_data), + TH1520_MUX_GPIO); +} + +static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev); + + return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE, + input ? TH1520_PADCFG_IE : 0); +} + +static const struct pinmux_ops th1520_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = th1520_pinmux_set_mux, + .gpio_request_enable = th1520_gpio_request_enable, + .gpio_set_direction = th1520_gpio_set_direction, + .strict = true, +}; + +static int th1520_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct th1520_pad_group *group; + struct device_node *np = dev->of_node; + struct th1520_pinctrl *thp; + struct clk *clk; + u32 pin_group; + int ret; + + thp = devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL); + if (!thp) + return -ENOMEM; + + thp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(thp->base)) + return PTR_ERR(thp->base); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n"); + + ret = of_property_read_u32(np, "thead,pad-group", &pin_group); + if (ret) + return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n"); + + if (pin_group == 1) + group = &th1520_group1; + else if (pin_group == 2) + group = &th1520_group2; + else if (pin_group == 3) + group = &th1520_group3; + else + return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n"); + + thp->desc.name = group->name; + thp->desc.pins = group->pins; + thp->desc.npins = group->npins; + thp->desc.pctlops = &th1520_pinctrl_ops; + thp->desc.pmxops = &th1520_pinmux_ops; + thp->desc.confops = &th1520_pinconf_ops; + thp->desc.owner = THIS_MODULE; + mutex_init(&thp->mutex); + raw_spin_lock_init(&thp->lock); + + ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl); + if (ret) + return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); + + return pinctrl_enable(thp->pctl); +} + +static const struct of_device_id th1520_pinctrl_of_match[] = { + { .compatible = "thead,th1520-pinctrl"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_pinctrl_of_match); + +static struct platform_driver th1520_pinctrl_driver = { + .probe = th1520_pinctrl_probe, + .driver = { + .name = "pinctrl-th1520", + .of_match_table = th1520_pinctrl_of_match, + }, +}; +module_platform_driver(th1520_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC"); +MODULE_AUTHOR("Emil Renner Berthing <emil.renner.berthing@canonical.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index f4256a918165..48f8aabf3bfa 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -1524,7 +1524,7 @@ static int pinmux_xway_probe(struct platform_device *pdev) * files which don't set the "gpio-ranges" property or systems that * utilize ACPI the driver has to call gpiochip_add_pin_range(). */ - if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) { + if (!of_property_present(pdev->dev.of_node, "gpio-ranges")) { /* finish with registering the gpio range in pinctrl */ xway_gpio_range.npins = xway_chip.ngpio; xway_gpio_range.base = xway_chip.base; diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 3c6d56fdb8c9..fddf0fef4b13 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -10,6 +10,7 @@ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> +#include <linux/bitfield.h> #include <linux/bitmap.h> #include <linux/init.h> #include <linux/module.h> @@ -44,12 +45,17 @@ #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 +#define VERSAL_LPD_PIN_PREFIX "LPD_MIO" +#define VERSAL_PMC_PIN_PREFIX "PMC_MIO" + +#define VERSAL_PINCTRL_ATTR_NODETYPE_MASK GENMASK(19, 14) +#define VERSAL_PINCTRL_NODETYPE_LPD_MIO BIT(0) + /** * struct zynqmp_pmux_function - a pinmux function * @name: Name of the pin mux function * @groups: List of pin groups for this function * @ngroups: Number of entries in @groups - * @node: Firmware node matching with the function * * This structure holds information about pin control function * and function group names supporting that function. @@ -93,6 +99,8 @@ struct zynqmp_pctrl_group { }; static struct pinctrl_desc zynqmp_desc; +static u32 family_code; +static u32 sub_family_code; static int zynqmp_pctrl_get_groups_count(struct pinctrl_dev *pctldev) { @@ -596,8 +604,12 @@ static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid, if (!groups[resp[i]].name) return -ENOMEM; - for (pin = 0; pin < groups[resp[i]].npins; pin++) - __set_bit(groups[resp[i]].pins[pin], used_pins); + for (pin = 0; pin < groups[resp[i]].npins; pin++) { + if (family_code == ZYNQMP_FAMILY_CODE) + __set_bit(groups[resp[i]].pins[pin], used_pins); + else + __set_bit((u8)groups[resp[i]].pins[pin] - 1, used_pins); + } } } done: @@ -873,6 +885,70 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, return 0; } +static int versal_pinctrl_get_attributes(u32 pin_idx, u32 *response) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_ATTRIBUTES; + qdata.arg1 = pin_idx; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + memcpy(response, &payload[1], sizeof(*response)); + + return 0; +} + +static int versal_pinctrl_prepare_pin_desc(struct device *dev, + const struct pinctrl_pin_desc **zynqmp_pins, + unsigned int *npins) +{ + u32 lpd_mio_pins = 0, attr, nodetype; + struct pinctrl_pin_desc *pins, *pin; + int ret, i; + + ret = zynqmp_pm_is_function_supported(PM_QUERY_DATA, PM_QID_PINCTRL_GET_ATTRIBUTES); + if (ret) + return ret; + + ret = zynqmp_pinctrl_get_num_pins(npins); + if (ret) + return ret; + + pins = devm_kzalloc(dev, sizeof(*pins) * *npins, GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < *npins; i++) { + ret = versal_pinctrl_get_attributes(i, &attr); + if (ret) + return ret; + + pin = &pins[i]; + pin->number = attr; + nodetype = FIELD_GET(VERSAL_PINCTRL_ATTR_NODETYPE_MASK, attr); + if (nodetype == VERSAL_PINCTRL_NODETYPE_LPD_MIO) { + pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", + VERSAL_LPD_PIN_PREFIX, i); + lpd_mio_pins++; + } else { + pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", + VERSAL_PMC_PIN_PREFIX, i - lpd_mio_pins); + } + + if (!pin->name) + return -ENOMEM; + } + + *zynqmp_pins = pins; + + return 0; +} + static int zynqmp_pinctrl_probe(struct platform_device *pdev) { struct zynqmp_pinctrl *pctrl; @@ -882,9 +958,18 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev) if (!pctrl) return -ENOMEM; - ret = zynqmp_pinctrl_prepare_pin_desc(&pdev->dev, - &zynqmp_desc.pins, - &zynqmp_desc.npins); + ret = zynqmp_pm_get_family_info(&family_code, &sub_family_code); + if (ret < 0) + return ret; + + if (family_code == ZYNQMP_FAMILY_CODE) { + ret = zynqmp_pinctrl_prepare_pin_desc(&pdev->dev, &zynqmp_desc.pins, + &zynqmp_desc.npins); + } else { + ret = versal_pinctrl_prepare_pin_desc(&pdev->dev, &zynqmp_desc.pins, + &zynqmp_desc.npins); + } + if (ret) { dev_err(&pdev->dev, "pin desc prepare fail with %d\n", ret); return ret; @@ -907,6 +992,7 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id zynqmp_pinctrl_of_match[] = { { .compatible = "xlnx,zynqmp-pinctrl" }, + { .compatible = "xlnx,versal-pinctrl" }, { } }; MODULE_DEVICE_TABLE(of, zynqmp_pinctrl_of_match); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 02033ea1c643..0743190da59e 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -14,6 +14,7 @@ #include <linux/array_size.h> #include <linux/ctype.h> +#include <linux/cleanup.h> #include <linux/debugfs.h> #include <linux/device.h> #include <linux/err.h> @@ -93,6 +94,7 @@ bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned int pin) if (!desc || !ops) return true; + guard(mutex)(&desc->mux_lock); if (ops->strict && desc->mux_usecount) return false; @@ -127,29 +129,31 @@ static int pin_request(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", pin, desc->name, owner); - if ((!gpio_range || ops->strict) && - desc->mux_usecount && strcmp(desc->mux_owner, owner)) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->mux_owner, owner); - goto out; - } + scoped_guard(mutex, &desc->mux_lock) { + if ((!gpio_range || ops->strict) && + desc->mux_usecount && strcmp(desc->mux_owner, owner)) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->mux_owner, owner); + goto out; + } - if ((gpio_range || ops->strict) && desc->gpio_owner) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->gpio_owner, owner); - goto out; - } + if ((gpio_range || ops->strict) && desc->gpio_owner) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->gpio_owner, owner); + goto out; + } - if (gpio_range) { - desc->gpio_owner = owner; - } else { - desc->mux_usecount++; - if (desc->mux_usecount > 1) - return 0; + if (gpio_range) { + desc->gpio_owner = owner; + } else { + desc->mux_usecount++; + if (desc->mux_usecount > 1) + return 0; - desc->mux_owner = owner; + desc->mux_owner = owner; + } } /* Let each pin increase references to this module */ @@ -178,12 +182,14 @@ static int pin_request(struct pinctrl_dev *pctldev, out_free_pin: if (status) { - if (gpio_range) { - desc->gpio_owner = NULL; - } else { - desc->mux_usecount--; - if (!desc->mux_usecount) - desc->mux_owner = NULL; + scoped_guard(mutex, &desc->mux_lock) { + if (gpio_range) { + desc->gpio_owner = NULL; + } else { + desc->mux_usecount--; + if (!desc->mux_usecount) + desc->mux_owner = NULL; + } } } out: @@ -219,15 +225,17 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin, return NULL; } - if (!gpio_range) { - /* - * A pin should not be freed more times than allocated. - */ - if (WARN_ON(!desc->mux_usecount)) - return NULL; - desc->mux_usecount--; - if (desc->mux_usecount) - return NULL; + scoped_guard(mutex, &desc->mux_lock) { + if (!gpio_range) { + /* + * A pin should not be freed more times than allocated. + */ + if (WARN_ON(!desc->mux_usecount)) + return NULL; + desc->mux_usecount--; + if (desc->mux_usecount) + return NULL; + } } /* @@ -239,13 +247,15 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin, else if (ops->free) ops->free(pctldev, pin); - if (gpio_range) { - owner = desc->gpio_owner; - desc->gpio_owner = NULL; - } else { - owner = desc->mux_owner; - desc->mux_owner = NULL; - desc->mux_setting = NULL; + scoped_guard(mutex, &desc->mux_lock) { + if (gpio_range) { + owner = desc->gpio_owner; + desc->gpio_owner = NULL; + } else { + owner = desc->mux_owner; + desc->mux_owner = NULL; + desc->mux_setting = NULL; + } } module_put(pctldev->owner); @@ -458,7 +468,8 @@ int pinmux_enable_setting(const struct pinctrl_setting *setting) pins[i]); continue; } - desc->mux_setting = &(setting->data.mux); + scoped_guard(mutex, &desc->mux_lock) + desc->mux_setting = &(setting->data.mux); } ret = ops->set_mux(pctldev, setting->data.mux.func, @@ -472,8 +483,10 @@ int pinmux_enable_setting(const struct pinctrl_setting *setting) err_set_mux: for (i = 0; i < num_pins; i++) { desc = pin_desc_get(pctldev, pins[i]); - if (desc) - desc->mux_setting = NULL; + if (desc) { + scoped_guard(mutex, &desc->mux_lock) + desc->mux_setting = NULL; + } } err_pin_request: /* On error release all taken pins */ @@ -492,6 +505,7 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) unsigned int num_pins = 0; int i; struct pin_desc *desc; + bool is_equal; if (pctlops->get_group_pins) ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, @@ -517,7 +531,10 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) pins[i]); continue; } - if (desc->mux_setting == &(setting->data.mux)) { + scoped_guard(mutex, &desc->mux_lock) + is_equal = (desc->mux_setting == &(setting->data.mux)); + + if (is_equal) { pin_free(pctldev, pins[i], NULL); } else { const char *gname; @@ -608,40 +625,42 @@ static int pinmux_pins_show(struct seq_file *s, void *what) if (desc == NULL) continue; - if (desc->mux_owner && - !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev))) - is_hog = true; - - if (pmxops->strict) { - if (desc->mux_owner) - seq_printf(s, "pin %d (%s): device %s%s", - pin, desc->name, desc->mux_owner, + scoped_guard(mutex, &desc->mux_lock) { + if (desc->mux_owner && + !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev))) + is_hog = true; + + if (pmxops->strict) { + if (desc->mux_owner) + seq_printf(s, "pin %d (%s): device %s%s", + pin, desc->name, desc->mux_owner, + is_hog ? " (HOG)" : ""); + else if (desc->gpio_owner) + seq_printf(s, "pin %d (%s): GPIO %s", + pin, desc->name, desc->gpio_owner); + else + seq_printf(s, "pin %d (%s): UNCLAIMED", + pin, desc->name); + } else { + /* For non-strict controllers */ + seq_printf(s, "pin %d (%s): %s %s%s", pin, desc->name, + desc->mux_owner ? desc->mux_owner + : "(MUX UNCLAIMED)", + desc->gpio_owner ? desc->gpio_owner + : "(GPIO UNCLAIMED)", is_hog ? " (HOG)" : ""); - else if (desc->gpio_owner) - seq_printf(s, "pin %d (%s): GPIO %s", - pin, desc->name, desc->gpio_owner); + } + + /* If mux: print function+group claiming the pin */ + if (desc->mux_setting) + seq_printf(s, " function %s group %s\n", + pmxops->get_function_name(pctldev, + desc->mux_setting->func), + pctlops->get_group_name(pctldev, + desc->mux_setting->group)); else - seq_printf(s, "pin %d (%s): UNCLAIMED", - pin, desc->name); - } else { - /* For non-strict controllers */ - seq_printf(s, "pin %d (%s): %s %s%s", pin, desc->name, - desc->mux_owner ? desc->mux_owner - : "(MUX UNCLAIMED)", - desc->gpio_owner ? desc->gpio_owner - : "(GPIO UNCLAIMED)", - is_hog ? " (HOG)" : ""); + seq_putc(s, '\n'); } - - /* If mux: print function+group claiming the pin */ - if (desc->mux_setting) - seq_printf(s, " function %s group %s\n", - pmxops->get_function_name(pctldev, - desc->mux_setting->func), - pctlops->get_group_name(pctldev, - desc->mux_setting->group)); - else - seq_putc(s, '\n'); } mutex_unlock(&pctldev->mutex); diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 8fe459d082ed..206226318e45 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -46,6 +46,15 @@ config PINCTRL_IPQ5332 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5332 platform. +config PINCTRL_IPQ5424 + tristate "Qualcomm Technologies, Inc. IPQ5424 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ5424 platform. Select this for + IPQ5424. + config PINCTRL_IPQ8074 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" depends on ARM64 || COMPILE_TEST @@ -182,6 +191,20 @@ config PINCTRL_QCS404 This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCS404 platform. +config PINCTRL_QCS615 + tristate "Qualcomm Technologies QCS615 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + TLMM block found on the Qualcomm QCS615 platform. + +config PINCTRL_QCS8300 + tristate "Qualcomm Technologies QCS8300 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm QCS8300 platform. + config PINCTRL_QDF2XXX tristate "Qualcomm Technologies QDF2xxx pin controller driver" depends on ACPI @@ -204,6 +227,14 @@ config PINCTRL_SA8775P This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm SA8775P platforms. +config PINCTRL_SAR2130P + tristate "Qualcomm Technologies Inc SAR2130P pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SAR2130P platform. + config PINCTRL_SC7180 tristate "Qualcomm Technologies Inc SC7180 pin controller driver" depends on ARM64 || COMPILE_TEST @@ -382,6 +413,14 @@ config PINCTRL_SM8650 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8650 platform. +config PINCTRL_SM8750 + tristate "Qualcomm Technologies Inc SM8750 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8750 platform. + config PINCTRL_X1E80100 tristate "Qualcomm Technologies Inc X1E80100 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index eb04297b6388..9a23d41d801c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o +obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o @@ -23,6 +24,8 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o obj-$(CONFIG_PINCTRL_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o +obj-$(CONFIG_PINCTRL_QCS615) += pinctrl-qcs615.o +obj-$(CONFIG_PINCTRL_QCS8300) += pinctrl-qcs8300.o obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o @@ -32,6 +35,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o +obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o @@ -62,6 +66,7 @@ obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8650) += pinctrl-sm8650.o obj-$(CONFIG_PINCTRL_SM8650_LPASS_LPI) += pinctrl-sm8650-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM8750) += pinctrl-sm8750.o obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o obj-$(CONFIG_PINCTRL_X1E80100) += pinctrl-x1e80100.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index a18df4162299..20c3b9025044 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -629,7 +629,7 @@ static struct platform_driver apq8064_pinctrl_driver = { .of_match_table = apq8064_pinctrl_of_match, }, .probe = apq8064_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init apq8064_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index afada80e52a2..3fc0a40762b6 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -1207,7 +1207,7 @@ static struct platform_driver apq8084_pinctrl_driver = { .of_match_table = apq8084_pinctrl_of_match, }, .probe = apq8084_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init apq8084_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index cb13576ad6cf..1f7944dd829d 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -710,7 +710,7 @@ static struct platform_driver ipq4019_pinctrl_driver = { .of_match_table = ipq4019_pinctrl_of_match, }, .probe = ipq4019_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq4019_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index 68f65b57003e..e2951f81c3ee 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -754,7 +754,7 @@ static struct platform_driver ipq5018_pinctrl_driver = { .of_match_table = ipq5018_pinctrl_of_match, }, .probe = ipq5018_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq5018_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c index 882175118970..625f8014051f 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5332.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -834,7 +834,7 @@ static struct platform_driver ipq5332_pinctrl_driver = { .of_match_table = ipq5332_pinctrl_of_match, }, .probe = ipq5332_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq5332_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c new file mode 100644 index 000000000000..796299cd2e4e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -0,0 +1,792 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5424_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); + +enum ipq5424_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tic, + msm_mux_audio_pri, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_sec, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_core_voltage, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_i2c0_scl, + msm_mux_i2c0_sda, + msm_mux_i2c1_scl, + msm_mux_i2c1_sda, + msm_mux_i2c11, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc_mst, + msm_mux_mdc_slv, + msm_mux_mdio_mst, + msm_mux_mdio_slv, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk, + msm_mux_pcie3_wake, + msm_mux_pll_test, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_PTA0_0, + msm_mux_PTA0_1, + msm_mux_PTA0_2, + msm_mux_PTA10, + msm_mux_PTA11, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_resout, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_rx2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_spi0, + msm_mux_spi1, + msm_mux_spi10, + msm_mux_spi11, + msm_mux_tsens_max, + msm_mux_uart0, + msm_mux_uart1, + msm_mux_wci_txd, + msm_mux_wci_rxd, + msm_mux_wsi_clk, + msm_mux_wsi_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const pwm2_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const wci_txd_groups[] = { + "gpio0", "gpio1", "gpio8", "gpio10", "gpio11", "gpio40", "gpio41", +}; + +static const char * const wci_rxd_groups[] = { + "gpio0", "gpio1", "gpio8", "gpio10", "gpio11", "gpio40", "gpio41", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char * const qspi_cs_groups[] = { + "gpio4", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio27", +}; + +static const char * const sdc_clk_groups[] = { + "gpio5", +}; + +static const char * const qspi_clk_groups[] = { + "gpio5", +}; + +static const char * const spi0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const pwm1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const cri_trng0_groups[] = { + "gpio6", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", + "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", "gpio36", "gpio37", + "gpio38", "gpio39", +}; + +static const char * const cri_trng1_groups[] = { + "gpio7", +}; + +static const char * const cri_trng2_groups[] = { + "gpio8", +}; + +static const char * const cri_trng3_groups[] = { + "gpio9", +}; + +static const char * const uart0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const pwm0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio12", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio13", +}; + +static const char * const i2c0_scl_groups[] = { + "gpio14", +}; + +static const char * const tsens_max_groups[] = { + "gpio14", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio14", +}; + +static const char * const i2c0_sda_groups[] = { + "gpio15", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio15", +}; + +static const char * const core_voltage_groups[] = { + "gpio16", "gpio17", +}; + +static const char * const i2c1_scl_groups[] = { + "gpio16", +}; + +static const char * const i2c1_sda_groups[] = { + "gpio17", +}; + +static const char * const mdc_slv_groups[] = { + "gpio20", +}; + +static const char * const atest_char0_groups[] = { + "gpio20", +}; + +static const char * const mdio_slv_groups[] = { + "gpio21", +}; + +static const char * const atest_char1_groups[] = { + "gpio21", +}; + +static const char * const mdc_mst_groups[] = { + "gpio22", +}; + +static const char * const atest_char2_groups[] = { + "gpio22", +}; + +static const char * const mdio_mst_groups[] = { + "gpio23", +}; + +static const char * const atest_char3_groups[] = { + "gpio23", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio24", +}; + +static const char * const PTA10_groups[] = { + "gpio24", "gpio26", "gpio27", +}; + +static const char * const mac0_groups[] = { + "gpio24", "gpio26", +}; + +static const char * const atest_char_groups[] = { + "gpio24", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio26", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio27", +}; + +static const char * const i2c11_groups[] = { + "gpio27", "gpio29", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio29", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio30", +}; + +static const char * const mac1_groups[] = { + "gpio30", "gpio32", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio32", +}; + +static const char * const PTA11_groups[] = { + "gpio30", "gpio32", "gpio33", +}; + +static const char * const audio_pri0_groups[] = { + "gpio32", "gpio32", +}; + +static const char * const pcie3_clk_groups[] = { + "gpio33", +}; + +static const char * const audio_pri1_groups[] = { + "gpio33", "gpio33", +}; + +static const char * const pcie3_wake_groups[] = { + "gpio35", +}; + +static const char * const audio_sec1_groups[] = { + "gpio35", "gpio35", +}; + +static const char * const audio_pri_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const spi1_groups[] = { + "gpio11", "gpio36", "gpio37", "gpio38", "gpio46", +}; + +static const char * const audio_sec0_groups[] = { + "gpio36", "gpio36", +}; + +static const char * const rx1_groups[] = { + "gpio38", "gpio46", +}; + +static const char * const pll_test_groups[] = { + "gpio38", +}; + +static const char * const dbg_out_groups[] = { + "gpio46", +}; + +static const char * const PTA0_0_groups[] = { + "gpio40", +}; + +static const char * const atest_tic_groups[] = { + "gpio40", +}; + +static const char * const PTA0_1_groups[] = { + "gpio41", +}; + +static const char * const cxc_data_groups[] = { + "gpio41", +}; + +static const char * const PTA0_2_groups[] = { + "gpio42", +}; + +static const char * const cxc_clk_groups[] = { + "gpio42", +}; + +static const char * const uart1_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const audio_sec_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio44", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio33", +}; + +static const char * const rx0_groups[] = { + "gpio39", "gpio47", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio46", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio24", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio26", +}; + +static const char * const resout_groups[] = { + "gpio49", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio30", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio32", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio35", +}; + +static const char * const spi10_groups[] = { + "gpio45", "gpio47", "gpio48", +}; + +static const char * const spi11_groups[] = { + "gpio10", "gpio12", "gpio13", +}; + +static const char * const wsi_clk_groups[] = { + "gpio24", "gpio27", +}; + +static const char * const wsi_data_groups[] = { + "gpio26", "gpio29", +}; + +static const char * const rx2_groups[] = { + "gpio37", "gpio45", +}; + +static const struct pinfunction ipq5424_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tic), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_pri0), + MSM_PIN_FUNCTION(audio_pri1), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec0), + MSM_PIN_FUNCTION(audio_sec1), + MSM_PIN_FUNCTION(core_voltage), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(cxc_clk), + MSM_PIN_FUNCTION(cxc_data), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2c0_scl), + MSM_PIN_FUNCTION(i2c0_sda), + MSM_PIN_FUNCTION(i2c1_scl), + MSM_PIN_FUNCTION(i2c1_sda), + MSM_PIN_FUNCTION(i2c11), + MSM_PIN_FUNCTION(mac0), + MSM_PIN_FUNCTION(mac1), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(PTA0_0), + MSM_PIN_FUNCTION(PTA0_1), + MSM_PIN_FUNCTION(PTA0_2), + MSM_PIN_FUNCTION(PTA10), + MSM_PIN_FUNCTION(PTA11), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(rx2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(spi0), + MSM_PIN_FUNCTION(spi1), + MSM_PIN_FUNCTION(spi10), + MSM_PIN_FUNCTION(spi11), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(uart0), + MSM_PIN_FUNCTION(uart1), + MSM_PIN_FUNCTION(wci_txd), + MSM_PIN_FUNCTION(wci_rxd), + MSM_PIN_FUNCTION(wsi_clk), + MSM_PIN_FUNCTION(wsi_data), +}; + +static const struct msm_pingroup ipq5424_groups[] = { + PINGROUP(0, sdc_data, qspi_data, pwm2, wci_txd, wci_rxd, _, _, _, _), + PINGROUP(1, sdc_data, qspi_data, pwm2, wci_txd, wci_rxd, _, _, _, _), + PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _), + PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + PINGROUP(6, spi0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _), + PINGROUP(7, spi0, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _), + PINGROUP(8, spi0, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _), + PINGROUP(9, spi0, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _), + PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), + PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _), + PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _), + PINGROUP(13, uart0, pwm0, spi11, _, prng_rosc1, qdss_tracedata_a, _, _, _), + PINGROUP(14, i2c0_scl, tsens_max, _, prng_rosc2, qdss_tracedata_a, _, _, _, _), + PINGROUP(15, i2c0_sda, _, prng_rosc3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(16, core_voltage, i2c1_scl, _, _, _, _, _, _, _), + PINGROUP(17, core_voltage, i2c1_sda, _, _, _, _, _, _, _), + PINGROUP(18, _, _, _, _, _, _, _, _, _), + PINGROUP(19, _, _, _, _, _, _, _, _, _), + PINGROUP(20, mdc_slv, atest_char0, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(21, mdio_slv, atest_char1, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(22, mdc_mst, atest_char2, _, _, _, _, _, _, _), + PINGROUP(23, mdio_mst, atest_char3, _, _, _, _, _, _, _), + PINGROUP(24, pcie0_clk, PTA10, mac0, _, wsi_clk, _, atest_char, qdss_cti_trig_out_a0, _), + PINGROUP(25, _, _, _, _, _, _, _, _, _), + PINGROUP(26, pcie0_wake, PTA10, mac0, _, wsi_data, _, qdss_cti_trig_in_a0, _, _), + PINGROUP(27, pcie1_clk, i2c11, PTA10, wsi_clk, qdss_cti_trig_out_a1, _, _, _, _), + PINGROUP(28, _, _, _, _, _, _, _, _, _), + PINGROUP(29, pcie1_wake, i2c11, wsi_data, qdss_cti_trig_in_a1, _, _, _, _, _), + PINGROUP(30, pcie2_clk, PTA11, mac1, qdss_cti_trig_out_b0, _, _, _, _, _), + PINGROUP(31, _, _, _, _, _, _, _, _, _), + PINGROUP(32, pcie2_wake, PTA11, mac1, audio_pri0, audio_pri0, qdss_cti_trig_in_b0, _, _, _), + PINGROUP(33, pcie3_clk, PTA11, audio_pri1, audio_pri1, qdss_cti_trig_out_b1, _, _, _, _), + PINGROUP(34, _, _, _, _, _, _, _, _, _), + PINGROUP(35, pcie3_wake, audio_sec1, audio_sec1, qdss_cti_trig_in_b1, _, _, _, _, _), + PINGROUP(36, audio_pri, spi1, audio_sec0, audio_sec0, qdss_tracedata_a, _, _, _, _), + PINGROUP(37, audio_pri, spi1, rx2, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(38, audio_pri, spi1, pll_test, rx1, qdss_tracedata_a, _, _, _, _), + PINGROUP(39, audio_pri, rx0, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(40, PTA0_0, wci_txd, wci_rxd, _, atest_tic, _, _, _, _), + PINGROUP(41, PTA0_1, wci_txd, wci_rxd, cxc_data, _, _, _, _, _), + PINGROUP(42, PTA0_2, cxc_clk, _, _, _, _, _, _, _), + PINGROUP(43, uart1, gcc_plltest, _, _, _, _, _, _, _), + PINGROUP(44, uart1, gcc_tlmm, _, _, _, _, _, _, _), + PINGROUP(45, spi10, rx2, audio_sec, gcc_plltest, _, qdss_traceclk_a, _, _, _), + PINGROUP(46, spi1, rx1, audio_sec, dbg_out, qdss_tracectl_a, _, _, _, _), + PINGROUP(47, spi10, rx0, audio_sec, _, _, _, _, _, _), + PINGROUP(48, spi10, audio_sec, _, _, _, _, _, _, _), + PINGROUP(49, resout, _, _, _, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5424_pinctrl = { + .pins = ipq5424_pins, + .npins = ARRAY_SIZE(ipq5424_pins), + .functions = ipq5424_functions, + .nfunctions = ARRAY_SIZE(ipq5424_functions), + .groups = ipq5424_groups, + .ngroups = ARRAY_SIZE(ipq5424_groups), + .ngpios = 50, +}; + +static int ipq5424_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5424_pinctrl); +} + +static const struct of_device_id ipq5424_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5424-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq5424_pinctrl_of_match); + +static struct platform_driver ipq5424_pinctrl_driver = { + .driver = { + .name = "ipq5424-tlmm", + .of_match_table = ipq5424_pinctrl_of_match, + }, + .probe = ipq5424_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5424_pinctrl_init(void) +{ + return platform_driver_register(&ipq5424_pinctrl_driver); +} +arch_initcall(ipq5424_pinctrl_init); + +static void __exit ipq5424_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5424_pinctrl_driver); +} +module_exit(ipq5424_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ5424 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index ac330d8712b5..0ad08647dbcd 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -1080,7 +1080,7 @@ static struct platform_driver ipq6018_pinctrl_driver = { .of_match_table = ipq6018_pinctrl_of_match, }, .probe = ipq6018_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq6018_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index e10e1bc4c911..e2bb94e86aef 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -631,7 +631,7 @@ static struct platform_driver ipq8064_pinctrl_driver = { .of_match_table = ipq8064_pinctrl_of_match, }, .probe = ipq8064_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq8064_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index fee32c1d1d3e..337f3a1c92c1 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -1041,7 +1041,7 @@ static struct platform_driver ipq8074_pinctrl_driver = { .of_match_table = ipq8074_pinctrl_of_match, }, .probe = ipq8074_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq8074_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c index 20ab59cb621b..e2491617b236 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq9574.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -799,7 +799,7 @@ static struct platform_driver ipq9574_pinctrl_driver = { .of_match_table = ipq9574_pinctrl_of_match, }, .probe = ipq9574_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init ipq9574_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index 415d24e16267..e7cd3ef1cf3e 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -1059,7 +1059,7 @@ static struct platform_driver mdm9607_pinctrl_driver = { .of_match_table = mdm9607_pinctrl_of_match, }, .probe = mdm9607_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init mdm9607_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c index 3f2eafea0b24..0a2ae383d3d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -446,7 +446,7 @@ static struct platform_driver mdm9615_pinctrl_driver = { .of_match_table = mdm9615_pinctrl_of_match, }, .probe = mdm9615_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init mdm9615_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index aeaf0d1958f5..ec913c2e200f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1457,7 +1457,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) * files which don't set the "gpio-ranges" property or systems that * utilize ACPI the driver has to call gpiochip_add_pin_range(). */ - if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); if (ret) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index 40806c0650ef..64fee70f1772 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -654,7 +654,7 @@ static struct platform_driver msm8226_pinctrl_driver = { .of_match_table = msm8226_pinctrl_of_match, }, .probe = msm8226_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8226_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index dba6d531b4a1..999a5f867eb5 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -981,7 +981,7 @@ static struct platform_driver msm8660_pinctrl_driver = { .of_match_table = msm8660_pinctrl_of_match, }, .probe = msm8660_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8660_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c index 14b17ba9f906..756856d20d6b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8909.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c @@ -929,7 +929,7 @@ static struct platform_driver msm8909_pinctrl_driver = { .of_match_table = msm8909_pinctrl_of_match, }, .probe = msm8909_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8909_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 184dcf842273..cea5c54f92fe 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -969,7 +969,7 @@ static struct platform_driver msm8916_pinctrl_driver = { .of_match_table = msm8916_pinctrl_of_match, }, .probe = msm8916_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8916_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index c2253821ae8d..998351bdfee1 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -1816,7 +1816,7 @@ static struct platform_driver msm8953_pinctrl_driver = { .of_match_table = msm8953_pinctrl_of_match, }, .probe = msm8953_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8953_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index 6b9148d226e9..ebe230b3b437 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -1246,7 +1246,7 @@ static struct platform_driver msm8960_pinctrl_driver = { .of_match_table = msm8960_pinctrl_of_match, }, .probe = msm8960_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8960_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index 9a951888e8a1..c30d80e4e98c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -1096,7 +1096,7 @@ static struct platform_driver msm8976_pinctrl_driver = { .of_match_table = msm8976_pinctrl_of_match, }, .probe = msm8976_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8976_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index 1ed1dd32d6c7..b1a6759ab4a5 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -1343,7 +1343,7 @@ static struct platform_driver msm8994_pinctrl_driver = { .of_match_table = msm8994_pinctrl_of_match, }, .probe = msm8994_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8994_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index 777c2a74036e..1b5d80eaab83 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1920,7 +1920,7 @@ static struct platform_driver msm8996_pinctrl_driver = { .of_match_table = msm8996_pinctrl_of_match, }, .probe = msm8996_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8996_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index 4aaf45e54f3a..b7cbf32b3125 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -1535,7 +1535,7 @@ static struct platform_driver msm8998_pinctrl_driver = { .of_match_table = msm8998_pinctrl_of_match, }, .probe = msm8998_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8998_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 750a8272ded7..238c83f6ec4f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -1083,7 +1083,7 @@ static struct platform_driver msm8x74_pinctrl_driver = { .of_match_table = msm8x74_pinctrl_of_match, }, .probe = msm8x74_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init msm8x74_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index f5c1c427b44e..ba699eac9ee8 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -1113,7 +1113,7 @@ static struct platform_driver qcm2290_pinctrl_driver = { .of_match_table = qcm2290_pinctrl_of_match, }, .probe = qcm2290_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init qcm2290_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 9a875b7dc998..ae7224012f8a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -1644,7 +1644,7 @@ static struct platform_driver qcs404_pinctrl_driver = { .of_match_table = qcs404_pinctrl_of_match, }, .probe = qcs404_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init qcs404_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c new file mode 100644 index 000000000000..23015b055f6a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -0,0 +1,1107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +enum { + SOUTH, + EAST, + WEST +}; + +static const char * const qcs615_tiles[] = { + [SOUTH] = "south", + [EAST] = "east", + [WEST] = "west" +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = _tile, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = WEST, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc qcs615_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "UFS_RESET"), + PINCTRL_PIN(124, "SDC1_RCLK"), + PINCTRL_PIN(125, "SDC1_CLK"), + PINCTRL_PIN(126, "SDC1_CMD"), + PINCTRL_PIN(127, "SDC1_DATA"), + PINCTRL_PIN(128, "SDC2_CLK"), + PINCTRL_PIN(129, "SDC2_CMD"), + PINCTRL_PIN(130, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); + +static const unsigned int ufs_reset_pins[] = { 123 }; +static const unsigned int sdc1_rclk_pins[] = { 124 }; +static const unsigned int sdc1_clk_pins[] = { 125 }; +static const unsigned int sdc1_cmd_pins[] = { 126 }; +static const unsigned int sdc1_data_pins[] = { 127 }; +static const unsigned int sdc2_clk_pins[] = { 128 }; +static const unsigned int sdc2_cmd_pins[] = { 129 }; +static const unsigned int sdc2_data_pins[] = { 130 }; + +enum qcs615_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_usb, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_copy_gp, + msm_mux_copy_phase, + msm_mux_cri_trng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dp_hot, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_emac_gcc, + msm_mux_emac_phy_intr, + msm_mux_forced_usb, + msm_mux_gcc_gp, + msm_mux_gp_pdm, + msm_mux_gps_tx, + msm_mux_hs0_mi2s, + msm_mux_hs1_mi2s, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mclk1, + msm_mux_mclk2, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync4_out, + msm_mux_mdp_vsync5_out, + msm_mux_mi2s_1, + msm_mux_mss_lte, + msm_mux_nav_pps_in, + msm_mux_nav_pps_out, + msm_mux_pa_indicator_or, + msm_mux_pcie_clk_req, + msm_mux_pcie_ep_rst, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset_n, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_rgmii, + msm_mux_sd_write_protect, + msm_mux_sp_cmu, + msm_mux_ter_mi2s, + msm_mux_tgu_ch, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_usb0_hs, + msm_mux_usb1_hs, + msm_mux_usb_phy_ps, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wlan, + msm_mux_wsa_clk, + msm_mux_wsa_data, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", +}; + +static const char *const adsp_ext_groups[] = { + "gpio118", +}; + +static const char *const agera_pll_groups[] = { + "gpio28", +}; + +static const char *const aoss_cti_groups[] = { + "gpio76", +}; + +static const char *const atest_char_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", + "gpio115", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", +}; + +static const char *const atest_tsens_groups[] = { + "gpio7", "gpio29", +}; + +static const char *const atest_usb_groups[] = { + "gpio7", "gpio10", "gpio11", "gpio54", + "gpio55", "gpio67", "gpio68", "gpio76", + "gpio75", "gpio77", +}; + +static const char *const cam_mclk_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const cci_async_groups[] = { + "gpio26", "gpio41", "gpio42", +}; + +static const char *const cci_i2c_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const cci_timer_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio41", + "gpio42", +}; + +static const char *const copy_gp_groups[] = { + "gpio86", +}; + +static const char *const copy_phase_groups[] = { + "gpio103", +}; + +static const char *const cri_trng_groups[] = { + "gpio60", "gpio61", "gpio62", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio11", +}; + +static const char *const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio6", "gpio7", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio54", "gpio55", +}; + +static const char *const dp_hot_groups[] = { + "gpio102", "gpio103", "gpio104", +}; + +static const char *const edp_hot_groups[] = { + "gpio113", +}; + +static const char *const edp_lcd_groups[] = { + "gpio119", +}; + +static const char *const emac_gcc_groups[] = { + "gpio101", "gpio102", +}; + +static const char *const emac_phy_intr_groups[] = { + "gpio89", +}; + +static const char *const forced_usb_groups[] = { + "gpio43", +}; + +static const char *const gcc_gp_groups[] = { + "gpio21", "gpio22", "gpio57", "gpio58", + "gpio59", "gpio78", +}; + +static const char *const gp_pdm_groups[] = { + "gpio8", "gpio54", "gpio63", "gpio66", + "gpio79", "gpio95", +}; + +static const char *const gps_tx_groups[] = { + "gpio53", "gpio54", "gpio56", "gpio57", + "gpio59", "gpio60", +}; + +static const char *const hs0_mi2s_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const hs1_mi2s_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const jitter_bist_groups[] = { + "gpio12", "gpio26", +}; + +static const char *const ldo_en_groups[] = { + "gpio97", +}; + +static const char *const ldo_update_groups[] = { + "gpio98", +}; + +static const char *const m_voc_groups[] = { + "gpio120", +}; + +static const char *const mclk1_groups[] = { + "gpio121", +}; + +static const char *const mclk2_groups[] = { + "gpio122", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio90", + "gpio97", "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio90", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio90", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio90", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio90", +}; + +static const char *const mdp_vsync4_out_groups[] = { + "gpio90", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio90", +}; + +static const char *const mi2s_1_groups[] = { + "gpio108", "gpio109", "gpio110", "gpio111", +}; + +static const char *const mss_lte_groups[] = { + "gpio106", "gpio107", +}; + +static const char *const nav_pps_in_groups[] = { + "gpio53", "gpio56", "gpio57", "gpio59", + "gpio60", +}; + +static const char *const nav_pps_out_groups[] = { + "gpio53", "gpio56", "gpio57", "gpio59", + "gpio60", +}; + +static const char *const pa_indicator_or_groups[] = { + "gpio53", +}; + +static const char *const pcie_clk_req_groups[] = { + "gpio90", +}; + +static const char *const pcie_ep_rst_groups[] = { + "gpio89", +}; + +static const char *const phase_flag_groups[] = { + "gpio10", "gpio18", "gpio19", "gpio20", + "gpio23", "gpio24", "gpio25", "gpio38", + "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio53", "gpio54", + "gpio55", "gpio67", "gpio68", "gpio75", + "gpio76", "gpio77", "gpio78", "gpio79", + "gpio80", "gpio82", "gpio84", "gpio92", + "gpio116", "gpio117", "gpio118", "gpio119", +}; + +static const char *const pll_bist_groups[] = { + "gpio27", +}; + +static const char *const pll_bypassnl_groups[] = { + "gpio13", +}; + +static const char *const pll_reset_n_groups[] = { + "gpio14", +}; + +static const char *const prng_rosc_groups[] = { + "gpio99", "gpio102", +}; + +static const char *const qdss_cti_groups[] = { + "gpio83", "gpio96", "gpio97", "gpio98", + "gpio103", "gpio104", "gpio112", "gpio113", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio14", "gpio15", "gpio20", "gpio21", + "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", + "gpio44", "gpio45", "gpio46", "gpio47", + "gpio81", "gpio82", "gpio92", "gpio93", + "gpio94", "gpio95", "gpio108", "gpio109", + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qlink_enable_groups[] = { + "gpio52", +}; + +static const char *const qlink_request_groups[] = { + "gpio51", +}; + +static const char *const qspi_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", +}; + +static const char *const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio16", "gpio17", + "gpio18", "gpio19", +}; + +static const char *const qup1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio20", "gpio21", + "gpio22", "gpio23", +}; + +static const char *const rgmii_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio102", "gpio103", + "gpio112", "gpio113", "gpio114", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio24", +}; + +static const char *const sp_cmu_groups[] = { + "gpio64", +}; + +static const char *const ter_mi2s_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", +}; + +static const char *const tgu_ch_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; + +static const char *const uim1_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", +}; + +static const char *const uim2_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", +}; + +static const char *const usb0_hs_groups[] = { + "gpio88", +}; + +static const char *const usb1_hs_groups[] = { + "gpio89", +}; + +static const char *const usb_phy_ps_groups[] = { + "gpio104", +}; + +static const char *const vfr_1_groups[] = { + "gpio92", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio7", +}; + +static const char *const wlan_groups[] = { + "gpio16", "gpio17", "gpio47", "gpio48", +}; + +static const char *const wsa_clk_groups[] = { + "gpio111", +}; + +static const char *const wsa_data_groups[] = { + "gpio110", +}; + +static const struct pinfunction qcs615_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(copy_gp), + MSM_PIN_FUNCTION(copy_phase), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(emac_gcc), + MSM_PIN_FUNCTION(emac_phy_intr), + MSM_PIN_FUNCTION(forced_usb), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gp_pdm), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(hs0_mi2s), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mclk1), + MSM_PIN_FUNCTION(mclk2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync4_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(mi2s_1), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps_in), + MSM_PIN_FUNCTION(nav_pps_out), + MSM_PIN_FUNCTION(pa_indicator_or), + MSM_PIN_FUNCTION(pcie_clk_req), + MSM_PIN_FUNCTION(pcie_ep_rst), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset_n), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb_phy_ps), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wlan), + MSM_PIN_FUNCTION(wsa_clk), + MSM_PIN_FUNCTION(wsa_data), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qcs615_groups[] = { + [0] = PINGROUP(0, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), + [1] = PINGROUP(1, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), + [2] = PINGROUP(2, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), + [3] = PINGROUP(3, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), + [4] = PINGROUP(4, WEST, qup0, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, WEST, qup0, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, EAST, qup1, qdss_gpio, ddr_pxi, _, _, _, _, _, _), + [7] = PINGROUP(7, EAST, qup1, ddr_bist, qdss_gpio, atest_tsens, + vsense_trigger_mirnat, atest_usb, ddr_pxi, _, _), + [8] = PINGROUP(8, EAST, qup1, gp_pdm, ddr_bist, qdss_gpio, _, _, _, _, _), + [9] = PINGROUP(9, EAST, qup1, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [10] = PINGROUP(10, EAST, qup1, ddr_bist, _, phase_flag, atest_usb, ddr_pxi, _, _, _), + [11] = PINGROUP(11, EAST, qup1, dbg_out_clk, atest_usb, ddr_pxi, _, _, _, _, _), + [12] = PINGROUP(12, EAST, qup1, jitter_bist, ddr_pxi, _, _, _, _, _, _), + [13] = PINGROUP(13, EAST, qup1, pll_bypassnl, _, ddr_pxi, _, _, _, _, _), + [14] = PINGROUP(14, EAST, qup1, pll_reset_n, _, qdss_gpio, _, _, _, _, _), + [15] = PINGROUP(15, EAST, qup1, qdss_gpio, _, _, _, _, _, _, _), + [16] = PINGROUP(16, WEST, qup0, _, wlan, _, _, _, _, _, _), + [17] = PINGROUP(17, WEST, qup0, _, wlan, _, _, _, _, _, _), + [18] = PINGROUP(18, WEST, qup0, _, phase_flag, _, _, _, _, _, _), + [19] = PINGROUP(19, WEST, qup0, _, phase_flag, _, _, _, _, _, _), + [20] = PINGROUP(20, SOUTH, qup1, _, phase_flag, qdss_gpio, _, _, _, _, _), + [21] = PINGROUP(21, SOUTH, qup1, gcc_gp, _, qdss_gpio, _, _, _, _, _), + [22] = PINGROUP(22, SOUTH, qup1, gcc_gp, _, _, _, _, _, _, _), + [23] = PINGROUP(23, SOUTH, qup1, _, phase_flag, _, _, _, _, _, _), + [24] = PINGROUP(24, EAST, hs1_mi2s, sd_write_protect, _, phase_flag, _, _, _, _, _), + [25] = PINGROUP(25, EAST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [26] = PINGROUP(26, EAST, cci_async, hs1_mi2s, jitter_bist, _, _, _, _, _, _), + [27] = PINGROUP(27, EAST, hs1_mi2s, pll_bist, _, _, _, _, _, _, _), + [28] = PINGROUP(28, EAST, cam_mclk, agera_pll, qdss_gpio, _, _, _, _, _, _), + [29] = PINGROUP(29, EAST, cam_mclk, _, qdss_gpio, atest_tsens, _, _, _, _, _), + [30] = PINGROUP(30, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [31] = PINGROUP(31, EAST, cam_mclk, _, qdss_gpio, _, _, _, _, _, _), + [32] = PINGROUP(32, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), + [33] = PINGROUP(33, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), + [34] = PINGROUP(34, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), + [35] = PINGROUP(35, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), + [36] = PINGROUP(36, EAST, hs0_mi2s, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _), + [38] = PINGROUP(38, EAST, cci_timer, hs0_mi2s, _, phase_flag, _, _, _, _, _), + [39] = PINGROUP(39, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, _, phase_flag, _, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _), + [42] = PINGROUP(42, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _), + [43] = PINGROUP(43, SOUTH, _, phase_flag, forced_usb, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _), + [45] = PINGROUP(45, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _), + [46] = PINGROUP(46, EAST, qspi, _, qdss_gpio, _, _, _, _, _, _), + [47] = PINGROUP(47, EAST, qspi, _, qdss_gpio, wlan, _, _, _, _, _), + [48] = PINGROUP(48, EAST, qspi, _, wlan, _, _, _, _, _, _), + [49] = PINGROUP(49, EAST, qspi, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, EAST, qspi, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qlink_request, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, pa_indicator_or, nav_pps_in, nav_pps_out, gps_tx, _, + phase_flag, _, _, _), + [54] = PINGROUP(54, SOUTH, _, gps_tx, gp_pdm, _, phase_flag, atest_usb, ddr_pxi, _, _), + [55] = PINGROUP(55, SOUTH, _, _, phase_flag, atest_usb, ddr_pxi, _, _, _, _), + [56] = PINGROUP(56, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, _, nav_pps_in, gps_tx, nav_pps_out, gcc_gp, _, _, _, _), + [58] = PINGROUP(58, SOUTH, _, gcc_gp, _, _, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, gcc_gp, _, _, _, _), + [60] = PINGROUP(60, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, cri_trng, _, _, _, _), + [61] = PINGROUP(61, SOUTH, _, cri_trng, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, _, cri_trng, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, _, _, gp_pdm, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, _, sp_cmu, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, SOUTH, _, gp_pdm, _, _, _, _, _, _, _), + [67] = PINGROUP(67, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _), + [68] = PINGROUP(68, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _), + [69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, uim2, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, uim2, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, uim2, _, phase_flag, atest_usb, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, uim2, _, phase_flag, atest_usb, aoss_cti, _, _, _, _), + [77] = PINGROUP(77, SOUTH, uim1, _, phase_flag, atest_usb, _, _, _, _, _), + [78] = PINGROUP(78, SOUTH, uim1, gcc_gp, _, phase_flag, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, uim1, gp_pdm, _, phase_flag, _, _, _, _, _), + [80] = PINGROUP(80, SOUTH, uim1, _, phase_flag, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, rgmii, mdp_vsync, _, qdss_gpio, _, _, _, _, _), + [82] = PINGROUP(82, WEST, rgmii, mdp_vsync, _, phase_flag, qdss_gpio, _, _, _, _), + [83] = PINGROUP(83, WEST, rgmii, mdp_vsync, _, qdss_cti, _, _, _, _, _), + [84] = PINGROUP(84, SOUTH, _, phase_flag, atest_char, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, _, atest_char, _, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, copy_gp, _, atest_char, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, _, atest_char, _, _, _, _, _, _, _), + [88] = PINGROUP(88, WEST, _, usb0_hs, _, _, _, _, _, _, _), + [89] = PINGROUP(89, WEST, emac_phy_intr, pcie_ep_rst, tgu_ch, usb1_hs, _, _, _, _, _), + [90] = PINGROUP(90, WEST, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, + mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, mdp_vsync5_out, + pcie_clk_req, tgu_ch), + [91] = PINGROUP(91, WEST, rgmii, tgu_ch, _, _, _, _, _, _, _), + [92] = PINGROUP(92, WEST, rgmii, vfr_1, tgu_ch, _, phase_flag, qdss_gpio, _, _, _), + [93] = PINGROUP(93, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _), + [94] = PINGROUP(94, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, rgmii, gp_pdm, qdss_gpio, _, _, _, _, _, _), + [96] = PINGROUP(96, WEST, rgmii, qdss_cti, _, _, _, _, _, _, _), + [97] = PINGROUP(97, WEST, rgmii, mdp_vsync, ldo_en, qdss_cti, _, _, _, _, _), + [98] = PINGROUP(98, WEST, mdp_vsync, ldo_update, qdss_cti, _, _, _, _, _, _), + [99] = PINGROUP(99, EAST, prng_rosc, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, WEST, emac_gcc, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, WEST, rgmii, dp_hot, emac_gcc, prng_rosc, _, _, _, _, _), + [103] = PINGROUP(103, WEST, rgmii, dp_hot, copy_phase, qdss_cti, _, _, _, _, _), + [104] = PINGROUP(104, WEST, usb_phy_ps, _, qdss_cti, dp_hot, _, _, _, _, _), + [105] = PINGROUP(105, SOUTH, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, EAST, mss_lte, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, EAST, mss_lte, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _), + [110] = PINGROUP(110, SOUTH, wsa_data, mi2s_1, _, _, _, _, _, _, _), + [111] = PINGROUP(111, SOUTH, wsa_clk, mi2s_1, _, _, _, _, _, _, _), + [112] = PINGROUP(112, WEST, rgmii, _, qdss_cti, _, _, _, _, _, _), + [113] = PINGROUP(113, WEST, rgmii, edp_hot, _, qdss_cti, _, _, _, _, _), + [114] = PINGROUP(114, WEST, rgmii, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, SOUTH, ter_mi2s, atest_char, _, _, _, _, _, _, _), + [116] = PINGROUP(116, SOUTH, ter_mi2s, _, phase_flag, _, _, _, _, _, _), + [117] = PINGROUP(117, SOUTH, ter_mi2s, _, phase_flag, qdss_gpio, atest_char, _, _, _, _), + [118] = PINGROUP(118, SOUTH, ter_mi2s, adsp_ext, _, phase_flag, qdss_gpio, atest_char, + _, _, _), + [119] = PINGROUP(119, SOUTH, edp_lcd, _, phase_flag, qdss_gpio, atest_char, _, _, _, _), + [120] = PINGROUP(120, SOUTH, m_voc, qdss_gpio, atest_char, _, _, _, _, _, _), + [121] = PINGROUP(121, SOUTH, mclk1, atest_char, _, _, _, _, _, _, _), + [122] = PINGROUP(122, SOUTH, mclk2, _, _, _, _, _, _, _, _), + [123] = UFS_RESET(ufs_reset, 0x9f000), + [124] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x9a000, 15, 0), + [125] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x9a000, 13, 6), + [126] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x9a000, 11, 3), + [127] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x9a000, 9, 0), + [128] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x98000, 14, 6), + [129] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x98000, 11, 3), + [130] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x98000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map qcs615_pdc_map[] = { + { 1, 45 }, { 3, 31 }, { 7, 55 }, { 9, 110 }, { 11, 34 }, + { 13, 33 }, { 14, 35 }, { 17, 46 }, { 19, 48 }, { 21, 83 }, + { 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 125 }, { 41, 47 }, + { 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 123 }, { 55, 56 }, + { 56, 57 }, { 57, 58 }, { 60, 60 }, { 71, 54 }, { 80, 73 }, + { 81, 64 }, { 82, 50 }, { 83, 65 }, { 84, 92 }, { 85, 99 }, + { 86, 67 }, { 87, 84 }, { 88, 124 }, { 89, 122 }, { 90, 69 }, + { 92, 88 }, { 93, 75 }, { 94, 91 }, { 95, 72 }, { 96, 82 }, + { 97, 74 }, { 98, 95 }, { 99, 94 }, { 100, 100 }, { 101, 40 }, + { 102, 93 }, { 103, 77 }, { 104, 78 }, { 105, 96 }, { 107, 97 }, + { 108, 111 }, { 112, 112 }, { 113, 113 }, { 117, 85 }, { 118, 102 }, + { 119, 87 }, { 120, 114 }, { 121, 89 }, { 122, 90 }, +}; + +static const struct msm_pinctrl_soc_data qcs615_tlmm = { + .pins = qcs615_pins, + .npins = ARRAY_SIZE(qcs615_pins), + .functions = qcs615_functions, + .nfunctions = ARRAY_SIZE(qcs615_functions), + .groups = qcs615_groups, + .ngroups = ARRAY_SIZE(qcs615_groups), + .ngpios = 123, + .tiles = qcs615_tiles, + .ntiles = ARRAY_SIZE(qcs615_tiles), + .wakeirq_map = qcs615_pdc_map, + .nwakeirq_map = ARRAY_SIZE(qcs615_pdc_map), +}; + +static const struct of_device_id qcs615_tlmm_of_match[] = { + { + .compatible = "qcom,qcs615-tlmm", + }, + {}, +}; + +static int qcs615_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qcs615_tlmm); +} + +static struct platform_driver qcs615_tlmm_driver = { + .driver = { + .name = "qcs615-tlmm", + .of_match_table = qcs615_tlmm_of_match, + }, + .probe = qcs615_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qcs615_tlmm_init(void) +{ + return platform_driver_register(&qcs615_tlmm_driver); +} +arch_initcall(qcs615_tlmm_init); + +static void __exit qcs615_tlmm_exit(void) +{ + platform_driver_unregister(&qcs615_tlmm_driver); +} +module_exit(qcs615_tlmm_exit); + +MODULE_DESCRIPTION("QTI QCS615 TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c new file mode 100644 index 000000000000..ba6de944a859 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -0,0 +1,1246 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode = qup_mode, \ + .offset = qup_offset, \ + } + +#define QUP_I3C_6_MODE_OFFSET 0xaf000 +#define QUP_I3C_7_MODE_OFFSET 0xb0000 +#define QUP_I3C_13_MODE_OFFSET 0xb1000 +#define QUP_I3C_14_MODE_OFFSET 0xb2000 + +static const struct pinctrl_pin_desc qcs8300_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "UFS_RESET"), + PINCTRL_PIN(134, "SDC1_RCLK"), + PINCTRL_PIN(135, "SDC1_CLK"), + PINCTRL_PIN(136, "SDC1_CMD"), + PINCTRL_PIN(137, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); + +static const unsigned int ufs_reset_pins[] = { 133 }; +static const unsigned int sdc1_rclk_pins[] = { 134 }; +static const unsigned int sdc1_clk_pins[] = { 135 }; +static const unsigned int sdc1_cmd_pins[] = { 136 }; +static const unsigned int sdc1_data_pins[] = { 137 }; + +enum qcs8300_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb2, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_lcd, + msm_mux_egpio, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_hs0_mi2s, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp_vsync, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk0, + msm_mux_mi2s_mclk1, + msm_mux_pcie0_clkreq, + msm_mux_pcie1_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup0_se7, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_sailss_emac0, + msm_mux_sailss_ospi, + msm_mux_sgmii_phy, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", +}; + +static const char *const aoss_cti_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", +}; + +static const char * const atest_char_groups[] = { + "gpio66", "gpio70", "gpio71", "gpio72", "gpio93", +}; + +static const char * const atest_usb2_groups[] = { + "gpio63", "gpio83", "gpio92", "gpio74", "gpio84", "gpio87", "gpio67", + "gpio75", "gpio85", "gpio65", "gpio68", "gpio80", "gpio64", "gpio69", + "gpio81", +}; + +static const char * const audio_ref_groups[] = { + "gpio105", +}; + +static const char * const cam_mclk_groups[] = { + "gpio67", "gpio68", "gpio69", +}; + +static const char * const cci_async_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio29", "gpio30", "gpio31", +}; + +static const char * const cci_i2c_scl_groups[] = { + "gpio58", "gpio30", "gpio60", "gpio32", "gpio62", "gpio55", +}; + +static const char * const cci_i2c_sda_groups[] = { + "gpio57", "gpio29", "gpio59", "gpio31", "gpio61", "gpio54", +}; + +static const char *const cci_timer_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio49", "gpio50", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const cri_trng_groups[] = { + "gpio92", "gpio90", "gpio91", +}; + +static const char *const dbg_out_groups[] = { + "gpio75", +}; + +static const char * const ddr_bist_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio49", "gpio50", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio52", "gpio83", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio80", "gpio81", +}; + +static const char *const edp0_hot_groups[] = { + "gpio94", +}; + +static const char *const edp0_lcd_groups[] = { + "gpio48", +}; + +static const char *const edp1_lcd_groups[] = { + "gpio49", +}; + +static const char *const egpio_groups[] = { + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", +}; + +static const char *const emac0_mcg0_groups[] = { + "gpio10", +}; + +static const char *const emac0_mcg1_groups[] = { + "gpio11", +}; + +static const char *const emac0_mcg2_groups[] = { + "gpio24", +}; + +static const char *const emac0_mcg3_groups[] = { + "gpio79", +}; + +static const char *const emac0_mdc_groups[] = { + "gpio5", +}; + +static const char *const emac0_mdio_groups[] = { + "gpio6", +}; + +static const char * const emac0_ptp_aux_groups[] = { + "gpio24", "gpio31", "gpio32", "gpio79", +}; + +static const char * const emac0_ptp_pps_groups[] = { + "gpio24", "gpio29", "gpio30", "gpio79", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio35", "gpio84", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio36", "gpio81", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio69", "gpio82", +}; + +static const char *const gcc_gp4_groups[] = { + "gpio68", "gpio83", +}; + +static const char *const gcc_gp5_groups[] = { + "gpio76", "gpio77", +}; + +static const char * const hs0_mi2s_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", "gpio37", "gpio38", + "gpio39", "gpio40", +}; + +static const char *const jitter_bist_groups[] = { + "gpio97", +}; + +static const char *const mdp0_vsync0_groups[] = { + "gpio89", +}; + +static const char *const mdp0_vsync1_groups[] = { + "gpio90", +}; + +static const char *const mdp0_vsync3_groups[] = { + "gpio91", +}; + +static const char *const mdp0_vsync6_groups[] = { + "gpio80", +}; + +static const char *const mdp0_vsync7_groups[] = { + "gpio81", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio42", "gpio52", "gpio32", +}; + +static const char *const mi2s1_data0_groups[] = { + "gpio100", +}; + +static const char *const mi2s1_data1_groups[] = { + "gpio101", +}; + +static const char *const mi2s1_sck_groups[] = { + "gpio98", +}; + +static const char *const mi2s1_ws_groups[] = { + "gpio99", +}; + +static const char *const mi2s2_data0_groups[] = { + "gpio104", +}; + +static const char *const mi2s2_data1_groups[] = { + "gpio105", +}; + +static const char *const mi2s2_sck_groups[] = { + "gpio102", +}; + +static const char *const mi2s2_ws_groups[] = { + "gpio103", +}; + +static const char *const mi2s_mclk0_groups[] = { + "gpio97", +}; + +static const char *const mi2s_mclk1_groups[] = { + "gpio109", +}; + +static const char *const pcie0_clkreq_groups[] = { + "gpio1", +}; + +static const char *const pcie1_clkreq_groups[] = { + "gpio22", +}; + +static const char *const phase_flag_groups[] = { + "gpio66", "gpio56", "gpio118", "gpio117", "gpio116", + "gpio3", "gpio114", "gpio113", "gpio112", "gpio111", + "gpio110", "gpio28", "gpio55", "gpio108", "gpio107", + "gpio106", "gpio105", "gpio104", "gpio103", "gpio102", + "gpio101", "gpio100", "gpio99", "gpio125", "gpio98", + "gpio54", "gpio25", "gpio26", "gpio122", "gpio121", + "gpio120", "gpio9", +}; + +static const char *const pll_bist_groups[] = { + "gpio107", +}; + +static const char *const pll_clk_groups[] = { + "gpio74", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio57", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio58", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio59", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio60", +}; + +static const char *const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio23", "gpio24", "gpio49", "gpio50", + "gpio51", "gpio52", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio57", "gpio58", "gpio97", "gpio106", + "gpio59", "gpio107", "gpio60", "gpio108", + "gpio36", "gpio100", "gpio61", "gpio101", + "gpio62", "gpio102", "gpio33", "gpio103", + "gpio34", "gpio104", "gpio75", "gpio105", + "gpio72", "gpio109", "gpio71", "gpio110", + "gpio70", "gpio111", "gpio63", "gpio112", + "gpio64", "gpio113", "gpio65", "gpio114", + "gpio73", "gpio98", "gpio74", "gpio99", +}; + +static const char *const qup0_se0_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; + +static const char *const qup0_se1_groups[] = { + "gpio19", "gpio20", "gpio17", "gpio18", +}; + +static const char *const qup0_se2_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char *const qup0_se3_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char *const qup0_se4_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char *const qup0_se5_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24", +}; + +static const char *const qup0_se6_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup0_se7_groups[] = { + "gpio43", "gpio44", "gpio43", "gpio44", +}; + +static const char *const qup1_se0_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", +}; + +static const char *const qup1_se1_groups[] = { + "gpio39", "gpio40", "gpio37", "gpio38", +}; + +static const char *const qup1_se2_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", +}; + +static const char *const qup1_se3_groups[] = { + "gpio41", "gpio42", "gpio41", "gpio42", +}; + +static const char *const qup1_se4_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const qup1_se5_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; + +static const char *const qup1_se6_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; + +static const char *const qup1_se7_groups[] = { + "gpio91", "gpio92", "gpio89", "gpio90", +}; + +static const char *const qup2_se0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", +}; + +static const char *const sailss_emac0_groups[] = { + "gpio15", "gpio16", +}; + +static const char *const sailss_ospi_groups[] = { + "gpio15", "gpio16", +}; + +static const char *const sgmii_phy_groups[] = { + "gpio4", +}; + +static const char *const tb_trig_groups[] = { + "gpio14", +}; + +static const char *const tgu_ch0_groups[] = { + "gpio43", +}; + +static const char *const tgu_ch1_groups[] = { + "gpio44", +}; + +static const char *const tgu_ch2_groups[] = { + "gpio29", +}; + +static const char *const tgu_ch3_groups[] = { + "gpio30", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio79", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio78", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio77", +}; + +static const char *const tsense_pwm4_groups[] = { + "gpio76", +}; + +static const char *const usb2phy_ac_groups[] = { + "gpio7", "gpio8", +}; + +static const char *const vsense_trigger_groups[] = { + "gpio67", +}; + +static const struct pinfunction qcs8300_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(emac0_mcg0), + MSM_PIN_FUNCTION(emac0_mcg1), + MSM_PIN_FUNCTION(emac0_mcg2), + MSM_PIN_FUNCTION(emac0_mcg3), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp_aux), + MSM_PIN_FUNCTION(emac0_ptp_pps), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp4), + MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(hs0_mi2s), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(hs2_mi2s), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp0_vsync0), + MSM_PIN_FUNCTION(mdp0_vsync1), + MSM_PIN_FUNCTION(mdp0_vsync3), + MSM_PIN_FUNCTION(mdp0_vsync6), + MSM_PIN_FUNCTION(mdp0_vsync7), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mi2s_mclk0), + MSM_PIN_FUNCTION(mi2s_mclk1), + MSM_PIN_FUNCTION(pcie0_clkreq), + MSM_PIN_FUNCTION(pcie1_clkreq), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup0_se7), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(sailss_emac0), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sgmii_phy), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qcs8300_groups[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, phase_flag, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, sgmii_phy, qdss_cti, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, emac0_mdc, qdss_cti, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, emac0_mdio, _, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, usb2phy_ac, _, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, usb2phy_ac, _, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, phase_flag, _, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup2_se0, emac0_mcg0, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup2_se0, emac0_mcg1, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup2_se0, tb_trig, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup2_se0, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup2_se0, _, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se5, cci_timer, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, pcie1_clkreq, qup0_se5, cci_timer, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se5, cci_timer, qdss_cti, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se5, emac0_ptp_aux, emac0_ptp_pps, qdss_cti, + emac0_mcg2, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se3, _, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_pps, + tgu_ch2, _, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, + tgu_ch3, _, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup0_se2, gcc_gp2, qdss_gpio, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se3, _, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se3, _, mdp_vsync, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup0_se7, _, tgu_ch0, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup0_se7, _, tgu_ch1, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, hs1_mi2s, edp0_lcd, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, edp1_lcd, + ddr_pxi1, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, _, ddr_pxi1, _, _, _, _, _), + [51] = PINGROUP(51, qup1_se5, hs2_mi2s, qdss_cti, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se5, hs2_mi2s, qdss_cti, mdp_vsync, ddr_pxi2, _, _, _, _, _, _), + [53] = PINGROUP(53, ddr_bist, _, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, cci_i2c_sda, phase_flag, ddr_bist, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, cci_i2c_scl, phase_flag, ddr_bist, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, phase_flag, ddr_bist, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, cci_i2c_sda, prng_rosc0, qdss_gpio, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, cci_i2c_scl, prng_rosc1, qdss_gpio, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, cci_i2c_sda, prng_rosc2, qdss_gpio, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, cci_i2c_scl, prng_rosc3, qdss_gpio, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), + [64] = PINGROUP(64, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), + [66] = PINGROUP(66, phase_flag, _, atest_char, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, cam_mclk, vsense_trigger, atest_usb2, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cam_mclk, gcc_gp4, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cam_mclk, gcc_gp3, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, qdss_gpio, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, _, dbg_out, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), + [76] = PINGROUP(76, gcc_gp5, tsense_pwm4, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, gcc_gp5, tsense_pwm3, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, tsense_pwm2, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, emac0_ptp_aux, emac0_ptp_pps, emac0_mcg3, _, + tsense_pwm1, _, _, _, _, _, _), + [80] = PINGROUP(80, qup0_se6, mdp0_vsync6, _, atest_usb2, ddr_pxi3, _, _, _, _, _, _), + [81] = PINGROUP(81, qup0_se6, mdp0_vsync7, gcc_gp2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), + [82] = PINGROUP(82, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup0_se6, gcc_gp4, _, atest_usb2, ddr_pxi2, _, _, _, _, _, _), + [84] = PINGROUP(84, qup1_se2, gcc_gp1, _, atest_usb2, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qup1_se6, qup1_se7, mdp0_vsync0, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, qup1_se6, qup1_se7, mdp0_vsync1, cri_trng, _, _, _, _, _, _, _), + [91] = PINGROUP(91, qup1_se7, qup1_se6, mdp0_vsync3, cri_trng, _, _, _, _, _, _, _), + [92] = PINGROUP(92, qup1_se7, qup1_se6, cri_trng, _, atest_usb2, _, _, _, _, _, _), + [93] = PINGROUP(93, atest_char, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, edp0_hot, _, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, _, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mi2s_mclk0, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [99] = PINGROUP(99, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, mi2s2_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [105] = PINGROUP(105, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [106] = PINGROUP(106, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [107] = PINGROUP(107, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), + [109] = PINGROUP(109, hs0_mi2s, mi2s_mclk1, qdss_gpio, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [111] = PINGROUP(111, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [112] = PINGROUP(112, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [113] = PINGROUP(113, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [114] = PINGROUP(114, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, egpio), + [116] = PINGROUP(116, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [117] = PINGROUP(117, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [118] = PINGROUP(118, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, egpio), + [120] = PINGROUP(120, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [121] = PINGROUP(121, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [122] = PINGROUP(122, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, egpio), + [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _, _, egpio), + [125] = PINGROUP(125, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _, _, egpio), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _, _, egpio), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _, egpio), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _, _, egpio), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, egpio), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _, egpio), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio), + [133] = UFS_RESET(ufs_reset, 0x92000), + [134] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x89000, 15, 0), + [135] = SDC_QDSD_PINGROUP(sdc1_clk, 0x89000, 13, 6), + [136] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x89000, 11, 3), + [137] = SDC_QDSD_PINGROUP(sdc1_data, 0x89000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map qcs8300_pdc_map[] = { + { 0, 169 }, { 1, 174 }, { 2, 221 }, { 3, 176 }, { 4, 171 }, + { 9, 198 }, { 10, 187 }, { 11, 188 }, { 13, 211 }, { 16, 203 }, + { 17, 213 }, { 18, 209 }, { 19, 201 }, { 20, 230 }, { 21, 231 }, + { 22, 175 }, { 23, 170 }, { 24, 232 }, { 28, 235 }, { 29, 216 }, + { 31, 208 }, { 32, 200 }, { 36, 212 }, { 37, 177 }, { 38, 178 }, + { 39, 184 }, { 40, 185 }, { 42, 186 }, { 44, 194 }, { 45, 173 }, + { 48, 195 }, { 51, 215 }, { 52, 197 }, { 53, 192 }, { 56, 193 }, + { 66, 238 }, { 67, 172 }, { 68, 182 }, { 69, 179 }, { 70, 181 }, + { 71, 202 }, { 72, 183 }, { 73, 189 }, { 74, 196 }, { 75, 190 }, + { 76, 191 }, { 77, 204 }, { 78, 206 }, { 79, 207 }, { 83, 214 }, + { 84, 205 }, { 87, 237 }, { 89, 225 }, { 90, 217 }, { 91, 218 }, + { 92, 226 }, { 93, 227 }, { 94, 228 }, { 95, 236 }, { 97, 199 }, + { 98, 229 }, { 99, 180 }, { 100, 220 }, { 101, 239 }, { 102, 219 }, + { 103, 233 }, { 104, 234 }, { 105, 223 }, { 129, 210 }, { 130, 222 }, +}; + +static const struct msm_pinctrl_soc_data qcs8300_pinctrl = { + .pins = qcs8300_pins, + .npins = ARRAY_SIZE(qcs8300_pins), + .functions = qcs8300_functions, + .nfunctions = ARRAY_SIZE(qcs8300_functions), + .groups = qcs8300_groups, + .ngroups = ARRAY_SIZE(qcs8300_groups), + .ngpios = 133, + .wakeirq_map = qcs8300_pdc_map, + .nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map), + .egpio_func = 11, +}; + +static int qcs8300_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qcs8300_pinctrl); +} + +static const struct of_device_id qcs8300_pinctrl_of_match[] = { + { .compatible = "qcom,qcs8300-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcs8300_pinctrl_of_match); + +static struct platform_driver qcs8300_pinctrl_driver = { + .driver = { + .name = "qcs8300-tlmm", + .of_match_table = qcs8300_pinctrl_of_match, + }, + .probe = qcs8300_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qcs8300_pinctrl_init(void) +{ + return platform_driver_register(&qcs8300_pinctrl_driver); +} +arch_initcall(qcs8300_pinctrl_init); + +static void __exit qcs8300_pinctrl_exit(void) +{ + platform_driver_unregister(&qcs8300_pinctrl_driver); +} +module_exit(qcs8300_pinctrl_exit); + +MODULE_DESCRIPTION("QTI QCS8300 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index 4d2f6f495163..b5808fcfb13c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -145,7 +145,7 @@ static struct platform_driver qdf2xxx_pinctrl_driver = { .acpi_match_table = qdf2xxx_acpi_ids, }, .probe = qdf2xxx_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init qdf2xxx_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index da4f940bc8d4..47bc529ef550 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -1248,7 +1248,7 @@ static struct platform_driver qdu1000_tlmm_driver = { .of_match_table = qdu1000_tlmm_of_match, }, .probe = qdu1000_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init qdu1000_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 5459c0c681a2..8fdea25d8d67 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -1530,7 +1530,7 @@ static struct platform_driver sa8775p_pinctrl_driver = { .of_match_table = sa8775p_pinctrl_of_match, }, .probe = sa8775p_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sa8775p_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sar2130p.c b/drivers/pinctrl/qcom/pinctrl-sar2130p.c new file mode 100644 index 000000000000..19a2e37826c7 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sar2130p.c @@ -0,0 +1,1505 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sar2130p_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "SDC1_RCLK"), + PINCTRL_PIN(157, "SDC1_CLK"), + PINCTRL_PIN(158, "SDC1_CMD"), + PINCTRL_PIN(159, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); + +static const unsigned int sdc1_rclk_pins[] = { 156 }; +static const unsigned int sdc1_clk_pins[] = { 157 }; +static const unsigned int sdc1_cmd_pins[] = { 158 }; +static const unsigned int sdc1_data_pins[] = { 159 }; + +enum sar2130p_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_usb0, + msm_mux_atest_usb00, + msm_mux_atest_usb01, + msm_mux_atest_usb02, + msm_mux_atest_usb03, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp0_hot, + msm_mux_ext_mclk0, + msm_mux_ext_mclk1, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_host2wlan_sol, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag0, + msm_mux_phase_flag1, + msm_mux_phase_flag10, + msm_mux_phase_flag11, + msm_mux_phase_flag12, + msm_mux_phase_flag13, + msm_mux_phase_flag14, + msm_mux_phase_flag15, + msm_mux_phase_flag16, + msm_mux_phase_flag17, + msm_mux_phase_flag18, + msm_mux_phase_flag19, + msm_mux_phase_flag2, + msm_mux_phase_flag20, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_phase_flag23, + msm_mux_phase_flag24, + msm_mux_phase_flag25, + msm_mux_phase_flag26, + msm_mux_phase_flag27, + msm_mux_phase_flag28, + msm_mux_phase_flag29, + msm_mux_phase_flag3, + msm_mux_phase_flag30, + msm_mux_phase_flag31, + msm_mux_phase_flag4, + msm_mux_phase_flag5, + msm_mux_phase_flag6, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_phase_flag9, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_gpio0, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio10, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio4, + msm_mux_qdss_gpio5, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_qdss_gpio8, + msm_mux_qdss_gpio9, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs0, + msm_mux_qspi_cs1, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_usb0_phy, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", +}; + +static const char * const aoss_cti_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const atest_char_groups[] = { + "gpio45", +}; + +static const char * const atest_char0_groups[] = { + "gpio90", +}; + +static const char * const atest_char1_groups[] = { + "gpio89", +}; + +static const char * const atest_char2_groups[] = { + "gpio88", +}; + +static const char * const atest_char3_groups[] = { + "gpio87", +}; + +static const char * const atest_usb0_groups[] = { + "gpio26", +}; + +static const char * const atest_usb00_groups[] = { + "gpio110", +}; + +static const char * const atest_usb01_groups[] = { + "gpio109", +}; + +static const char * const atest_usb02_groups[] = { + "gpio27", +}; + +static const char * const atest_usb03_groups[] = { + "gpio60", +}; + +static const char * const audio_ref_groups[] = { + "gpio103", +}; + +static const char * const cam_mclk_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", + "gpio76", +}; + +static const char * const cci_async_groups[] = { + "gpio80", "gpio81", "gpio82", +}; + +static const char * const cci_i2c_groups[] = { + "gpio67", "gpio68", "gpio78", "gpio79", "gpio80", "gpio81", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", +}; + +static const char * const cci_timer0_groups[] = { + "gpio77", +}; + +static const char * const cci_timer1_groups[] = { + "gpio78", +}; + +static const char * const cci_timer2_groups[] = { + "gpio79", +}; + +static const char * const cci_timer3_groups[] = { + "gpio80", +}; + +static const char * const cci_timer4_groups[] = { + "gpio81", +}; + +static const char * const cri_trng_groups[] = { + "gpio60", +}; + +static const char * const cri_trng0_groups[] = { + "gpio70", +}; + +static const char * const cri_trng1_groups[] = { + "gpio71", +}; + +static const char * const dbg_out_groups[] = { + "gpio59", +}; + +static const char * const ddr_bist_groups[] = { + "gpio4", "gpio5", "gpio100", "gpio103", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio56", "gpio57", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio41", "gpio45", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio48", "gpio55", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const dp0_hot_groups[] = { + "gpio35", "gpio103", +}; + +static const char * const ext_mclk0_groups[] = { + "gpio104", +}; + +static const char * const ext_mclk1_groups[] = { + "gpio103", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio129", "gpio132", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio130", "gpio135", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio131", "gpio136", +}; + +static const char * const host2wlan_sol_groups[] = { + "gpio111", +}; + +static const char * const i2s0_data0_groups[] = { + "gpio106", +}; + +static const char * const i2s0_data1_groups[] = { + "gpio107", +}; + +static const char * const i2s0_sck_groups[] = { + "gpio105", +}; + +static const char * const i2s0_ws_groups[] = { + "gpio108", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio91", "gpio92", +}; + +static const char * const jitter_bist_groups[] = { + "gpio0", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio12", "gpio13", "gpio41", "gpio49", "gpio50", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio49", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio49", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio50", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio50", +}; + +static const char * const pcie0_clkreqn_groups[] = { + "gpio56", +}; + +static const char * const pcie1_clkreqn_groups[] = { + "gpio59", +}; + +static const char * const phase_flag0_groups[] = { + "gpio133", +}; + +static const char * const phase_flag1_groups[] = { + "gpio128", +}; + +static const char * const phase_flag10_groups[] = { + "gpio94", +}; + +static const char * const phase_flag11_groups[] = { + "gpio93", +}; + +static const char * const phase_flag12_groups[] = { + "gpio134", +}; + +static const char * const phase_flag13_groups[] = { + "gpio139", +}; + +static const char * const phase_flag14_groups[] = { + "gpio138", +}; + +static const char * const phase_flag15_groups[] = { + "gpio137", +}; + +static const char * const phase_flag16_groups[] = { + "gpio62", +}; + +static const char * const phase_flag17_groups[] = { + "gpio61", +}; + +static const char * const phase_flag18_groups[] = { + "gpio41", +}; + +static const char * const phase_flag19_groups[] = { + "gpio23", +}; + +static const char * const phase_flag2_groups[] = { + "gpio127", +}; + +static const char * const phase_flag20_groups[] = { + "gpio22", +}; + +static const char * const phase_flag21_groups[] = { + "gpio21", +}; + +static const char * const phase_flag22_groups[] = { + "gpio19", +}; + +static const char * const phase_flag23_groups[] = { + "gpio18", +}; + +static const char * const phase_flag24_groups[] = { + "gpio17", +}; + +static const char * const phase_flag25_groups[] = { + "gpio16", +}; + +static const char * const phase_flag26_groups[] = { + "gpio13", +}; + +static const char * const phase_flag27_groups[] = { + "gpio12", +}; + +static const char * const phase_flag28_groups[] = { + "gpio3", +}; + +static const char * const phase_flag29_groups[] = { + "gpio2", +}; + +static const char * const phase_flag3_groups[] = { + "gpio126", +}; + +static const char * const phase_flag30_groups[] = { + "gpio149", +}; + +static const char * const phase_flag31_groups[] = { + "gpio148", +}; + +static const char * const phase_flag4_groups[] = { + "gpio151", +}; + +static const char * const phase_flag5_groups[] = { + "gpio150", +}; + +static const char * const phase_flag6_groups[] = { + "gpio98", +}; + +static const char * const phase_flag7_groups[] = { + "gpio97", +}; + +static const char * const phase_flag8_groups[] = { + "gpio96", +}; + +static const char * const phase_flag9_groups[] = { + "gpio95", +}; + +static const char * const pll_bist_groups[] = { + "gpio8", +}; + +static const char * const pll_clk_groups[] = { + "gpio54", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio72", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio73", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio74", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio75", +}; + +static const char * const qdss_cti_groups[] = { + "gpio28", "gpio29", "gpio36", "gpio37", "gpio38", "gpio38", "gpio47", + "gpio48", "gpio53", "gpio53", "gpio105", "gpio106", "gpio154", + "gpio155", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio89", "gpio90", "gpio109", "gpio110", +}; + +static const char * const qdss_gpio0_groups[] = { + "gpio24", "gpio65", +}; + +static const char * const qdss_gpio1_groups[] = { + "gpio25", "gpio66", +}; + +static const char * const qdss_gpio10_groups[] = { + "gpio63", "gpio83", +}; + +static const char * const qdss_gpio11_groups[] = { + "gpio64", "gpio84", +}; + +static const char * const qdss_gpio12_groups[] = { + "gpio39", "gpio85", +}; + +static const char * const qdss_gpio13_groups[] = { + "gpio10", "gpio86", +}; + +static const char * const qdss_gpio14_groups[] = { + "gpio45", "gpio87", +}; + +static const char * const qdss_gpio15_groups[] = { + "gpio11", "gpio88", +}; + +static const char * const qdss_gpio2_groups[] = { + "gpio26", "gpio67", +}; + +static const char * const qdss_gpio3_groups[] = { + "gpio27", "gpio68", +}; + +static const char * const qdss_gpio4_groups[] = { + "gpio30", "gpio77", +}; + +static const char * const qdss_gpio5_groups[] = { + "gpio31", "gpio78", +}; + +static const char * const qdss_gpio6_groups[] = { + "gpio4", "gpio79", +}; + +static const char * const qdss_gpio7_groups[] = { + "gpio5", "gpio80", +}; + +static const char * const qdss_gpio8_groups[] = { + "gpio6", "gpio81", +}; + +static const char * const qdss_gpio9_groups[] = { + "gpio7", "gpio82", +}; + +static const char * const qspi0_groups[] = { + "gpio32", +}; + +static const char * const qspi1_groups[] = { + "gpio33", +}; + +static const char * const qspi2_groups[] = { + "gpio36", +}; + +static const char * const qspi3_groups[] = { + "gpio37", +}; + +static const char * const qspi_clk_groups[] = { + "gpio34", +}; + +static const char * const qspi_cs0_groups[] = { + "gpio35", +}; + +static const char * const qspi_cs1_groups[] = { + "gpio38", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio93", +}; + +static const char * const qup1_groups[] = { + "gpio2", "gpio3", "gpio61", "gpio62", +}; + +static const char * const qup2_groups[] = { + "gpio12", "gpio13", "gpio22", "gpio23", +}; + +static const char * const qup3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio41", +}; + +static const char * const qup4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", "gpio94", +}; + +static const char * const qup5_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", +}; + +static const char * const qup6_groups[] = { + "gpio63", "gpio64", "gpio91", "gpio92", +}; + +static const char * const qup7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup8_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qup9_groups[] = { + "gpio34", "gpio35", "gpio109", "gpio110", +}; + +static const char * const qup10_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup11_groups[] = { + "gpio14", "gpio15", "gpio28", "gpio30", +}; + +static const char * const tb_trig_groups[] = { + "gpio69", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio20", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio21", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio22", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio23", +}; + +static const char * const tmess_prng0_groups[] = { + "gpio80", +}; + +static const char * const tmess_prng1_groups[] = { + "gpio79", +}; + +static const char * const tmess_prng2_groups[] = { + "gpio83", +}; + +static const char * const tmess_prng3_groups[] = { + "gpio81", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio86", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio86", +}; + +static const char * const usb0_phy_groups[] = { + "gpio100", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio36", +}; + +static const struct pinfunction sar2130p_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(phase_flag29), + MSM_PIN_FUNCTION(phase_flag28), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(qdss_gpio6), + MSM_PIN_FUNCTION(qdss_gpio7), + MSM_PIN_FUNCTION(qdss_gpio8), + MSM_PIN_FUNCTION(qdss_gpio9), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(qdss_gpio13), + MSM_PIN_FUNCTION(qdss_gpio15), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(phase_flag27), + MSM_PIN_FUNCTION(phase_flag26), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(phase_flag25), + MSM_PIN_FUNCTION(phase_flag24), + MSM_PIN_FUNCTION(phase_flag23), + MSM_PIN_FUNCTION(phase_flag22), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(phase_flag21), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(phase_flag20), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(phase_flag19), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qdss_gpio0), + MSM_PIN_FUNCTION(qdss_gpio1), + MSM_PIN_FUNCTION(qdss_gpio2), + MSM_PIN_FUNCTION(atest_usb0), + MSM_PIN_FUNCTION(qdss_gpio3), + MSM_PIN_FUNCTION(atest_usb02), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio4), + MSM_PIN_FUNCTION(qdss_gpio5), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qspi_cs0), + MSM_PIN_FUNCTION(dp0_hot), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_cs1), + MSM_PIN_FUNCTION(qdss_gpio12), + MSM_PIN_FUNCTION(phase_flag18), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(qdss_gpio14), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pcie0_clkreqn), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(pcie1_clkreqn), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(atest_usb03), + MSM_PIN_FUNCTION(phase_flag17), + MSM_PIN_FUNCTION(phase_flag16), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qdss_gpio10), + MSM_PIN_FUNCTION(qdss_gpio11), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(phase_flag11), + MSM_PIN_FUNCTION(phase_flag10), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(phase_flag9), + MSM_PIN_FUNCTION(phase_flag8), + MSM_PIN_FUNCTION(phase_flag7), + MSM_PIN_FUNCTION(phase_flag6), + MSM_PIN_FUNCTION(usb0_phy), + MSM_PIN_FUNCTION(ext_mclk1), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(ext_mclk0), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(atest_usb01), + MSM_PIN_FUNCTION(atest_usb00), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(phase_flag3), + MSM_PIN_FUNCTION(phase_flag2), + MSM_PIN_FUNCTION(phase_flag1), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(phase_flag0), + MSM_PIN_FUNCTION(phase_flag12), + MSM_PIN_FUNCTION(phase_flag15), + MSM_PIN_FUNCTION(phase_flag14), + MSM_PIN_FUNCTION(phase_flag13), + MSM_PIN_FUNCTION(phase_flag31), + MSM_PIN_FUNCTION(phase_flag30), + MSM_PIN_FUNCTION(phase_flag5), + MSM_PIN_FUNCTION(phase_flag4), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sar2130p_groups[] = { + [0] = PINGROUP(0, qup0, ibi_i3c, jitter_bist, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0, ibi_i3c, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup0, qup1, phase_flag29, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0, qup1, phase_flag28, _, _, _, _, _, _), + [4] = PINGROUP(4, qup10, ddr_bist, qdss_gpio6, _, _, _, _, _, _), + [5] = PINGROUP(5, qup10, ddr_bist, qdss_gpio7, _, _, _, _, _, _), + [6] = PINGROUP(6, qup10, qdss_gpio8, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup10, qdss_gpio9, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup8, pll_bist, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup8, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup8, qdss_gpio13, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup8, qdss_gpio15, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup2, mdp_vsync, phase_flag27, _, _, _, _, _, _), + [13] = PINGROUP(13, qup2, mdp_vsync, phase_flag26, _, _, _, _, _, _), + [14] = PINGROUP(14, qup11, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup11, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3, phase_flag25, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3, phase_flag24, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup3, phase_flag23, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup3, phase_flag22, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup4, aoss_cti, tgu_ch0, _, _, _, _, _, _), + [21] = PINGROUP(21, qup4, aoss_cti, phase_flag21, tgu_ch1, _, _, _, _, _), + [22] = PINGROUP(22, qup4, qup2, aoss_cti, phase_flag20, tgu_ch2, _, _, _, _), + [23] = PINGROUP(23, qup4, qup2, aoss_cti, phase_flag19, tgu_ch3, _, _, _, _), + [24] = PINGROUP(24, qup7, qdss_gpio0, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup7, qdss_gpio1, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup7, qdss_gpio2, atest_usb0, _, _, _, _, _, _), + [27] = PINGROUP(27, qup7, qdss_gpio3, atest_usb02, _, _, _, _, _, _), + [28] = PINGROUP(28, qup11, qdss_cti, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qdss_cti, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup11, qdss_gpio4, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qdss_gpio5, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qspi0, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qspi1, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qspi_clk, qup9, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qspi_cs0, qup9, dp0_hot, _, _, _, _, _, _), + [36] = PINGROUP(36, qspi2, qdss_cti, vsense_trigger, _, _, _, _, _, _), + [37] = PINGROUP(37, qspi3, qdss_cti, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qspi_cs1, qdss_cti, qdss_cti, _, _, _, _, _, _), + [39] = PINGROUP(39, qdss_gpio12, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup3, mdp_vsync, phase_flag18, _, ddr_pxi1, _, _, _, _), + [42] = PINGROUP(42, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qdss_gpio14, ddr_pxi1, atest_char, _, _, _, _, _, _), + [46] = PINGROUP(46, ddr_pxi3, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qdss_cti, ddr_pxi3, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qdss_cti, ddr_pxi2, _, _, _, _, _, _, _), + [49] = PINGROUP(49, mdp_vsync, mdp_vsync0, mdp_vsync1, _, _, _, _, _, _), + [50] = PINGROUP(50, mdp_vsync, mdp_vsync2, mdp_vsync3, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [54] = PINGROUP(54, pll_clk, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, ddr_pxi2, _, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie0_clkreqn, _, ddr_pxi0, _, _, _, _, _, _), + [57] = PINGROUP(57, ddr_pxi0, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, pcie1_clkreqn, dbg_out, _, _, _, _, _, _, _), + [60] = PINGROUP(60, cri_trng, atest_usb03, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1, phase_flag17, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1, phase_flag16, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup6, qdss_gpio10, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup6, qdss_gpio11, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qdss_gpio0, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qdss_gpio1, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, cci_i2c, qdss_gpio2, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cci_i2c, qdss_gpio3, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cam_mclk, tb_trig, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cam_mclk, cri_trng0, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cam_mclk, cri_trng1, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cam_mclk, prng_rosc0, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cam_mclk, prng_rosc1, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cam_mclk, prng_rosc2, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cam_mclk, prng_rosc3, _, _, _, _, _, _, _), + [76] = PINGROUP(76, cam_mclk, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, cci_timer0, qdss_gpio4, _, _, _, _, _, _, _), + [78] = PINGROUP(78, cci_timer1, cci_i2c, qdss_gpio5, _, _, _, _, _, _), + [79] = PINGROUP(79, cci_timer2, cci_i2c, tmess_prng1, qdss_gpio6, _, _, _, _, _), + [80] = PINGROUP(80, cci_timer3, cci_i2c, cci_async, tmess_prng0, qdss_gpio7, _, _, _, _), + [81] = PINGROUP(81, cci_timer4, cci_i2c, cci_async, tmess_prng3, qdss_gpio8, _, _, _, _), + [82] = PINGROUP(82, cci_async, qdss_gpio9, _, _, _, _, _, _, _), + [83] = PINGROUP(83, cci_i2c, tmess_prng2, qdss_gpio10, _, _, _, _, _, _), + [84] = PINGROUP(84, cci_i2c, qdss_gpio11, _, _, _, _, _, _, _), + [85] = PINGROUP(85, cci_i2c, qdss_gpio12, _, _, _, _, _, _, _), + [86] = PINGROUP(86, cci_i2c, qdss_gpio13, tsense_pwm1, tsense_pwm2, _, _, _, _, _), + [87] = PINGROUP(87, cci_i2c, qdss_gpio14, atest_char3, _, _, _, _, _, _), + [88] = PINGROUP(88, cci_i2c, qdss_gpio15, atest_char2, _, _, _, _, _, _), + [89] = PINGROUP(89, cci_i2c, qdss_gpio, atest_char1, _, _, _, _, _, _), + [90] = PINGROUP(90, cci_i2c, qdss_gpio, atest_char0, _, _, _, _, _, _), + [91] = PINGROUP(91, cci_i2c, qup6, ibi_i3c, _, _, _, _, _, _), + [92] = PINGROUP(92, cci_i2c, qup6, ibi_i3c, _, _, _, _, _, _), + [93] = PINGROUP(93, qup0, phase_flag11, _, _, _, _, _, _, _), + [94] = PINGROUP(94, qup4, phase_flag10, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qup5, phase_flag9, _, _, _, _, _, _, _), + [96] = PINGROUP(96, qup5, phase_flag8, _, _, _, _, _, _, _), + [97] = PINGROUP(97, qup5, phase_flag7, _, _, _, _, _, _, _), + [98] = PINGROUP(98, qup5, phase_flag6, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, usb0_phy, ddr_bist, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, ext_mclk1, audio_ref, dp0_hot, ddr_bist, _, _, _, _, _), + [104] = PINGROUP(104, ext_mclk0, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, i2s0_sck, _, qdss_cti, _, _, _, _, _, _), + [106] = PINGROUP(106, i2s0_data0, _, qdss_cti, _, _, _, _, _, _), + [107] = PINGROUP(107, i2s0_data1, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, i2s0_ws, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, qup9, qdss_gpio, atest_usb01, _, _, _, _, _, _), + [110] = PINGROUP(110, qup9, qdss_gpio, atest_usb00, _, _, _, _, _, _), + [111] = PINGROUP(111, host2wlan_sol, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, phase_flag3, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, phase_flag2, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, phase_flag1, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, gcc_gp1, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, gcc_gp2, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, gcc_gp3, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, gcc_gp1, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, phase_flag0, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, phase_flag12, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, gcc_gp2, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, gcc_gp3, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, phase_flag15, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, phase_flag14, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, phase_flag13, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, phase_flag31, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, phase_flag30, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, phase_flag5, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, phase_flag4, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, qdss_cti, _, _, _, _, _, _, _, _), + [156] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xa1000, 0, 0), + [157] = SDC_QDSD_PINGROUP(sdc1_clk, 0xa0000, 13, 6), + [158] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xa0000, 11, 3), + [159] = SDC_QDSD_PINGROUP(sdc1_data, 0xa0000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sar2130p_pdc_map[] = { + { 0, 50 }, { 3, 68 }, { 6, 88 }, { 7, 55 }, { 10, 66 }, { 11, 96 }, + { 12, 48 }, { 13, 49 }, { 15, 62 }, { 18, 57 }, { 19, 59 }, { 23, 51 }, + { 27, 74 }, { 28, 67 }, { 29, 84 }, { 30, 58 }, { 31, 94 }, { 32, 60 }, + { 33, 61 }, { 35, 69 }, { 37, 70 }, { 38, 64 }, { 39, 65 }, { 40, 63 }, + { 41, 92 }, { 42, 82 }, { 44, 83 }, { 45, 43 }, { 46, 72 }, { 47, 45 }, + { 48, 44 }, { 49, 71 }, { 50, 87 }, { 53, 77 }, { 54, 78 }, + { 55, 106 }, { 56, 79 }, { 57, 80 }, { 58, 107 }, { 59, 81 }, + { 60, 89 }, { 61, 54 }, { 62, 73 }, { 63, 93 }, { 64, 86 }, { 65, 75 }, + { 67, 42 }, { 68, 76 }, { 76, 116 }, { 77, 12 }, { 83, 13 }, + { 91, 90 }, { 94, 95 }, { 95, 91 }, { 98, 47 }, { 100, 85 }, + { 101, 52 }, { 102, 53 }, { 103, 97 }, { 104, 98 }, { 105, 99 }, + { 106, 100 }, { 107, 101 }, { 108, 102 }, { 109, 103 }, { 111, 104 }, + { 113, 46 }, { 114, 56 }, { 115, 108 }, { 116, 109 }, { 117, 110 }, + { 118, 111 }, { 121, 112 }, { 122, 113 }, { 124, 114 }, { 127, 115 }, + { 132, 118 }, { 134, 119 }, { 135, 120 }, { 136, 121 }, { 139, 122 }, + { 140, 123 }, { 141, 124 }, { 143, 128 }, { 144, 129 }, { 145, 130 }, + { 146, 131 }, { 148, 132 }, { 150, 133 }, { 151, 134 }, { 153, 135 }, + { 155, 137 }, +}; + +static const struct msm_pinctrl_soc_data sar2130p_tlmm = { + .pins = sar2130p_pins, + .npins = ARRAY_SIZE(sar2130p_pins), + .functions = sar2130p_functions, + .nfunctions = ARRAY_SIZE(sar2130p_functions), + .groups = sar2130p_groups, + .ngroups = ARRAY_SIZE(sar2130p_groups), + .ngpios = 156, + .wakeirq_map = sar2130p_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sar2130p_pdc_map), +}; + +static int sar2130p_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sar2130p_tlmm); +} + +static const struct of_device_id sar2130p_tlmm_of_match[] = { + { .compatible = "qcom,sar2130p-tlmm", .data = &sar2130p_tlmm}, + { }, +}; +MODULE_DEVICE_TABLE(of, sar2130p_tlmm_of_match); + +static struct platform_driver sar2130p_tlmm_driver = { + .driver = { + .name = "sar2130p-tlmm", + .of_match_table = sar2130p_tlmm_of_match, + }, + .probe = sar2130p_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sar2130p_tlmm_init(void) +{ + return platform_driver_register(&sar2130p_tlmm_driver); +} +arch_initcall(sar2130p_tlmm_init); + +static void __exit sar2130p_tlmm_exit(void) +{ + platform_driver_unregister(&sar2130p_tlmm_driver); +} +module_exit(sar2130p_tlmm_exit); + +MODULE_DESCRIPTION("QTI SAR2130P TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index c27aaa599b91..6eb0c73791c0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1159,7 +1159,7 @@ static struct platform_driver sc7180_pinctrl_driver = { .of_match_table = sc7180_pinctrl_of_match, }, .probe = sc7180_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sc7180_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index 6bb39812e1d8..1161f0a91a00 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -142,7 +142,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index c2db663e396e..0c10eeb60b55 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1505,7 +1505,7 @@ static struct platform_driver sc7280_pinctrl_driver = { .of_match_table = sc7280_pinctrl_of_match, }, .probe = sc7280_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sc7280_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index cfa7c8be9770..d6a79ad41a40 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1720,7 +1720,7 @@ static struct platform_driver sc8180x_pinctrl_driver = { .acpi_match_table = sc8180x_pinctrl_acpi_match, }, .probe = sc8180x_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sc8180x_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index c0369baf3398..0e839b6aaaf4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -179,7 +179,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c index 4b1c49697698..96f4fb5a5d29 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -1926,7 +1926,7 @@ static struct platform_driver sc8280xp_pinctrl_driver = { .of_match_table = sc8280xp_pinctrl_of_match, }, .probe = sc8280xp_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sc8280xp_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index b93837c00954..907e4ffca5e7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1442,7 +1442,7 @@ static struct platform_driver sdm660_pinctrl_driver = { .of_match_table = sdm660_pinctrl_of_match, }, .probe = sdm660_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdm660_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c index 894c042cb524..c76183ba95e1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -1337,7 +1337,7 @@ static struct platform_driver sdm670_pinctrl_driver = { .of_match_table = sdm670_pinctrl_of_match, }, .probe = sdm670_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdm670_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 3f3265e0018d..cc05c415ed15 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1351,7 +1351,7 @@ static struct platform_driver sdm845_pinctrl_driver = { .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match), }, .probe = sdm845_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdm845_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index c88b8bfcacb6..8826db9d21d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -990,7 +990,7 @@ static struct platform_driver sdx55_pinctrl_driver = { .of_match_table = sdx55_pinctrl_of_match, }, .probe = sdx55_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdx55_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index bd44ec0fcab4..f6f319c997fc 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -939,7 +939,7 @@ static struct platform_driver sdx65_pinctrl_driver = { .of_match_table = sdx65_pinctrl_of_match, }, .probe = sdx65_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdx65_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index 396f6fc779a2..3cfe8c7f04df 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -1124,7 +1124,7 @@ static struct platform_driver sdx75_pinctrl_driver = { .of_match_table = sdx75_pinctrl_of_match, }, .probe = sdx75_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sdx75_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c index 2d2c636a3e20..c0e178be9cfc 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -227,7 +227,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index 27317b86d835..622f20e6f6f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -994,7 +994,7 @@ static struct platform_driver sm4450_tlmm_driver = { .of_match_table = sm4450_tlmm_of_match, }, .probe = sm4450_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; MODULE_DEVICE_TABLE(of, sm4450_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c index 316d6fc69131..b7d9186861a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -147,7 +147,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 7ce04144b6ed..4e91c75ad952 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -907,7 +907,7 @@ static struct platform_driver sm6115_tlmm_driver = { .of_match_table = sm6115_tlmm_of_match, }, .probe = sm6115_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm6115_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 65de34c30759..c188842047aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1266,7 +1266,7 @@ static struct platform_driver sm6125_tlmm_driver = { .of_match_table = sm6125_tlmm_of_match, }, .probe = sm6125_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm6125_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index 4aeb1ba43ee3..f3828c07b134 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -1373,7 +1373,7 @@ static struct platform_driver sm6350_tlmm_driver = { .of_match_table = sm6350_tlmm_of_match, }, .probe = sm6350_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm6350_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index d86630d7125c..c82c8516932e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -1516,7 +1516,7 @@ static struct platform_driver sm6375_tlmm_driver = { .of_match_table = sm6375_tlmm_of_match, }, .probe = sm6375_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm6375_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c index 095a1ca75849..3c7fd8af6635 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm7150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c @@ -1255,7 +1255,7 @@ static struct platform_driver sm7150_tlmm_driver = { .of_match_table = sm7150_tlmm_of_match, }, .probe = sm7150_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm7150_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index f8f5bee74f1d..01aea9c70b7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -1542,7 +1542,7 @@ static struct platform_driver sm8150_pinctrl_driver = { .of_match_table = sm8150_pinctrl_of_match, }, .probe = sm8150_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8150_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c index 9791d9ba5087..64494a86490e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -140,7 +140,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index 54fda77bf296..e9961a49ff98 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -1351,7 +1351,7 @@ static struct platform_driver sm8250_pinctrl_driver = { .of_match_table = sm8250_pinctrl_of_match, }, .probe = sm8250_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8250_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c index 5b9a2cb216bd..7b146b4acfdf 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c @@ -142,7 +142,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index ac7f2820f2cb..9c69458bd910 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1642,7 +1642,7 @@ static struct platform_driver sm8350_tlmm_driver = { .of_match_table = sm8350_tlmm_of_match, }, .probe = sm8350_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8350_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index a028cbb49947..439f6541622e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -208,7 +208,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index 617286711695..d11bb1ee9e3d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -1677,7 +1677,7 @@ static struct platform_driver sm8450_tlmm_driver = { .of_match_table = sm8450_tlmm_of_match, }, .probe = sm8450_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8450_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c index 852192b044e1..73065919c8c2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -216,7 +216,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 9184e0183755..3c847d9cb5d9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -1762,7 +1762,7 @@ static struct platform_driver sm8550_tlmm_driver = { .of_match_table = sm8550_tlmm_of_match, }, .probe = sm8550_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8550_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c index 04400c832327..f9fcedf5a65d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -223,7 +223,7 @@ static struct platform_driver lpi_pinctrl_driver = { .of_match_table = lpi_pinctrl_of_match, }, .probe = lpi_pinctrl_probe, - .remove_new = lpi_pinctrl_remove, + .remove = lpi_pinctrl_remove, }; module_platform_driver(lpi_pinctrl_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index adaddd728662..104708252d12 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -1742,7 +1742,7 @@ static struct platform_driver sm8650_tlmm_driver = { .of_match_table = sm8650_tlmm_of_match, }, .probe = sm8650_tlmm_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init sm8650_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c new file mode 100644 index 000000000000..1af11cd95fb0 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -0,0 +1,1729 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8750_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "UFS_RESET"), + PINCTRL_PIN(216, "SDC2_CLK"), + PINCTRL_PIN(217, "SDC2_CMD"), + PINCTRL_PIN(218, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); + +static const unsigned int ufs_reset_pins[] = { 215 }; +static const unsigned int sdc2_clk_pins[] = { 216 }; +static const unsigned int sdc2_cmd_pins[] = { 217 }; +static const unsigned int sdc2_data_pins[] = { 218 }; + +enum sm8750_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_aon_mclk2, + msm_mux_cam_aon_mclk4, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gnss_adc0, + msm_mux_gnss_adc1, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2chub0_se5, + msm_mux_i2chub0_se6, + msm_mux_i2chub0_se7, + msm_mux_i2chub0_se8, + msm_mux_i2chub0_se9, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data0, + msm_mux_i2s1_data1, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0_out, + msm_mux_mdp_esync1_out, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_nav_gpio3, + msm_mux_pcie0_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qlink_big_enable, + msm_mux_qlink_big_request, + msm_mux_qlink_little_enable, + msm_mux_qlink_little_request, + msm_mux_qlink_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_sd_write_protect, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig_sdc2, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb1_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", +}; + +static const char *const egpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", + "gpio213", "gpio214", +}; + +static const char *const aoss_cti_groups[] = { + "gpio50", "gpio51", "gpio60", "gpio61", +}; + +static const char *const atest_char_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133", "gpio137", +}; + +static const char *const atest_usb_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", "gpio76", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio125", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio124", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio124", +}; + +static const char *const cam_aon_mclk2_groups[] = { + "gpio91", +}; + +static const char *const cam_aon_mclk4_groups[] = { + "gpio93", +}; + +static const char *const cam_mclk_groups[] = { + "gpio89", "gpio90", "gpio92", "gpio94", "gpio95", "gpio96", +}; + +static const char *const cci_async_in_groups[] = { + "gpio10", "gpio11", "gpio15", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio114", "gpio116", "gpio118", "gpio120", "gpio153", "gpio164", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio115", "gpio117", "gpio119", +}; + +static const char *const cci_timer_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio163", "gpio164", +}; + +static const char *const cmu_rng_groups[] = { + "gpio40", "gpio41", "gpio41", "gpio43", "gpio148", "gpio149", + "gpio150", "gpio151", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio148", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio149", +}; + +static const char *const coex_uart2_rx_groups[] = { + "gpio150", +}; + +static const char *const coex_uart2_tx_groups[] = { + "gpio151", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio78", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio44", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio40", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio41", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio45", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio54", "gpio55", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio44", "gpio45", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio43", "gpio52", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio46", "gpio53", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio86", "gpio134", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio87", "gpio135", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio88", "gpio136", +}; + +static const char *const gnss_adc0_groups[] = { + "gpio78", "gpio79", +}; + +static const char *const gnss_adc1_groups[] = { + "gpio77", "gpio99", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio64", "gpio65", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio72", "gpio73", +}; + +static const char *const i2chub0_se5_groups[] = { + "gpio74", "gpio75", +}; + +static const char *const i2chub0_se6_groups[] = { + "gpio76", "gpio77", +}; + +static const char *const i2chub0_se7_groups[] = { + "gpio82", "gpio83", +}; + +static const char *const i2chub0_se8_groups[] = { + "gpio206", "gpio207", +}; + +static const char *const i2chub0_se9_groups[] = { + "gpio80", "gpio81", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio127", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio128", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio126", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio129", +}; + +static const char *const i2s1_data0_groups[] = { + "gpio122", +}; + +static const char *const i2s1_data1_groups[] = { + "gpio124", +}; + +static const char *const i2s1_sck_groups[] = { + "gpio121", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio123", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33", + "gpio36", "gpio37", "gpio48", "gpio49", +}; + +static const char *const jitter_bist_groups[] = { + "gpio73", +}; + +static const char *const mdp_esync0_out_groups[] = { + "gpio88", +}; + +static const char *const mdp_esync1_out_groups[] = { + "gpio100", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", "gpio87", "gpio97", "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio88", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio154", +}; + +static const char *const nav_gpio1_groups[] = { + "gpio155", +}; + +static const char *const nav_gpio2_groups[] = { + "gpio152", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio154", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio103", +}; + +static const char *const phase_flag_groups[] = { + "gpio10", "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27", "gpio28", "gpio29", "gpio31", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio82", "gpio83", "gpio85", + "gpio101", "gpio102", "gpio103", "gpio104", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio95", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio85", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio64", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio65", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio66", +}; + +static const char *const qdss_cti_groups[] = { + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83", "gpio159", + "gpio162", +}; + +static const char *const qlink_big_enable_groups[] = { + "gpio160", +}; + +static const char *const qlink_big_request_groups[] = { + "gpio159", +}; + +static const char *const qlink_little_enable_groups[] = { + "gpio157", +}; + +static const char *const qlink_little_request_groups[] = { + "gpio156", +}; + +static const char *const qlink_wmss_groups[] = { + "gpio158", +}; + +static const char *const qspi0_groups[] = { + "gpio52", +}; + +static const char *const qspi1_groups[] = { + "gpio53", +}; + +static const char *const qspi2_groups[] = { + "gpio55", +}; + +static const char *const qspi3_groups[] = { + "gpio56", +}; + +static const char *const qspi_clk_groups[] = { + "gpio54", +}; + +static const char *const qspi_cs_groups[] = { + "gpio57", "gpio58", +}; + +static const char *const qup1_se0_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se1_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio134", "gpio135", "gpio136", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup2_se3_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup2_se4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup2_se5_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup2_se6_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup2_se7_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio85", +}; + +static const char *const sdc40_groups[] = { + "gpio36", "gpio49", +}; + +static const char *const sdc41_groups[] = { + "gpio37", "gpio51", +}; + +static const char *const sdc42_groups[] = { + "gpio38", "gpio60", +}; + +static const char *const sdc43_groups[] = { + "gpio39", "gpio61", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio50", "gpio150", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio48", "gpio151", +}; + +static const char *const tb_trig_sdc2_groups[] = { + "gpio89", +}; + +static const char *const tb_trig_sdc4_groups[] = { + "gpio147", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio85", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio64", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio65", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio66", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio57", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio57", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio57", +}; + +static const char *const tsense_pwm4_groups[] = { + "gpio57", +}; + +static const char *const uim0_clk_groups[] = { + "gpio131", +}; + +static const char *const uim0_data_groups[] = { + "gpio130", +}; + +static const char *const uim0_present_groups[] = { + "gpio133", +}; + +static const char *const uim0_reset_groups[] = { + "gpio132", +}; + +static const char *const uim1_clk_groups[] = { + "gpio37", "gpio55", "gpio71", "gpio135", +}; + +static const char *const uim1_data_groups[] = { + "gpio134", "gpio36", "gpio54", "gpio70", +}; + +static const char *const uim1_present_groups[] = { + "gpio137", +}; + +static const char *const uim1_reset_groups[] = { + "gpio39", "gpio56", "gpio72", "gpio136", +}; + +static const char *const usb1_hs_groups[] = { + "gpio79", +}; + +static const char *const usb_phy_groups[] = { + "gpio59", "gpio61", +}; + +static const char *const vfr_0_groups[] = { + "gpio150", +}; + +static const char *const vfr_1_groups[] = { + "gpio155", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio59", +}; + +static const char *const wcn_sw_groups[] = { + "gpio19", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio18", +}; + +static const struct pinfunction sm8750_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_aon_mclk2), + MSM_PIN_FUNCTION(cam_aon_mclk4), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(coex_uart2_rx), + MSM_PIN_FUNCTION(coex_uart2_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gnss_adc0), + MSM_PIN_FUNCTION(gnss_adc1), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2chub0_se5), + MSM_PIN_FUNCTION(i2chub0_se6), + MSM_PIN_FUNCTION(i2chub0_se7), + MSM_PIN_FUNCTION(i2chub0_se8), + MSM_PIN_FUNCTION(i2chub0_se9), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_data0), + MSM_PIN_FUNCTION(i2s1_data1), + MSM_PIN_FUNCTION(i2s1_sck), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0_out), + MSM_PIN_FUNCTION(mdp_esync1_out), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink_big_enable), + MSM_PIN_FUNCTION(qlink_big_request), + MSM_PIN_FUNCTION(qlink_little_enable), + MSM_PIN_FUNCTION(qlink_little_request), + MSM_PIN_FUNCTION(qlink_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup2_se7), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8750_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] = PINGROUP(8, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup2_se2, cci_async_in, phase_flag, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup2_se2, cci_async_in, phase_flag, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup2_se3, ibi_i3c, qup2_se2, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup2_se3, ibi_i3c, qup2_se2, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup2_se3, cci_async_in, qup2_se2, phase_flag, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup2_se4, phase_flag, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup2_se4, phase_flag, _, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, wcn_sw_ctrl, qup2_se4, phase_flag, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, wcn_sw, qup2_se4, phase_flag, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup2_se5, phase_flag, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup2_se5, phase_flag, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup2_se5, phase_flag, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup2_se5, qup2_se5, phase_flag, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup2_se6, phase_flag, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup2_se6, phase_flag, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup2_se6, phase_flag, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup2_se6, qdss_cti, phase_flag, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup2_se7, ibi_i3c, phase_flag, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup2_se7, ibi_i3c, phase_flag, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup2_se7, _, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup2_se7, qdss_cti, phase_flag, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [33] = PINGROUP(33, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [34] = PINGROUP(34, qup1_se0, _, _, _, _, _, _, _, _, _, egpio), + [35] = PINGROUP(35, qup1_se0, _, _, _, _, _, _, _, _, _, egpio), + [36] = PINGROUP(36, qup1_se1, uim1_data, ibi_i3c, sdc40, _, _, _, _, _, _, egpio), + [37] = PINGROUP(37, qup1_se1, uim1_clk, ibi_i3c, sdc41, _, _, _, _, _, _, egpio), + [38] = PINGROUP(38, qup1_se1, sdc42, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se1, uim1_reset, sdc43, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, cmu_rng, ddr_bist_fail, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, cmu_rng, ddr_bist_start, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, cmu_rng, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se2, cmu_rng, _, ddr_pxi2, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, ddr_bist_complete, ddr_pxi1, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, ddr_bist_stop, ddr_pxi1, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, ddr_pxi3, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, ibi_i3c, sdc4_cmd, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se4, ibi_i3c, sdc40, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se4, aoss_cti, sdc4_clk, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, qup1_se4, aoss_cti, sdc41, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se5, qspi0, ddr_pxi2, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se5, qspi1, _, ddr_pxi3, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, qspi_clk, uim1_data, ddr_pxi0, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, qspi2, uim1_clk, ddr_pxi0, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se6, qspi3, uim1_reset, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, qspi_cs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, qspi_cs, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se7, aoss_cti, sdc42, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1_se7, usb_phy, aoss_cti, sdc43, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, i2chub0_se0, prng_rosc1, tmess_prng1, phase_flag, _, _, _, _, _, _, _), + [65] = PINGROUP(65, i2chub0_se0, prng_rosc2, tmess_prng2, phase_flag, _, _, _, _, _, _, _), + [66] = PINGROUP(66, i2chub0_se1, prng_rosc3, tmess_prng3, phase_flag, _, _, _, _, _, _, _), + [67] = PINGROUP(67, i2chub0_se1, phase_flag, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, i2chub0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, i2chub0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, i2chub0_se3, uim1_data, _, atest_usb, _, _, _, _, _, _, _), + [71] = PINGROUP(71, i2chub0_se3, uim1_clk, _, atest_usb, _, _, _, _, _, _, _), + [72] = PINGROUP(72, i2chub0_se4, uim1_reset, qdss_cti, _, atest_usb, _, _, _, _, _, _), + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _), + [74] = PINGROUP(74, i2chub0_se5, _, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, i2chub0_se5, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, i2chub0_se6, atest_usb, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, i2chub0_se6, gnss_adc1, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, dbg_out_clk, gnss_adc0, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, usb1_hs, gnss_adc0, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, i2chub0_se9, _, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, i2chub0_se9, _, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write_protect, prng_rosc0, tmess_prng0, phase_flag, _, _, _, _, _, + _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _, _, + _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, gcc_gp2, _, + _, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync_e, mdp_esync0_out, gcc_gp3, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, cam_mclk, tb_trig_sdc2, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cam_aon_mclk2, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_aon_mclk4, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mdp_vsync, _, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, mdp_vsync, _, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, gnss_adc1, _, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_esync1_out, _, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, phase_flag, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, phase_flag, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, pcie0_clk_req_n, phase_flag, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, pll_bist_sync, phase_flag, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _, _, egpio), + [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _, _, egpio), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _, _, egpio), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, egpio), + [109] = PINGROUP(109, cci_timer, _, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_timer, _, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_timer, cci_i2c_sda, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, i2s1_data0, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, i2s0_data0, _, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, i2s0_data1, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, i2s0_ws, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim0_data, atest_char, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim0_clk, atest_char, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim0_present, atest_char, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_data, qup1_se2, gcc_gp1, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_clk, qup1_se2, gcc_gp2, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_reset, qup1_se2, gcc_gp3, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, uim1_present, atest_char, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, tb_trig_sdc4, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, coex_uart1_rx, cmu_rng, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, coex_uart1_tx, cmu_rng, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, vfr_0, coex_uart2_rx, cmu_rng, sdc4_clk, _, _, _, _, _, _), + [151] = PINGROUP(151, _, coex_uart2_tx, cmu_rng, sdc4_cmd, _, _, _, _, _, _, _), + [152] = PINGROUP(152, nav_gpio2, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, nav_gpio1, vfr_1, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink_little_request, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qlink_little_enable, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qlink_wmss, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink_big_request, qdss_cti, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qdss_cti, _, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, cci_timer, _, _, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, cci_timer, cci_i2c_scl, _, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, _, _, _, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, _, _, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, _, _, _, _, _, _, _, _, _, _, egpio), + [211] = PINGROUP(211, _, _, _, _, _, _, _, _, _, _, egpio), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, _, _, _, _, _, _, _, _, _, _, egpio), + [215] = UFS_RESET(ufs_reset, 0xe2004, 0xe3000), + [216] = SDC_QDSD_PINGROUP(sdc2_clk, 0xdb000, 14, 6), + [217] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xdb000, 11, 3), + [218] = SDC_QDSD_PINGROUP(sdc2_data, 0xdb000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8750_pdc_map[] = { + { 0, 72 }, { 3, 80 }, { 4, 73 }, { 7, 74 }, { 8, 75 }, + { 11, 76 }, { 12, 87 }, { 15, 98 }, { 18, 110 }, { 19, 79 }, + { 23, 82 }, { 24, 83 }, { 27, 84 }, { 28, 85 }, { 31, 86 }, + { 32, 92 }, { 35, 68 }, { 36, 93 }, { 39, 94 }, { 43, 95 }, + { 46, 96 }, { 47, 121 }, { 48, 97 }, { 51, 118 }, { 54, 102 }, + { 55, 71 }, { 56, 103 }, { 57, 104 }, { 59, 105 }, { 61, 81 }, + { 63, 91 }, { 64, 77 }, { 65, 90 }, { 66, 106 }, { 67, 99 }, + { 68, 112 }, { 69, 113 }, { 75, 114 }, { 78, 115 }, { 79, 116 }, + { 80, 122 }, { 81, 123 }, { 84, 101 }, { 85, 124 }, { 86, 125 }, + { 87, 126 }, { 88, 127 }, { 95, 128 }, { 96, 129 }, { 97, 100 }, + { 98, 117 }, { 99, 78 }, { 102, 130 }, { 103, 131 }, { 104, 132 }, + { 108, 133 }, { 133, 134 }, { 137, 67 }, { 148, 135 }, { 150, 136 }, + { 152, 137 }, { 154, 138 }, { 155, 89 }, { 156, 139 }, { 159, 140 }, + { 162, 109 }, { 163, 108 }, { 166, 141 }, { 169, 142 }, { 171, 143 }, + { 172, 144 }, { 174, 145 }, { 176, 146 }, { 177, 120 }, { 181, 147 }, + { 182, 148 }, { 185, 149 }, { 188, 111 }, { 190, 88 }, { 191, 150 }, + { 192, 151 }, { 193, 152 }, { 196, 153 }, { 197, 154 }, { 198, 70 }, + { 199, 119 }, { 200, 69 }, { 201, 155 }, { 202, 156 }, { 203, 157 }, + { 204, 158 }, { 205, 107 }, { 209, 159 }, +}; + +static const struct msm_pinctrl_soc_data sm8750_tlmm = { + .pins = sm8750_pins, + .npins = ARRAY_SIZE(sm8750_pins), + .functions = sm8750_functions, + .nfunctions = ARRAY_SIZE(sm8750_functions), + .groups = sm8750_groups, + .ngroups = ARRAY_SIZE(sm8750_groups), + .ngpios = 216, + .wakeirq_map = sm8750_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8750_pdc_map), + .egpio_func = 11, +}; + +static int sm8750_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8750_tlmm); +} + +static const struct of_device_id sm8750_tlmm_of_match[] = { + { .compatible = "qcom,sm8750-tlmm", }, + {}, +}; + +static struct platform_driver sm8750_tlmm_driver = { + .driver = { + .name = "sm8750-tlmm", + .of_match_table = sm8750_tlmm_of_match, + }, + .probe = sm8750_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8750_tlmm_init(void) +{ + return platform_driver_register(&sm8750_tlmm_driver); +} +arch_initcall(sm8750_tlmm_init); + +static void __exit sm8750_tlmm_exit(void) +{ + platform_driver_unregister(&sm8750_tlmm_driver); +} +module_exit(sm8750_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8750 TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index d2dd66769aa8..0c806b8128b6 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -667,7 +667,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, "push-pull", "open-drain", "open-source" }; static const char *const strengths[] = { - "no", "high", "medium", "low" + "no", "low", "medium", "high" }; pad = pctldev->desc->pins[pin].drv_data; @@ -1169,7 +1169,7 @@ static int pmic_gpio_probe(struct platform_device *pdev) * files which don't set the "gpio-ranges" property or systems that * utilize ACPI the driver has to call gpiochip_add_pin_range(). */ - if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { + if (!of_property_present(dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); if (ret) { @@ -1226,6 +1226,8 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 }, { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, + /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */ + { .compatible = "qcom,pm8937-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, @@ -1268,7 +1270,7 @@ static struct platform_driver pmic_gpio_driver = { .of_match_table = pmic_gpio_of_match, }, .probe = pmic_gpio_probe, - .remove_new = pmic_gpio_remove, + .remove = pmic_gpio_remove, }; module_platform_driver(pmic_gpio_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index d16ece90d926..84de584cf7eb 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -983,6 +983,7 @@ static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8937-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 }, { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 }, @@ -1000,7 +1001,7 @@ static struct platform_driver pmic_mpp_driver = { .of_match_table = pmic_mpp_of_match, }, .probe = pmic_mpp_probe, - .remove_new = pmic_mpp_remove, + .remove = pmic_mpp_remove, }; module_platform_driver(pmic_mpp_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 9cd5247ea574..2225dc49d477 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -832,7 +832,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) * files which don't set the "gpio-ranges" property or systems that * utilize ACPI the driver has to call gpiochip_add_pin_range(). */ - if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, pctrl->chip.ngpio); if (ret) { @@ -866,7 +866,7 @@ static struct platform_driver pm8xxx_gpio_driver = { .of_match_table = pm8xxx_gpio_of_match, }, .probe = pm8xxx_gpio_probe, - .remove_new = pm8xxx_gpio_remove, + .remove = pm8xxx_gpio_remove, }; module_platform_driver(pm8xxx_gpio_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 3aee6835a2de..9b1039c08aa6 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -949,7 +949,7 @@ static struct platform_driver pm8xxx_mpp_driver = { .of_match_table = pm8xxx_mpp_of_match, }, .probe = pm8xxx_mpp_probe, - .remove_new = pm8xxx_mpp_remove, + .remove = pm8xxx_mpp_remove, }; module_platform_driver(pm8xxx_mpp_driver); diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index abfcdd3da9e8..419cb8facb2f 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1861,7 +1861,7 @@ static struct platform_driver x1e80100_pinctrl_driver = { .of_match_table = x1e80100_pinctrl_of_match, }, .probe = x1e80100_pinctrl_probe, - .remove_new = msm_pinctrl_remove, + .remove = msm_pinctrl_remove, }; static int __init x1e80100_pinctrl_init(void) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 14bd55d64731..7f3f41c7fe54 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -41,6 +41,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0 select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 + select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 6527872813dc..b1058504e0bb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -19,6 +19,7 @@ #include <linux/ioport.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> @@ -750,6 +751,11 @@ static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) { struct rza1_port *port = gpiochip_get_data(chip); + int ret; + + ret = pinctrl_gpio_request(chip, gpio); + if (ret) + return ret; rza1_pin_reset(port, gpio); @@ -771,6 +777,7 @@ static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) struct rza1_port *port = gpiochip_get_data(chip); rza1_pin_reset(port, gpio); + pinctrl_gpio_free(chip, gpio); } static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index af689d7c117f..dd1f8c29d3e7 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> @@ -229,6 +230,8 @@ static const char * const rza2_gpio_names[] = { static struct gpio_chip chip = { .names = rza2_gpio_names, .base = -1, + .request = pinctrl_gpio_request, + .free = pinctrl_gpio_free, .get_direction = rza2_chip_get_direction, .direction_input = rza2_chip_direction_input, .direction_output = rza2_chip_direction_output, diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 5a403915fed2..8ffb9430a134 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -139,6 +139,8 @@ #define IEN(off) (0x1800 + (off) * 8) #define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) +#define NOD(off) (0x3000 + (off) * 8) +#define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) @@ -160,6 +162,8 @@ #define IOLH_MASK 0x03 #define SR_MASK 0x01 #define PUPD_MASK 0x03 +#define NOD_MASK 0x01 +#define SMT_MASK 0x01 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -168,7 +172,6 @@ #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) #define RZG2L_TINT_MAX_INTERRUPT 32 -#define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) /* Custom pinconf parameters */ @@ -247,6 +250,7 @@ enum rzg2l_iolh_index { * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values * @iolh_groupb_oi: IOLH group B output impedance specific values + * @tint_start_index: the start index for the TINT interrupts * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable @@ -258,6 +262,7 @@ struct rzg2l_hwcfg { u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_oi[4]; + u16 tint_start_index; bool drive_strength_ua; u8 func_base; u8 oen_max_pin; @@ -1337,6 +1342,27 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(cfg & PIN_CFG_NOD)) + return -EINVAL; + + arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); + if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) + return -EINVAL; + if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) + return -EINVAL; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); + if (!arg) + return -EINVAL; + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -1466,6 +1492,22 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(cfg & PIN_CFG_NOD)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, + param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -2379,7 +2421,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] = child; - irq += RZG2L_TINT_IRQ_START_INDEX; + irq += pctrl->data->hwcfg->tint_start_index; /* All these interrupts are level high in the CPU */ *parent_type = IRQ_TYPE_LEVEL_HIGH; @@ -2391,21 +2433,6 @@ err: return ret; } -static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, - union gpio_irq_fwspec *gfwspec, - unsigned int parent_hwirq, - unsigned int parent_type) -{ - struct irq_fwspec *fwspec = &gfwspec->fwspec; - - fwspec->fwnode = chip->irq.parent_domain->fwnode; - fwspec->param_count = 2; - fwspec->param[0] = parent_hwirq; - fwspec->param[1] = parent_type; - - return 0; -} - static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) { struct irq_domain *domain = pctrl->gpio_chip.irq.domain; @@ -2607,7 +2634,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) girq->fwnode = dev_fwnode(pctrl->dev); girq->parent_domain = parent_domain; girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; - girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; girq->init_valid_mask = rzg2l_init_irq_valid_mask; @@ -2710,7 +2737,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) ret = pinctrl_enable(pctrl->pctl); if (ret) - dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); + return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); ret = rzg2l_gpio_register(pctrl); if (ret) @@ -3034,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, }, .iolh_groupb_oi = { 100, 66, 50, 33, }, + .tint_start_index = 9, .oen_max_pin = 0, }; @@ -3063,6 +3091,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { /* 3v3 power source */ [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, }, + .tint_start_index = 9, .drive_strength_ua = true, .func_base = 1, .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ @@ -3073,6 +3102,7 @@ static const struct rzg2l_hwcfg rzv2h_hwcfg = { .regs = { .pwpr = 0x3c04, }, + .tint_start_index = 17, }; static struct rzg2l_pinctrl_data r9a07g043_data = { diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c index 39af1fe79c84..d442d4f9981c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzn1.c +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c @@ -925,7 +925,7 @@ MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match); static struct platform_driver rzn1_pinctrl_driver = { .probe = rzn1_pinctrl_probe, - .remove_new = rzn1_pinctrl_remove, + .remove = rzn1_pinctrl_remove, .driver = { .name = "rzn1-pinctrl", .of_match_table = rzn1_pinctrl_match, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 5480e0884abe..3ea7106ce5ea 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -58,6 +58,15 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 + */ +static const struct samsung_pin_bank_type exynos8895_bank_type_off = { + .fld_width = { 4, 1, 2, 3, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -618,6 +627,300 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), }; +/* pin banks of exynos990 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos990_pin_banks0[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos990 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos990_pin_banks1[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), + EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), + EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), + EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), + EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), + EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), + EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), + EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), + EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), + +}; + +/* pin banks of exynos990 pin-controller 2 (HSI1) */ +static struct samsung_pin_bank_data exynos990_pin_banks2[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos990 pin-controller 3 (HSI2) */ +static struct samsung_pin_bank_data exynos990_pin_banks3[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), +}; + +/* pin banks of exynos990 pin-controller 4 (PERIC0) */ +static struct samsung_pin_bank_data exynos990_pin_banks4[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), + EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), +}; + +/* pin banks of exynos990 pin-controller 5 (PERIC1) */ +static struct samsung_pin_bank_data exynos990_pin_banks5[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), + EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), + EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), +}; + +/* pin banks of exynos990 pin-controller 6 (VTS) */ +static struct samsung_pin_bank_data exynos990_pin_banks6[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos990_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos990_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 HSI1 data */ + .pin_banks = exynos990_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 HSI2 data */ + .pin_banks = exynos990_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 PERIC0 data */ + .pin_banks = exynos990_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERIC1 data */ + .pin_banks = exynos990_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 6 VTS data */ + .pin_banks = exynos990_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { + .ctrl = exynos990_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), +}; + +/* pin banks of exynos9810 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), + EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), +}; + +/* pin banks of exynos9810 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9810 pin-controller 2 (CHUB) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 3 (CMGP) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), +}; + +/* pin banks of exynos9810 pin-controller 4 (FSYS0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos9810 pin-controller 5 (FSYS1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 8 (VTS) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos9810_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynos9810_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), + }, { + /* pin-controller instance 2 CHUB data */ + .pin_banks = exynos9810_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 CMGP data */ + .pin_banks = exynos9810_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), + .eint_wkup_init = exynos_eint_wkup_init, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS0 data */ + .pin_banks = exynos9810_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 FSYS1 data */ + .pin_banks = exynos9810_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynos9810_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynos9810_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 8 VTS data */ + .pin_banks = exynos9810_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { + .ctrl = exynos9810_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), +}; + /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), @@ -866,6 +1169,134 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), }; +/* pin banks of exynos8895 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), + EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), +}; + +/* pin banks of exynos8895 pin-controller 1 (ABOX) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), +}; + +/* pin banks of exynos8895 pin-controller 2 (VTS) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), +}; + +/* pin banks of exynos8895 pin-controller 3 (FSYS0) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), +}; + +/* pin banks of exynos8895 pin-controller 4 (FSYS1) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), +}; + +/* pin banks of exynos8895 pin-controller 5 (BUSC) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { + EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), +}; + +/* pin banks of exynos8895 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), +}; + +/* pin banks of exynos8895 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), +}; + +static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos8895_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 ABOX data */ + .pin_banks = exynos8895_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), + }, { + /* pin-controller instance 2 VTS data */ + .pin_banks = exynos8895_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 FSYS0 data */ + .pin_banks = exynos8895_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS1 data */ + .pin_banks = exynos8895_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 BUSC data */ + .pin_banks = exynos8895_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynos8895_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynos8895_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { + .ctrl = exynos8895_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 305cb1d31de4..7b7ff7ffeb56 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -141,6 +141,16 @@ .name = id \ } +#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos8895_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ { \ .type = &exynos850_bank_type_off, \ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 675efa5d86a9..bbedd980ec67 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1477,6 +1477,12 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, + { .compatible = "samsung,exynos8895-pinctrl", + .data = &exynos8895_of_data }, + { .compatible = "samsung,exynos9810-pinctrl", + .data = &exynos9810_of_data }, + { .compatible = "samsung,exynos990-pinctrl", + .data = &exynos990_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, { .compatible = "samsung,exynosautov920-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index a1e7377bd890..bb0689d52ea0 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -384,6 +384,9 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; +extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; diff --git a/drivers/pinctrl/sophgo/Kconfig b/drivers/pinctrl/sophgo/Kconfig index b14792ee46fc..c05f909a8838 100644 --- a/drivers/pinctrl/sophgo/Kconfig +++ b/drivers/pinctrl/sophgo/Kconfig @@ -43,7 +43,7 @@ config PINCTRL_SOPHGO_SG2000 pinctrl-sg2000. config PINCTRL_SOPHGO_SG2002 - tristate "Sophgo SG2000 SoC Pinctrl driver" + tristate "Sophgo SG2002 SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF select PINCTRL_SOPHGO_CV18XX diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig new file mode 100644 index 000000000000..168f8a5ffbb9 --- /dev/null +++ b/drivers/pinctrl/spacemit/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Sophgo SoC PINCTRL drivers +# + +config PINCTRL_SPACEMIT_K1 + tristate "SpacemiT K1 SoC Pinctrl driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + Say Y to select the pinctrl driver for K1 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-k1. diff --git a/drivers/pinctrl/spacemit/Makefile b/drivers/pinctrl/spacemit/Makefile new file mode 100644 index 000000000000..fede1e80fe0f --- /dev/null +++ b/drivers/pinctrl/spacemit/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PINCTRL_SPACEMIT_K1) += pinctrl-k1.o diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c new file mode 100644 index 000000000000..a32579d73613 --- /dev/null +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -0,0 +1,1051 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ + +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> +#include <linux/module.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "../pinconf.h" +#include "../pinmux.h" +#include "pinctrl-k1.h" + +/* + * +---------+----------+-----------+--------+--------+----------+--------+ + * | pull | drive | schmitter | slew | edge | strong | mux | + * | up/down | strength | trigger | rate | detect | pull | mode | + * +---------+----------+-----------+--------+--------+----------+--------+ + * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits + */ + +#define PAD_MUX GENMASK(2, 0) +#define PAD_STRONG_PULL BIT(3) +#define PAD_EDGE_RISE BIT(4) +#define PAD_EDGE_FALL BIT(5) +#define PAD_EDGE_CLEAR BIT(6) +#define PAD_SLEW_RATE GENMASK(12, 11) +#define PAD_SLEW_RATE_EN BIT(7) +#define PAD_SCHMITT GENMASK(9, 8) +#define PAD_DRIVE GENMASK(12, 10) +#define PAD_PULLDOWN BIT(13) +#define PAD_PULLUP BIT(14) +#define PAD_PULL_EN BIT(15) + +struct spacemit_pin { + u16 pin; + u16 flags; + u8 gpiofunc; +}; + +struct spacemit_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + const struct spacemit_pinctrl_data *data; + struct pinctrl_desc pdesc; + + struct mutex mutex; + raw_spinlock_t lock; + + void __iomem *regs; +}; + +struct spacemit_pinctrl_data { + const struct pinctrl_pin_desc *pins; + const struct spacemit_pin *data; + u16 npins; +}; + +struct spacemit_pin_mux_config { + const struct spacemit_pin *pin; + u32 config; +}; + +struct spacemit_pin_drv_strength { + u8 val; + u32 mA; +}; + +/* map pin id to pinctrl register offset, refer MFPR definition */ +static unsigned int spacemit_pin_to_offset(unsigned int pin) +{ + unsigned int offset = 0; + + switch (pin) { + case 0 ... 85: + offset = pin + 1; + break; + case 86 ... 92: + offset = pin + 37; + break; + case 93 ... 97: + offset = pin + 24; + break; + case 98: + offset = 93; + break; + case 99: + offset = 92; + break; + case 100: + offset = 91; + break; + case 101: + offset = 90; + break; + case 102: + offset = 95; + break; + case 103: + offset = 94; + break; + case 104 ... 110: + offset = pin + 6; + break; + case 111 ... 127: + offset = pin + 20; + break; + default: + break; + } + + return offset << 2; +} + +static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, + unsigned int pin) +{ + return pctrl->regs + spacemit_pin_to_offset(pin); +} + +static u16 spacemit_dt_get_pin(u32 value) +{ + return value >> 16; +} + +static u16 spacemit_dt_get_pin_mux(u32 value) +{ + return value & GENMASK(15, 0); +} + +static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl, + unsigned long pin) +{ + const struct spacemit_pin *pdata = pctrl->data->data; + int i; + + for (i = 0; i < pctrl->data->npins; i++) { + if (pin == pdata[i].pin) + return &pdata[i]; + } + + return NULL; +} + +static inline enum spacemit_pin_io_type spacemit_to_pin_io_type( + const struct spacemit_pin *pin) +{ + return K1_PIN_GET_IO_TYPE(pin->flags); +} + +/* External: IO voltage via external source, can be 1.8V or 3.3V */ +static const char * const io_type_desc[] = { + "None", + "Fixed/1V8", + "Fixed/3V3", + "External", +}; + +static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); + void __iomem *reg; + u32 value; + + seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); + seq_printf(seq, "type: %s ", io_type_desc[type]); + + reg = spacemit_pin_to_reg(pctrl, pin); + value = readl(reg); + seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); +} + +/* use IO high level output current as the table */ +static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { + { 0, 11 }, + { 2, 21 }, + { 4, 32 }, + { 6, 42 }, +}; + +static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { + { 0, 7 }, + { 2, 10 }, + { 4, 13 }, + { 6, 16 }, + { 1, 19 }, + { 3, 23 }, + { 5, 26 }, + { 7, 29 }, +}; + +static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, + u32 num, u32 mA) +{ + int i; + + for (i = 0; i < num; i++) + if (mA <= tbl[i].mA) + return tbl[i].val; + + return tbl[num - 1].val; +} + +static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, + u32 num, u32 val) +{ + int i; + + for (i = 0; i < num; i++) + if (val == tbl[i].val) + return tbl[i].mA; + + return 0; +} + +static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, + u32 mA) +{ + switch (type) { + case IO_TYPE_1V8: + return spacemit_get_ds_value(spacemit_ds_1v8_tbl, + ARRAY_SIZE(spacemit_ds_1v8_tbl), + mA); + case IO_TYPE_3V3: + return spacemit_get_ds_value(spacemit_ds_3v3_tbl, + ARRAY_SIZE(spacemit_ds_3v3_tbl), + mA); + default: + return 0; + } +} + +static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, + u32 value) +{ + switch (type) { + case IO_TYPE_1V8: + return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, + ARRAY_SIZE(spacemit_ds_1v8_tbl), + value & 0x6); + case IO_TYPE_3V3: + return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, + ARRAY_SIZE(spacemit_ds_3v3_tbl), + value); + default: + return 0; + } +} + +static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, + struct device_node *dn, + struct spacemit_pin_mux_config *pinmuxs, + int num_pins, const char *grpname) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; + enum spacemit_pin_io_type type; + u32 power = 0, i; + + of_property_read_u32(dn, "power-source", &power); + + for (i = 0; i < num_pins; i++) { + type = spacemit_to_pin_io_type(pinmuxs[i].pin); + + if (type != IO_TYPE_EXTERNAL) + continue; + + switch (power) { + case PIN_POWER_STATE_1V8: + case PIN_POWER_STATE_3V3: + break; + default: + dev_err(dev, "group %s has unsupported power\n", + grpname); + return -ENOTSUPP; + } + } + + return 0; +} + +static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; + struct device_node *child; + struct pinctrl_map *map; + const char **grpnames; + const char *grpname; + int ngroups = 0; + int nmaps = 0; + int ret; + + for_each_available_child_of_node(np, child) + ngroups += 1; + + grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); + if (!grpnames) + return -ENOMEM; + + map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + ngroups = 0; + guard(mutex)(&pctrl->mutex); + for_each_available_child_of_node_scoped(np, child) { + struct spacemit_pin_mux_config *pinmuxs; + unsigned int config, *pins; + int i, npins; + + npins = of_property_count_u32_elems(child, "pinmux"); + + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", + np, child); + return -EINVAL; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!grpname) + return -ENOMEM; + + grpnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) + return -ENOMEM; + + for (i = 0; i < npins; i++) { + ret = of_property_read_u32_index(child, "pinmux", + i, &config); + + if (ret) + return -EINVAL; + + pins[i] = spacemit_dt_get_pin(config); + pinmuxs[i].config = config; + pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]); + + if (!pinmuxs[i].pin) + return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]); + } + + ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs, + npins, grpname); + if (ret < 0) + return ret; + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmuxs); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret); + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) + return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", + grpname); + + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + grpnames, ngroups, NULL); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, map, nmaps); + return dev_err_probe(dev, ret, "error adding function %s\n", np->name); + } + + *maps = map; + *num_maps = nmaps; + + return 0; +} + +static const struct pinctrl_ops spacemit_pctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = spacemit_pctrl_dbg_show, + .dt_node_to_map = spacemit_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const struct spacemit_pin_mux_config *configs; + unsigned int i, mux; + void __iomem *reg; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + configs = group->data; + + for (i = 0; i < group->grp.npins; i++) { + const struct spacemit_pin *spin = configs[i].pin; + u32 value = configs[i].config; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); + mux = spacemit_dt_get_pin_mux(value); + + guard(raw_spinlock_irqsave)(&pctrl->lock); + value = readl_relaxed(reg) & ~PAD_MUX; + writel_relaxed(mux | value, reg); + } + + return 0; +} + +static int spacemit_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + void __iomem *reg; + + reg = spacemit_pin_to_reg(pctrl, pin); + guard(raw_spinlock_irqsave)(&pctrl->lock); + writel_relaxed(spin->gpiofunc, reg); + + return 0; +} + +static const struct pinmux_ops spacemit_pmx_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = spacemit_pmx_set_mux, + .gpio_request_enable = spacemit_request_gpio, + .strict = true, +}; + +static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + u32 value, arg = 0; + + if (!pin) + return -EINVAL; + + value = readl(spacemit_pin_to_reg(pctrl, pin)); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + if (FIELD_GET(PAD_SLEW_RATE_EN, value)) + arg = FIELD_GET(PAD_SLEW_RATE, value) + 2; + else + arg = 0; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +#define ENABLE_DRV_STRENGTH BIT(1) +#define ENABLE_SLEW_RATE BIT(2) +static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + unsigned long *configs, + unsigned int num_configs, + u32 *value) +{ + enum spacemit_pin_io_type type; + int i, param; + u32 v = 0, voltage = 0, arg, val; + u32 flag = 0, drv_strength, slew_rate; + + if (!spin) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP); + v &= ~PAD_STRONG_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + v &= ~(PAD_PULLUP | PAD_STRONG_PULL); + v |= (PAD_PULL_EN | PAD_PULLDOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + v &= ~PAD_PULLDOWN; + v |= (PAD_PULL_EN | PAD_PULLUP); + + if (arg == 1) + v |= PAD_STRONG_PULL; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + flag |= ENABLE_DRV_STRENGTH; + drv_strength = arg; + break; + case PIN_CONFIG_INPUT_SCHMITT: + v &= ~PAD_SCHMITT; + v |= FIELD_PREP(PAD_SCHMITT, arg); + break; + case PIN_CONFIG_POWER_SOURCE: + voltage = arg; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) { + flag |= ENABLE_SLEW_RATE; + v |= PAD_SLEW_RATE_EN; + slew_rate = arg; + } else { + v &= ~PAD_SLEW_RATE_EN; + } + break; + default: + return -EINVAL; + } + } + + if (flag & ENABLE_DRV_STRENGTH) { + type = spacemit_to_pin_io_type(spin); + + /* fix external io type */ + if (type == IO_TYPE_EXTERNAL) { + switch (voltage) { + case 1800: + type = IO_TYPE_1V8; + break; + case 3300: + type = IO_TYPE_3V3; + break; + default: + return -EINVAL; + } + } + + val = spacemit_get_driver_strength(type, drv_strength); + + v &= ~PAD_DRIVE; + v |= FIELD_PREP(PAD_DRIVE, val); + } + + if (flag & ENABLE_SLEW_RATE) { + /* check, driver strength & slew rate */ + if (flag & ENABLE_DRV_STRENGTH) { + val = FIELD_GET(PAD_SLEW_RATE, v) + 2; + if (slew_rate > 1 && slew_rate != val) { + pr_err("slew rate conflict with drive strength\n"); + return -EINVAL; + } + } else { + v &= ~PAD_SLEW_RATE; + slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0; + v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate); + } + } + + *value = v; + + return 0; +} + +static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, + unsigned int pin, u32 value) +{ + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + void __iomem *reg; + unsigned int mux; + + if (!pin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); + + guard(raw_spinlock_irqsave)(&pctrl->lock); + mux = readl_relaxed(reg) & PAD_MUX; + writel_relaxed(mux | value, reg); + + return 0; +} + +static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; + + if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) + return -EINVAL; + + return spacemit_pin_set_config(pctrl, pin, value); +} + +static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin; + const struct group_desc *group; + u32 value; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); + if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) + return -EINVAL; + + for (i = 0; i < group->grp.npins; i++) + spacemit_pin_set_config(pctrl, group->grp.pins[i], value); + + return 0; +} + +static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value) +{ + u32 normal, strong; + + if (!FIELD_GET(PAD_PULL_EN, value)) { + seq_puts(seq, ", bias pull disabled"); + return; + } + + if (FIELD_GET(PAD_PULLDOWN, value)) + seq_puts(seq, ", bias pull down"); + + normal = FIELD_GET(PAD_PULLUP, value); + strong = FIELD_GET(PAD_STRONG_PULL, value); + + if (normal && strong) + seq_puts(seq, ", bias strong pull up"); + else if (normal) + seq_puts(seq, ", bias normal pull up"); +} + +static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin) +{ + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); + void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); + u32 value, tmp, mA; + + value = readl(reg); + spacemit_pinconf_dbg_pull(seq, value); + + seq_printf(seq, ", io type (%s)", io_type_desc[type]); + + tmp = FIELD_GET(PAD_DRIVE, value); + if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { + mA = spacemit_get_drive_strength_mA(type, tmp); + seq_printf(seq, ", drive strength (%d mA)", mA); + } + + /* drive strength depend on power source, so show all values */ + if (type == IO_TYPE_EXTERNAL) + seq_printf(seq, ", drive strength (%d or %d mA)", + spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), + spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); + + seq_printf(seq, ", register (0x%04x)\n", value); +} + +static const struct pinconf_ops spacemit_pinconf_ops = { + .pin_config_get = spacemit_pinconf_get, + .pin_config_set = spacemit_pinconf_set, + .pin_config_group_set = spacemit_pinconf_group_set, + .pin_config_dbg_show = spacemit_pinconf_dbg_show, + .is_generic = true, +}; + +static int spacemit_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spacemit_pinctrl *pctrl; + const struct spacemit_pinctrl_data *pctrl_data; + int ret; + + pctrl_data = device_get_match_data(dev); + if (!pctrl_data) + return -ENODEV; + + if (pctrl_data->npins == 0) + return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + + pctrl->pdesc.name = dev_name(dev); + pctrl->pdesc.pins = pctrl_data->pins; + pctrl->pdesc.npins = pctrl_data->npins; + pctrl->pdesc.pctlops = &spacemit_pctrl_ops; + pctrl->pdesc.pmxops = &spacemit_pmx_ops; + pctrl->pdesc.confops = &spacemit_pinconf_ops; + pctrl->pdesc.owner = THIS_MODULE; + + pctrl->data = pctrl_data; + pctrl->dev = dev; + raw_spin_lock_init(&pctrl->lock); + mutex_init(&pctrl->mutex); + + platform_set_drvdata(pdev, pctrl); + + ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, + pctrl, &pctrl->pctl_dev); + if (ret) + return dev_err_probe(dev, ret, + "fail to register pinctrl driver\n"); + + return pinctrl_enable(pctrl->pctl_dev); +} + +static const struct pinctrl_pin_desc k1_pin_desc[] = { + PINCTRL_PIN(0, "GPIO_00"), + PINCTRL_PIN(1, "GPIO_01"), + PINCTRL_PIN(2, "GPIO_02"), + PINCTRL_PIN(3, "GPIO_03"), + PINCTRL_PIN(4, "GPIO_04"), + PINCTRL_PIN(5, "GPIO_05"), + PINCTRL_PIN(6, "GPIO_06"), + PINCTRL_PIN(7, "GPIO_07"), + PINCTRL_PIN(8, "GPIO_08"), + PINCTRL_PIN(9, "GPIO_09"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70/PRI_DTI"), + PINCTRL_PIN(71, "GPIO_71/PRI_TMS"), + PINCTRL_PIN(72, "GPIO_72/PRI_TCK"), + PINCTRL_PIN(73, "GPIO_73/PRI_TDO"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93/PWR_SCL"), + PINCTRL_PIN(94, "GPIO_94/PWR_SDA"), + PINCTRL_PIN(95, "GPIO_95/VCX0_EN"), + PINCTRL_PIN(96, "GPIO_96/DVL0"), + PINCTRL_PIN(97, "GPIO_97/DVL1"), + PINCTRL_PIN(98, "GPIO_98/QSPI_DAT3"), + PINCTRL_PIN(99, "GPIO_99/QSPI_DAT2"), + PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"), + PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"), + PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"), + PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"), + PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"), + PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"), + PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"), + PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"), + PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"), + PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), +}; + +static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = { + K1_FUNC_PIN(0, 0, IO_TYPE_1V8), + K1_FUNC_PIN(1, 0, IO_TYPE_1V8), + K1_FUNC_PIN(2, 0, IO_TYPE_1V8), + K1_FUNC_PIN(3, 0, IO_TYPE_1V8), + K1_FUNC_PIN(4, 0, IO_TYPE_1V8), + K1_FUNC_PIN(5, 0, IO_TYPE_1V8), + K1_FUNC_PIN(6, 0, IO_TYPE_1V8), + K1_FUNC_PIN(7, 0, IO_TYPE_1V8), + K1_FUNC_PIN(8, 0, IO_TYPE_1V8), + K1_FUNC_PIN(9, 0, IO_TYPE_1V8), + K1_FUNC_PIN(10, 0, IO_TYPE_1V8), + K1_FUNC_PIN(11, 0, IO_TYPE_1V8), + K1_FUNC_PIN(12, 0, IO_TYPE_1V8), + K1_FUNC_PIN(13, 0, IO_TYPE_1V8), + K1_FUNC_PIN(14, 0, IO_TYPE_1V8), + K1_FUNC_PIN(15, 0, IO_TYPE_1V8), + K1_FUNC_PIN(16, 0, IO_TYPE_1V8), + K1_FUNC_PIN(17, 0, IO_TYPE_1V8), + K1_FUNC_PIN(18, 0, IO_TYPE_1V8), + K1_FUNC_PIN(19, 0, IO_TYPE_1V8), + K1_FUNC_PIN(20, 0, IO_TYPE_1V8), + K1_FUNC_PIN(21, 0, IO_TYPE_1V8), + K1_FUNC_PIN(22, 0, IO_TYPE_1V8), + K1_FUNC_PIN(23, 0, IO_TYPE_1V8), + K1_FUNC_PIN(24, 0, IO_TYPE_1V8), + K1_FUNC_PIN(25, 0, IO_TYPE_1V8), + K1_FUNC_PIN(26, 0, IO_TYPE_1V8), + K1_FUNC_PIN(27, 0, IO_TYPE_1V8), + K1_FUNC_PIN(28, 0, IO_TYPE_1V8), + K1_FUNC_PIN(29, 0, IO_TYPE_1V8), + K1_FUNC_PIN(30, 0, IO_TYPE_1V8), + K1_FUNC_PIN(31, 0, IO_TYPE_1V8), + K1_FUNC_PIN(32, 0, IO_TYPE_1V8), + K1_FUNC_PIN(33, 0, IO_TYPE_1V8), + K1_FUNC_PIN(34, 0, IO_TYPE_1V8), + K1_FUNC_PIN(35, 0, IO_TYPE_1V8), + K1_FUNC_PIN(36, 0, IO_TYPE_1V8), + K1_FUNC_PIN(37, 0, IO_TYPE_1V8), + K1_FUNC_PIN(38, 0, IO_TYPE_1V8), + K1_FUNC_PIN(39, 0, IO_TYPE_1V8), + K1_FUNC_PIN(40, 0, IO_TYPE_1V8), + K1_FUNC_PIN(41, 0, IO_TYPE_1V8), + K1_FUNC_PIN(42, 0, IO_TYPE_1V8), + K1_FUNC_PIN(43, 0, IO_TYPE_1V8), + K1_FUNC_PIN(44, 0, IO_TYPE_1V8), + K1_FUNC_PIN(45, 0, IO_TYPE_1V8), + K1_FUNC_PIN(46, 0, IO_TYPE_1V8), + K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(53, 0, IO_TYPE_1V8), + K1_FUNC_PIN(54, 0, IO_TYPE_1V8), + K1_FUNC_PIN(55, 0, IO_TYPE_1V8), + K1_FUNC_PIN(56, 0, IO_TYPE_1V8), + K1_FUNC_PIN(57, 0, IO_TYPE_1V8), + K1_FUNC_PIN(58, 0, IO_TYPE_1V8), + K1_FUNC_PIN(59, 0, IO_TYPE_1V8), + K1_FUNC_PIN(60, 0, IO_TYPE_1V8), + K1_FUNC_PIN(61, 0, IO_TYPE_1V8), + K1_FUNC_PIN(62, 0, IO_TYPE_1V8), + K1_FUNC_PIN(63, 0, IO_TYPE_1V8), + K1_FUNC_PIN(64, 0, IO_TYPE_1V8), + K1_FUNC_PIN(65, 0, IO_TYPE_1V8), + K1_FUNC_PIN(66, 0, IO_TYPE_1V8), + K1_FUNC_PIN(67, 0, IO_TYPE_1V8), + K1_FUNC_PIN(68, 0, IO_TYPE_1V8), + K1_FUNC_PIN(69, 0, IO_TYPE_1V8), + K1_FUNC_PIN(70, 1, IO_TYPE_1V8), + K1_FUNC_PIN(71, 1, IO_TYPE_1V8), + K1_FUNC_PIN(72, 1, IO_TYPE_1V8), + K1_FUNC_PIN(73, 1, IO_TYPE_1V8), + K1_FUNC_PIN(74, 0, IO_TYPE_1V8), + K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(81, 0, IO_TYPE_1V8), + K1_FUNC_PIN(82, 0, IO_TYPE_1V8), + K1_FUNC_PIN(83, 0, IO_TYPE_1V8), + K1_FUNC_PIN(84, 0, IO_TYPE_1V8), + K1_FUNC_PIN(85, 0, IO_TYPE_1V8), + K1_FUNC_PIN(86, 0, IO_TYPE_1V8), + K1_FUNC_PIN(87, 0, IO_TYPE_1V8), + K1_FUNC_PIN(88, 0, IO_TYPE_1V8), + K1_FUNC_PIN(89, 0, IO_TYPE_1V8), + K1_FUNC_PIN(90, 0, IO_TYPE_1V8), + K1_FUNC_PIN(91, 0, IO_TYPE_1V8), + K1_FUNC_PIN(92, 0, IO_TYPE_1V8), + K1_FUNC_PIN(93, 1, IO_TYPE_1V8), + K1_FUNC_PIN(94, 1, IO_TYPE_1V8), + K1_FUNC_PIN(95, 1, IO_TYPE_1V8), + K1_FUNC_PIN(96, 1, IO_TYPE_1V8), + K1_FUNC_PIN(97, 1, IO_TYPE_1V8), + K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(110, 0, IO_TYPE_1V8), + K1_FUNC_PIN(111, 0, IO_TYPE_1V8), + K1_FUNC_PIN(112, 0, IO_TYPE_1V8), + K1_FUNC_PIN(113, 0, IO_TYPE_1V8), + K1_FUNC_PIN(114, 0, IO_TYPE_1V8), + K1_FUNC_PIN(115, 0, IO_TYPE_1V8), + K1_FUNC_PIN(116, 0, IO_TYPE_1V8), + K1_FUNC_PIN(117, 0, IO_TYPE_1V8), + K1_FUNC_PIN(118, 0, IO_TYPE_1V8), + K1_FUNC_PIN(119, 0, IO_TYPE_1V8), + K1_FUNC_PIN(120, 0, IO_TYPE_1V8), + K1_FUNC_PIN(121, 0, IO_TYPE_1V8), + K1_FUNC_PIN(122, 0, IO_TYPE_1V8), + K1_FUNC_PIN(123, 0, IO_TYPE_1V8), + K1_FUNC_PIN(124, 0, IO_TYPE_1V8), + K1_FUNC_PIN(125, 0, IO_TYPE_1V8), + K1_FUNC_PIN(126, 0, IO_TYPE_1V8), + K1_FUNC_PIN(127, 0, IO_TYPE_1V8), +}; + +static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .pins = k1_pin_desc, + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), +}; + +static const struct of_device_id k1_pinctrl_ids[] = { + { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); + +static struct platform_driver k1_pinctrl_driver = { + .probe = spacemit_pinctrl_probe, + .driver = { + .name = "k1-pinctrl", + .suppress_bind_attrs = true, + .of_match_table = k1_pinctrl_ids, + }, +}; +module_platform_driver(k1_pinctrl_driver); + +MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>"); +MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.h b/drivers/pinctrl/spacemit/pinctrl-k1.h new file mode 100644 index 000000000000..16143fea469e --- /dev/null +++ b/drivers/pinctrl/spacemit/pinctrl-k1.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ + +#ifndef _PINCTRL_SPACEMIT_K1_H +#define _PINCTRL_SPACEMIT_K1_H + +#include <linux/bits.h> +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> + +enum spacemit_pin_io_type { + IO_TYPE_NONE = 0, + IO_TYPE_1V8, + IO_TYPE_3V3, + IO_TYPE_EXTERNAL, +}; + +#define PIN_POWER_STATE_1V8 1800 +#define PIN_POWER_STATE_3V3 3300 + +#define K1_PIN_IO_TYPE GENMASK(2, 1) + +#define K1_PIN_CAP_IO_TYPE(type) \ + FIELD_PREP_CONST(K1_PIN_IO_TYPE, type) +#define K1_PIN_GET_IO_TYPE(val) \ + FIELD_GET(K1_PIN_IO_TYPE, val) + +#define K1_FUNC_PIN(_id, _gpiofunc, _io) \ + { \ + .pin = (_id), \ + .gpiofunc = (_gpiofunc), \ + .flags = (K1_PIN_CAP_IO_TYPE(_io)), \ + } + +#endif /* _PINCTRL_SPACEMIT_K1_H */ diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c index 9c3c39dc6550..d14f382f2392 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -943,7 +943,7 @@ static struct platform_driver sprd_pinctrl_driver = { .of_match_table = sprd_pinctrl_of_match, }, .probe = sprd_pinctrl_probe, - .remove_new = sprd_pinctrl_remove, + .remove = sprd_pinctrl_remove, .shutdown = sprd_pinctrl_shutdown, }; module_platform_driver(sprd_pinctrl_driver); diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 76d85ad82ec0..6d4dbc196b93 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -263,6 +263,7 @@ enum pm_query_id { PM_QID_PINCTRL_GET_PIN_GROUPS = 11, PM_QID_CLOCK_GET_NUM_CLOCKS = 12, PM_QID_CLOCK_GET_MAX_DIVISOR = 13, + PM_QID_PINCTRL_GET_ATTRIBUTES = 15, }; enum rpu_oper_mode { |