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authorArnd Bergmann <arnd@arndb.de>2026-04-20 17:03:06 +0200
committerArnd Bergmann <arnd@arndb.de>2026-04-20 17:03:16 +0200
commitde65fe9160d27166045291b9cdf7bffdb7d1c815 (patch)
tree392a0a6ad20c215c04c5216c52d7890255d08d1f
parent7b82df336809eff5a2fdea1452c37cc45b448ec5 (diff)
parent00e6d608fe80b0f68c325cb46862f78e9a8ec768 (diff)
downloadlwn-de65fe9160d27166045291b9cdf7bffdb7d1c815.tar.gz
lwn-de65fe9160d27166045291b9cdf7bffdb7d1c815.zip
Merge tag 'mvebu-dt64-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/late2
mvebu dt64 for 7.1 (part 1) - Armada 37xx/3720 device tree fixes: - Reorder USB PHYs, standardize names, drop undocumented properties, fix schema alignment - Add Marvell 7k COMe board bindings and uDPU ethernet aliases - Cleanup: drop unused .dtsi files * tag 'mvebu-dt64-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names arm64: dts: marvell: armada-37xx: drop 'marvell,usb-misc-reg' from USB host nodes arm64: dts: marvell: armada-37xx: drop redundant status property arm64: dts: marvell: armada-37xx: align 'phy-names' of EHCI node with DT schema dt-bindings: arm64: add Marvell 7k COMe boards arm64: dts: marvell: armada-3720: drop 'marvell,xenon-emmc' properties arm64: dts: marvell: uDPU: add ethernet aliases arm/arm64: dts: marvell: Drop unused .dtsi arm64: dts: a7k: use phy handle Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/boot/dts/marvell/armada-380.dtsi148
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi7
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi9
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8020.dtsi20
-rw-r--r--arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi96
8 files changed, 10 insertions, 274 deletions
diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi
deleted file mode 100644
index e94f22b0e9b5..000000000000
--- a/arch/arm/boot/dts/marvell/armada-380.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for Marvell Armada 380 SoC.
- *
- * Copyright (C) 2014 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- */
-
-#include "armada-38x.dtsi"
-
-/ {
- model = "Marvell Armada 380 family SoC";
- compatible = "marvell,armada380";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "marvell,armada-380-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
- };
-
- soc {
- internal-regs {
- pinctrl@18000 {
- compatible = "marvell,mv88f6810-pinctrl";
- };
- };
-
- pcie {
- compatible = "marvell,armada-370-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
-
- /* x1 port */
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
- <0 0 0 2 &pcie1_intc 1>,
- <0 0 0 3 &pcie1_intc 2>,
- <0 0 0 4 &pcie1_intc 3>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 8>;
- status = "disabled";
-
- pcie1_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- /* x1 port */
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2_intc 0>,
- <0 0 0 2 &pcie2_intc 1>,
- <0 0 0 3 &pcie2_intc 2>,
- <0 0 0 4 &pcie2_intc 3>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
-
- pcie2_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- /* x1 port */
- pcie@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
- 0x81000000 0 0 0x81000000 0x3 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3_intc 0>,
- <0 0 0 2 &pcie3_intc 1>,
- <0 0 0 3 &pcie3_intc 2>,
- <0 0 0 4 &pcie3_intc 3>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 6>;
- status = "disabled";
-
- pcie3_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
- };
- };
-};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
index 070d10a705bb..a313d5687789 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
@@ -82,7 +82,6 @@
mmc-ddr-1_8v;
mmc-hs400-1_8v;
sd-uhs-sdr104;
- marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
vqmmc-supply = <&vsdc_reg>;
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index fed2dcecb323..37e16fb3a383 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -78,7 +78,6 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
- marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
index 242820845707..12deacb741cc 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
@@ -15,6 +15,11 @@
#include "armada-372x.dtsi"
/ {
+ aliases {
+ ethernet0 = &eth0;
+ ethernet1 = &eth1;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -156,7 +161,7 @@
&usb3 {
status = "okay";
phys = <&usb2_utmi_otg_phy>;
- phy-names = "usb2-utmi-otg-phy";
+ phy-names = "usb2-phy";
};
&uart0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 87f9367aec12..360fc24fdde2 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -369,11 +369,10 @@
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
- marvell,usb-misc-reg = <&usb32_syscon>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 12>;
- phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
- phy-names = "usb3-phy", "usb2-utmi-otg-phy";
+ phys = <&usb2_utmi_otg_phy>, <&comphy0 0>;
+ phy-names = "usb2-phy", "usb3-phy";
status = "disabled";
};
@@ -393,10 +392,9 @@
usb2: usb@5e000 {
compatible = "marvell,armada-3700-ehci";
reg = <0x5e000 0x1000>;
- marvell,usb-misc-reg = <&usb2_syscon>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_utmi_host_phy>;
- phy-names = "usb2-utmi-host-phy";
+ phy-names = "usb";
status = "disabled";
};
@@ -534,7 +532,6 @@
armada-3700-rwtm {
compatible = "marvell,armada-3700-rwtm-firmware";
mboxes = <&rwtm 0>;
- status = "okay";
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
index 2b5ec4a451e3..0cfcf5f6bde1 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
@@ -70,7 +70,7 @@
&cp0_eth1 {
status = "okay";
- phy = <&phy0>;
+ phy-handle = <&phy0>;
phy-mode = "rgmii-id";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
deleted file mode 100644
index b6fc18876093..000000000000
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
- * two CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-80x0.dtsi"
-
-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
- * in CP master is not connected (by package) to the oscillator. So
- * disable it. However, the RTC clock in CP slave is connected to the
- * oscillator so this one is let enabled.
- */
-
-&cp0_rtc {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
deleted file mode 100644
index 028496ebc473..000000000000
--- a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Marvell International Ltd.
- *
- * Device tree for the CN9130-DB Com Express CPU module board.
- */
-
-#include "cn9130-db.dtsi"
-
-/ {
- model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
- compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
- "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
-};
-
-&ap0_reg_sd_vccq {
- regulator-max-microvolt = <1800000>;
- states = <1800000 0x1 1800000 0x0>;
- /delete-property/ gpios;
-};
-
-&cp0_reg_usb3_vbus0 {
- /delete-property/ gpio;
-};
-
-&cp0_reg_usb3_vbus1 {
- /delete-property/ gpio;
-};
-
-&cp0_reg_sd_vcc {
- status = "disabled";
-};
-
-&cp0_reg_sd_vccq {
- status = "disabled";
-};
-
-&cp0_sdhci0 {
- status = "disabled";
-};
-
-&cp0_eth0 {
- status = "disabled";
-};
-
-&cp0_eth1 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
-};
-
-&cp0_eth2 {
- status = "disabled";
-};
-
-&cp0_mdio {
- status = "okay";
- pinctrl-0 = <&cp0_ge_mdio_pins>;
- phy0: ethernet-phy@0 {
- status = "okay";
- };
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
-
- cp0_ge_mdio_pins: ge-mdio-pins {
- marvell,pins = "mpp40", "mpp41";
- marvell,function = "ge";
- };
- };
-};
-
-&cp0_sdhci0 {
- status = "disabled";
-};
-
-&cp0_spi1 {
- status = "okay";
-};
-
-&cp0_usb3_0 {
- status = "okay";
- usb-phy = <&cp0_usb3_0_phy0>;
- phy-names = "usb";
- /delete-property/ phys;
-};
-
-&cp0_usb3_1 {
- status = "okay";
- usb-phy = <&cp0_usb3_0_phy1>;
- phy-names = "usb";
- /delete-property/ phys;
-};