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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-31 14:11:56 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-31 17:28:46 +0200 |
| commit | a7c66cd86ae0a2377b6efda56b93b26ce1f4322e (patch) | |
| tree | af38b4c82717babfb4dd5755f7abf8c1507e75e4 | |
| parent | b37a6434cfa9477e6e5cb386e7e3d135073aef63 (diff) | |
| download | lwn-a7c66cd86ae0a2377b6efda56b93b26ce1f4322e.tar.gz lwn-a7c66cd86ae0a2377b6efda56b93b26ce1f4322e.zip | |
drm/i915: Assume 400MHz cdclk for the rest of gen4-7
We don't currently have cdclk extraction code for 965g,snb,ivb.
Let's assume 400 MHz until we know better. That seems to match hints
in various vague documents. Whether that's good enough is not
entirely clear.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c43716a3ad2e..44a146b27c2f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13506,7 +13506,8 @@ static void intel_init_display(struct drm_device *dev) else if (IS_GEN5(dev)) dev_priv->display.get_display_clock_speed = ilk_get_display_clock_speed; - else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) + else if (IS_I945G(dev) || IS_BROADWATER(dev) || + IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) dev_priv->display.get_display_clock_speed = i945_get_display_clock_speed; else if (IS_I915G(dev)) |