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#ifndef _ASM_M32R_CACHE_H
#define _ASM_M32R_CACHE_H

/* $Id$ */

/* L1 cache line size */
#define L1_CACHE_SHIFT		4
#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#endif  /* _ASM_M32R_CACHE_H */