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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Copyright (c) 2017-2019 Andreas Färber
 */

/memreserve/ 0x00000000 0x0000a800; /* boot code */
/memreserve/ 0x0000a800 0x000f5800;
/memreserve/ 0x17fff000 0x00001000;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "realtek,rtd1195";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clock-frequency = <1000000000>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rpc_comm: rpc@b000 {
			reg = <0x0000b000 0x1000>;
		};

		audio@1b00000 {
			reg = <0x01b00000 0x400000>;
		};

		rpc_ringbuf: rpc@1ffe000 {
			reg = <0x01ffe000 0x4000>;
		};

		secure@10000000 {
			reg = <0x10000000 0x100000>;
			no-map;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <27000000>;
	};

	osc27M: osc {
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
		#clock-cells = <0>;
		clock-output-names = "osc27M";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x0000a800>,
			 <0x18000000 0x18000000 0x00070000>,
			 <0x18100000 0x18100000 0x01000000>,
			 <0x80000000 0x80000000 0x80000000>;

		wdt: watchdog@18007680 {
			compatible = "realtek,rtd1295-watchdog";
			reg = <0x18007680 0x100>;
			clocks = <&osc27M>;
		};

		uart0: serial@18007800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x18007800 0x400>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clock-frequency = <27000000>;
			status = "disabled";
		};

		uart1: serial@1801b200 {
			compatible = "snps,dw-apb-uart";
			reg = <0x1801b200 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clock-frequency = <27000000>;
			status = "disabled";
		};

		gic: interrupt-controller@ff011000 {
			compatible = "arm,cortex-a7-gic";
			reg = <0xff011000 0x1000>,
			      <0xff012000 0x2000>,
			      <0xff014000 0x2000>,
			      <0xff016000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};