/*
* Copyright (c) 2016 MediaTek Inc.
* Author: John Crispin <john@phrozen.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
/ {
compatible = "mediatek,mt7623";
interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "mediatek,mt6589-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
};
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
rtc32k: oscillator@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "rtc32k";
};
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt7623-topckgen",
"mediatek,mt2701-topckgen",
"syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt7623-infracfg",
"mediatek,mt2701-infracfg",
"syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt7623-pericfg",
"mediatek,mt2701-pericfg",
"syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt7623-pinctrl",
"mediatek,mt2701-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
syscfg_pctl_a: syscfg@10005000 {
compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt7623-scpsys",
"mediatek,mt2701-scpsys",
"syscon";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
infracfg = <&infracfg>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_MFG_SEL>,
<&topckgen CLK_TOP_ETHIF_SEL>;
clock-names = "mm", "mfg", "ethif";
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt7623-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
timer: timer@10008000 {
compatible = "mediatek,mt7623-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc32k>;
clock-names = "system-clk", "rtc-clk";
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt7623-pwrap",
"mediatek,mt2701-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
reset-names = "pwrap";
clocks = <&infracfg CLK_INFRA_PMICSPI>,
<&infracfg CLK_INFRA_PMICWRAP>;
clock-names = "spi", "wrap";
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt7623-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200100 0 0x1c>;
};
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt7623-apmixedsys",
"mediatek,mt2701-apmixedsys",
"syscon";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x2000>,
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART0_SEL>,
<&pericfg CLK_PERI_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART1_SEL>,
<&pericfg CLK_PERI_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART2_SEL>,
<&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART3_SEL>,
<&pericfg CLK_PERI_UART3>;
clock-names = "baud", "bus";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt7623-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11007000 0 0x70>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C0>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt7623-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11008000 0 0x70>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C1>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt7623-i2c",
"mediatek,mt6577-i2c";
reg = <0 0x11009000 0 0x70>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C2>,
<&pericfg CLK_PERI_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI0_SEL>,
<&pericfg CLK_PERI_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi1: spi@11016000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11016000 0 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI1_SEL>,
<&pericfg CLK_PERI_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11017000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11017000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI2_SEL>,
<&pericfg CLK_PERI_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
nandc: nfi@1100d000 {
compatible = "mediatek,mt7623-nfc",
"mediatek,mt2701-nfc";
reg = <0 0x1100d000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&pericfg CLK_PERI_NFI>,
<&pericfg CLK_PERI_NFI_PAD>;
clock-names = "nfi_clk", "pad_clk";
status = "disabled";
ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
};
bch: ecc@1100e000 {
compatible = "mediatek,mt7623-ecc",
"mediatek,mt2701-ecc";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI_ECC>;
clock-names = "nfiecc_clk";
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7623-mmc",
"mediatek,mt8135-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&topckgen CLK_TOP_MSDC30_0_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt7623-mmc",
"mediatek,mt8135-mmc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1>,
<&topckgen CLK_TOP_MSDC30_1_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
"syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys",
"mediatek,mt2701-ethsys",
"syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
};
