summaryrefslogblamecommitdiff
path: root/arch/arm/boot/dts/meson8m2.dtsi
blob: 2397ba06d608034c01eb8efa2feb83d8d9c5b47d (plain) (tree) 
e592f6585cdf ^
















10256a4755db ^










e592f6585cdf ^






b632506c5af2 ^



e592f6585cdf ^























7e26335b1a3f ^

e592f6585cdf ^




c0ad99a2deac ^




f5a7382d6f17 ^








e592f6585cdf ^



1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26

27
28
29
30
31
32

33
34
35

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

59

60
61
62
63

64
65
66
67

68
69
70
71
72
73
74
75

76
77
78
















                                                                               









                                                                               





                                                            


                                                                           






















                                                               
                                     



                  



                                                                       







                                                                              


                                                                   
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
 */

#include "meson8.dtsi"

/ {
	model = "Amlogic Meson8m2 SoC";
	compatible = "amlogic,meson8m2";
}; /* end of / */

&clkc {
	compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
};

&dmcbus {
	/* the offset of the canvas registers has changed compared to Meson8 */
	/delete-node/ video-lut@20;

	canvas: video-lut@48 {
		compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
		reg = <0x48 0x14>;
	};
};

&ethmac {
	compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
	reg = <0xc9410000 0x10000
		0xc1108140 0x8>;
	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
	resets = <&reset RESET_ETHERNET>;
	reset-names = "stmmaceth";
};

&pinctrl_aobus {
	compatible = "amlogic,meson8m2-aobus-pinctrl",
		     "amlogic,meson8-aobus-pinctrl";
};

&pinctrl_cbus {
	compatible = "amlogic,meson8m2-cbus-pinctrl",
		     "amlogic,meson8-cbus-pinctrl";

	eth_rgmii_pins: ethernet {
		mux {
			groups = "eth_tx_clk_50m", "eth_tx_en",
				 "eth_txd3", "eth_txd2",
				 "eth_txd1", "eth_txd0",
				 "eth_rx_clk_in", "eth_rx_dv",
				 "eth_rxd3", "eth_rxd2",
				 "eth_rxd1", "eth_rxd0",
				 "eth_mdio", "eth_mdc";
			function = "ethernet";
			bias-disable;
		};
	};
};

&saradc {
	compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
};

&usb0_phy {
	compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
};

&usb1_phy {
	compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
};

&wdt {
	compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
};