summaryrefslogblamecommitdiff
path: root/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
blob: 0df6f016b1b771611fe4c83a8db76fc00d9db0f8 (plain) (tree) 
12ece40d9196 ^

























1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

























                                                              
* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock

RTC controller for the Xilinx Zynq MPSoC Real Time Clock
Separate IRQ lines for seconds and alarm

Required properties:
- compatible: Should be "xlnx,zynqmp-rtc"
- reg: Physical base address of the controller and length
       of memory mapped region.
- interrupts: IRQ lines for the RTC.
- interrupt-names: interrupt line names eg. "sec" "alarm"

Optional:
- calibration: calibration value for 1 sec period which will
		be programmed directly to calibration register

Example:
rtc: rtc@ffa60000 {
	compatible = "xlnx,zynqmp-rtc";
	reg = <0x0 0xffa60000 0x100>;
	interrupt-parent = <&gic>;
	interrupts = <0 26 4>, <0 27 4>;
	interrupt-names = "alarm", "sec";
	calibration = <0x198233>;
};