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2026-10-13clk: qcom: gpucc-sc8280xp: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-38-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gpucc-sc7280: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Move the GMU branch register update into the clk_regs_configure callback so it still follows the always-on branch enables. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-37-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gpucc-sar2130p: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-36-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-x1e80100: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-35-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8750: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-34-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8650: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-33-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8550: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-32-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8450: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array and describe the DFS RCGs through qcom_cc_driver_data. Move the UFS PHY ICE core FORCE_MEM_CORE_ON setting into the clk_regs_configure callback. This moves the UFS setting after the always-on branch enables. Those branches serve the camera, display, GPU and video blocks, not the UFS PHY ICE core clock. The UFS setting is still applied before GDSC and CCF clock registration. Keep the SM8475-specific PLL and RCG adjustments in the driver's probe before calling qcom_cc_probe(), which now handles register mapping and the common initialization sequence. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-31-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8350: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-30-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8250: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-29-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm7150: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-28-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm4450: Use common clock controller probe dataAbel Vesa
Describe the always-on branches, DFS RCGs and GPLL3 through qcom_cc_driver_data. Associate GPLL3 with its existing configuration so the common PLL setup invokes the Lucid EVO configuration helper. Move the UFS PHY ICE core FORCE_MEM_CORE_ON setting and the video branch register update into the clk_regs_configure callback. This moves the UFS setting after the always-on branch enables. Those branches serve the camera, display, GPU and video blocks, not the UFS PHY ICE core clock. The UFS setting is still applied before GDSC and CCF clock registration, while GPLL3 configuration still precedes the branch enables. Use qcom_cc_probe() for the resulting common initialization sequence instead of open-coding it in gcc_sm4450_probe(). Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-26-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sdx75: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array and describe the DFS RCGs through qcom_cc_driver_data. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-25-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sdx65: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-24-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sdx55: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-23-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sc8280xp: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array and describe the DFS RCGs through qcom_cc_driver_data. Delegate always-on branch and DFS initialization to the common probe path while retaining the device-specific setup in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-22-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sc7280: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-21-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sc7180: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-20-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sar2130p: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-19-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sa8775p: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-18-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-qcs8300: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-17-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-qcs615: Use common clock controller probe dataAbel Vesa
Move the always-on branch register offsets into a critical_cbcrs array, describe the DFS RCGs through qcom_cc_driver_data and move the register programming into the clk_regs_configure callback. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-16-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc1-sa8775p: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-15-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc0-sa8775p: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-14-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-x1e80100: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-13-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm8750: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-12-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm8550: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-11-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm8250: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-10-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm7150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-9-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm6115: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-8-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm4450: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-7-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sc8280xp: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Share the CBCR data between the two display controller descriptors. The XO branch is now enabled by the common probe before clock registration. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-6-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sc7280: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-5-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sm8150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-4-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sm7150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-3-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sc8280xp: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-2-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sa8775p: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Keep separate CBCR arrays for SA8775P and QCS8300 to preserve their different CAMNOC XO, GDSC and sleep clock register offsets. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-1-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Clear force enable after rate failureKonrad Dybcio
Shared RCG rate changes assert force-enable before programming the new configuration. If programming fails, the function returns without clearing force-enable, leaving the root running while CCF can release temporary parent and resource references. Attempt to clear force-enable on the configuration error path before returning the original programming error. This restores the same cleanup performed after a successful configuration while preserving the primary failure for callers. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-3-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Propagate force-enable status errorsKonrad Dybcio
clk_rcg2_is_enabled() returns either a hardware status or a negative regmap error. The force-enable polling loop treats every nonzero return as an enabled clock, so a failed status read is incorrectly reported as success and clock reconfiguration can continue with unknown hardware state. Check for negative returns before testing the enabled status and propagate the read error to the caller. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-2-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Initialize shared floor clock stateKonrad Dybcio
Shared floor RCGs use the cached parked_cfg whenever CCF considers the clock disabled. Unlike the other shared RCG variants, their ops do not initialize that cache, leaving it zeroed until the first disable or rate change. This can make registration report an undivided XO configuration instead of the boot-programmed parent and divider. Initialize parked_cfg from CFG_REG without parking or otherwise changing the hardware. Propagate read failures so a clock with unknown initial state is not registered. Fixes: aec8c0e28ce4 ("clk: qcom: rcg2: add clk_rcg2_shared_floor_ops") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-1-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-msm8960: Configure PLL15 only on APQ8064Abel Vesa
PLL15 is specific to APQ8064, but the shared probe function configures it unconditionally, including on MSM8960. Its configuration registers at offsets 0x33c through 0x348 exceed the MSM8960 regmap maximum of 0x334, so regmap rejects these accesses. The PLL configuration helper ignores the errors and probe continues. Only configure PLL15 when the selected descriptor is for APQ8064, matching the existing variant check for the GFX3D clock adjustments. Fixes: e216ce60a9e0 ("clk: qcom: Add support for APQ8064 multimedia clocks") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-msm8960-fix-pll15-config-v1-1-11fae0be111d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-sdm660: Fix MDSS AHB clock HWCG register offsetAbel Vesa
The MDSS AHB clock HWCG bit resides in the same register as the branch enable and halt status bits, at offset 0x2308. The current HWCG register offset of 0x8a004 exceeds the regmap maximum of 0x40000, so regmap rejects the read in clk_branch_in_hwcg_mode(). Since the read error is ignored, the helper uses an uninitialized value to decide whether to skip the halt status check. Correct the HWCG register offset so the helper reads the actual hardware clock gating state. Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-sdm660-fix-mdss-ahb-hwcg-offset-v1-1-30dcf09d907c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-msm8996: Fix FD AHB clock register offsetAbel Vesa
The FD AHB clock branch register is at offset 0x3b74, not 0x3ba74. The incorrect offset exceeds the regmap maximum of 0xb008, so regmap rejects accesses to it and the clock cannot be enabled. Correct both the enable and halt register offsets so the driver can enable the branch and check its status. Assisted-by: LLM Fixes: c252659770db ("clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-msm8996-fix-fd-ahb-offset-v1-1-a575e1b9112c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-ipq5424: Fix TME reset register offsetsAbel Vesa
The GCC_TME_BCR and GCC_TME_SEC_BUS_BCR offsets exceed the regmap maximum of 0x3f024. Regmap therefore rejects accesses to both registers, leaving the resets ineffective while the reset operations report success. The offsets appear to contain typographical errors. Use 0x10000 for GCC_TME_BCR, matching the offset used on IPQ9574 and the surrounding register layout. Use 0x1a030 for GCC_TME_SEC_BUS_BCR, placing it in the same register block as GCC_SEC_CTRL_BCR at 0x1a000. Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-gcc-ipq5424-fix-tme-bcrs-offsets-v1-1-0fa10674908a@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLKKonrad Dybcio
These clocks are PHY-sourced and their halt bits seem not to update reliably. Ignore it to prevent spurious warnings. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-topic-hamoa_clk_usb4-v1-1-5d8d5225b598@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-glymur: Use clk_regmap_phy_mux_ops for GCC UFS muxesJagadeesh Kona
Use clk_regmap_phy_mux_ops for GCC UFS muxes so these muxes are automatically switched to UFS external symbol clocks during enable and safely parked at XO clk during disable. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-glymur-ufs-clk-changes-v2-2-d0aa1c60c269@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rpmhcc: Add LNBB clocks support for GlymurJagadeesh Kona
Add support for rpmh LN_BB_CLK2 and LN_BB_CLK3 clocks on Qualcomm Glymur platform. Fixes: ebcb9db98bda ("clk: qcom: rpmh: Add support for Glymur rpmh clocks") Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-glymur-ufs-clk-changes-v2-1-d0aa1c60c269@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Assign .num before accessing .hwsAamir Ahmed
hw_data->hws[] is annotated with __counted_by(num), so hw_data->num must hold the element count before the array is accessed. ipq_cmn_pll_register_clks() assigns it only after storing the fixed rate output clocks and the CMN PLL, and the unwind loop under unregister_fixed_clk reads .hws[] with .num still zero. Both are out-of-bounds accesses under CONFIG_UBSAN_BOUNDS. Move the assignment to right after the allocation. Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Aamir Ahmed <elb12345@hotmail.co.uk> Reviewed-by: Luo Jie <jie.luo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/AS8P251MB000187BDFAD98A21F4C356E9C8BD2@AS8P251MB0001.EURP251.PROD.OUTLOOK.COM Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210Luo Jie
Add the IPQ5210 output clock array and the device match table entry, wiring together all the infrastructure added in the previous patches. The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-10-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocksLuo Jie
Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed rate with enable/disable/is_enabled gate control through the shared regmap for CMN_PLL_OUTPUT_RELATED_1. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). Parent the gated fixed-rate output clocks on `cmn_pll_div2` to reflect the CMN PLL clock hierarchy. Their rates remain fixed constants returned by `clk_fixed_gate_recalc_rate()`. Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-9-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>