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path: root/drivers/gpu
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2026-10-01drm/amd/display: Add dcn60 revision specific clock overridesDillon Varone
[WHY&HOW] Not all revisions require the same clock overrides. Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add missing message to static_assertDominik Kaszewski
[Why & How] static_assert requires a message in older standards. Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Serialize HDMI FRL status polling against link detectFangzhi Zuo
[WHY] The HDMI FRL status polling work can run concurrently with link detect after an unplug/replug. Both paths access the same link through DDC and may perform FRL link training, while the polling path also reads link state without holding dc_lock. [HOW] Use mutex_trylock() to serialize the complete link walk, FRL status polling, and retraining sequence with dc_lock. If the lock is busy, defer the background poll to the next 200ms cycle instead of blocking an active detect, modeset, or flip. Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix DCN60 UTM QoS override for invalid PMFW tableWenjing Liu
[Why] The QoS model override for a display IP block was silently skipped whenever the firmware-populated table was invalid. [How] Always re-point the bandwidth params at the driver's own persistent QoS model storage before applying the override, instead of returning early when the firmware-populated model is NULL. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Consolidate bandwidth overridesWenjing Liu
[Why] Bandwidth overrides must be applied in a defined order so debug settings are reflected in the final parameters. [How] Group clock adjustments with the clock table override and derive the final mode limits after all clock table changes. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Synchronize UTM overrides with SMUWenjing Liu
[Why] Keep the display QoS model and firmware table consistent when test overrides are enabled. [How] Serialize the overridden QoS values into a dedicated transfer buffer and send the table after clock initialization. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Move struct dtbclk_dto_params to dc_hw_types.hTony Cheng
This can simplify includes Assisted-by: Cursor:composer-2.5 Signed-off-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: specify cwsr_enable usage docEric Huang
to prevent misunderstanding in cwsr off case. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdkfd: Fix always mapped range mapping to all ACCESS GPUsAndrew Martin
CWSR ranges use the always mapped flag and only need a mapping on the GPU running the queue. However, svm_range_validate_and_map now updates the mapping on every GPU with the ACCESS attribute, which is all supported GPUs when XNACK is on. After the range is prefetched to VRAM, those GPUs may span different XGMI hives, so the page owner mismatches and is set to NULL. hmm_range_fault then tries to migrate the VRAM pages back to system memory, but svm_migrate_to_ram skips it because migrating pages back to system memory is not allowed while the GPU mapping is being updated, so the CPU page fault is never resolved. Only map to the ACCESS GPUs if the range is not mapped to any GPU and is not in VRAM. Fixes: b96f26104946 ("drm/amdkfd: Unmap svm range from GPU set to no-access") Signed-off-by: Andrew Martin <andrew.martin@amd.com> Assisted-by: Claude:claude-opus-5 Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0 supportHawking Zhang
Add initial implemenation for the new generation of mmhub Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0_1 ip headers v3Alex Deucher
Add header files for mmhub v5_0_1 register offsets and shift masks v2: Update mmhub ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use PCRU0 C2PMSG for Uniras on psp v15_0_3Candice Li
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127 for psp ring wptr and RAS capability query. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for psp v15_0_3Gangliang Xie
add uniras support for psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for nbio v7_10_0Gangliang Xie
add uniras support for nbio v7_10_0 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for smu v15_0_3Gangliang Xie
add uniras support for smu_v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for GC 13Gangliang Xie
add uniras support for GC 13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for umc v13Gangliang Xie
add uniras support for umc v13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: skip vpe dpm enable if dpm_enabled flag is falseLin Cao
amdgpu_dpm_enable_vpe() should be skipped if dpm_enabled is false Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Allocate VPE cmdbuf from VRAMLin Cao
PSP should not accept a GART VA directly from VF Add logical to allocate VPE cmdbuf from VRAM Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.1 supportCaden Chien
This initializes VPE IP version 3.0.1 Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.0 supportCaden Chien
This patch adds support for vpe v3.0.0 with new structs and ip functions Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add vpe v3_0_0 ip headers v4Hawking Zhang
Add header files for vpe v3_0_0 register offsets and shift masks v2: Update vpe ip headers to LSC version v3: Update vpe ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/psp: wait for TOS ready on all AIDs in v15_0_3 ring createEmily Deng
When aid_mask is set, poll MP0 C2PMSG_64 on each AID instance before creating the PSP GFX command ring. Single-die paths are unchanged. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add VPE FW list to PSP_15_0_3 under SRIOVLin Cao
Add VPE FW list including VPE_CTX and VPE_CTL Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add GFX FW list to PSP_15_0_3 under SRIOVLin Cao
[Why] Under SRIOV VF, GFX firmware are required to loaded. [How] Add GFX FW list. FW contains: PFP ucode, PFP data P0-P1 ME ucode, ME data P0-P1 MEC ucode, MEC data P0-P7 MES SCH ucode and data MES KIQ ucode and data Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add new MEC2 firmware loading frameworkLin Cao
Add ucode loading support for MEC pipe stacks P4-P7: - add GFX_FW_TYPE_RS64_MEC_P4..P7 firmware types - add AMDGPU_UCODE_ID_CP_RS64_MEC_P4..P7 ucode ids - handle P4-P7 in ucode name/init, psp fw type Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Yiqing Yao <yiqing.yao@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: support MP5 in firmware info queriesYang Wang
Handle AMDGPU_INFO_FW_MP5 in the firmware query path and report the MP5 firmware version in the debugfs firmware_info output. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: expose MP5 firmware version in sysfsYang Wang
Add an mp5_fw_version attribute to the fw_version sysfs group, so userspace can read the MP5 firmware version. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add infrastructrure for handling mp5 firmwareFrank Min
Add framework for MP5 firmware. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add ta loading in psp v15_0_3Gangliang Xie
add ta loading in psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix ASP 15.0.3 runtime DB offsetYang Wang
ASP 15.0.3 stores the PSP runtime database at a fixed 64KB offset from the IP discovery table, not at the legacy offset from the end of VRAM. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add firmware type retrieval in PSP v15.0.3Frank Min
Add firmware type retrieval in PSP v15.0.3 to adapt psp fw updates Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add support for PSP version 15.0.3Frank Min
Add support for PSP version 15.0.3 v2: fix psp 15.0.3 C2P message reg access issue Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mp v15_0_3 ip headers v4Hawking Zhang
Add header files for mp v15_0_3 register offsets and shift masks v2: Update mp ip headers to LSC version v3: Update mp ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add support for lsdma v8Likun Gao
Add support for LSDMA v8 v2: fix wait_pio_status() per Philip's comments. Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add lsdma v8_0_1 ip headersHawking Zhang
Add header files for lsdma v8_0_1 register offsets and shift masks v2: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add hdp v8 ip blockFrank Min
add hdp v8 ip block Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add hdp v8_0_1 ip headers v3Hawking Zhang
Add header files for hdp v8_0_1 register offsets and shift masks v2: Update hdp ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add smuio v15_0_3 supportHawking Zhang
Add initial implementation for the new generation of smuio v2: squash in clock counter changes Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add smuio v15_0_3 ip headers v4Hawking Zhang
Add header files for smuio v15_0_3 register offsets and shift masks v2: Update smuio ip headers to LSC version v3: Update smuio ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fall back to RCC_HW_DEBUG for VF frame buffer sizeZhenGuo Yin
On some SR-IOV VFs RCC_CONFIG_MEMSIZE reads back 0. Fall back to RCC_HW_DEBUG for the frame buffer size in the nbif get_memsize() callback and in the early-init paths that read the register directly. Only VFs that read back 0 are affected. Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com> Reviewed-by: Frank Min <frank.min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add nbif v7_10 supportHawking Zhang
Add initial implementation for the new generation of nbif v2: squash in HDP, VPE, RLC/IH, SDMA fixes Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add pcie v6_1_3 ip headers v4Hawking Zhang
Add header files for pcie v6_1_3 register offsets and shift masks v2: Update pcie ip headers to LSC version v3: Update pcie ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add nbif v7_10_0 ip headers v4Hawking Zhang
Add header files for nbif v7_10_0 register headers and shift masks v2: Update nbif ip headers to LSC version v3: Update nbif ip headers to BTO version v4: Update registers (Alex) v5: Squash in SR-IOV updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/discovery: Add ih v8_0 ip blockHawking Zhang
Add ih v8_0 ip block Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add ih v8_0 supportHawking Zhang
Add initial implementation for the new generation of ih v2: squash in flood control fix Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add osssys v8_0_1 ip headers v3Hawking Zhang
Add header files for osssys v8_0_1 register offsets and shift masks v2: Update osssys ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add soc v2_0 ih client id tableHawking Zhang
To acommandate the specific ih client for soc v2_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix ip discovery table validationLin Cao
Fix ip discovery table_check, get_mall_info, and get_vcn_info to guard on both offset and size being non-zero before parsing. Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix atomics on DF 5.0.2Eric Huang
DF 5.0.2 needs to program DF config register as DF 4.15.x, so share the functions, they have the same register layout. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: David Belanger <david.belanger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>