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2026-08-03drm/xe: split VF pause into prepare and revert phasesNiranjana Vishwanathapura
Extract xe_sched_submission_stop() + cancel_delayed_work_sync() into a new guc_exec_queue_pause_prepare() helper, then call it in a first pass over all queues before the existing revert loop in xe_guc_submit_pause_vf(). In a multi-queue group a secondary's run_job() can register the primary queue, which must not race an in-progress revert of a sibling queue. Stopping every scheduler before reverting any queue prevents that race. No functional change outside the VF migration path. Assisted-by: Github-Copilot:Claude-opus-4.8 Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260803230528.3428029-7-niranjana.vishwanathapura@intel.com
2026-08-04drm/xe/uc: Apply RCS/CCS yield policy to SR-IOV VFsMarcin Bernatowicz
VFs were missing the call to apply the global scheduling policy. Call xe_guc_submit_enable() during vf_uc_load_hw() to ensure VFs get the same policy enforcement as PF. Fixes: 26caeae9fb48 ("drm/xe/guc: Set RCS/CCS yield policy") Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patch.msgid.link/20260709075945.1337660-1-marcin.bernatowicz@linux.intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2026-08-04drm/xe: Reject duplicated properties for EXEC_QUEUE_SET_PROPERTYMichał Winiarski
All of the properties are idempotent - setting them multiple times on the same exec_queue within a single IOCTL doesn't make sense. Return an error when duplicated property is found. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260624111421.1258364-2-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2026-08-04drm/xe: Fix memory leak in exec_queue_set_hang_replay_state()Michał Winiarski
The q->replay_state is blindly overwritten, which can potentially leak memory that was previously allocated by vmemdup_user(). Return an error if q->replay_state is not empty. Discovered using AI-assisted static analysis confirmed by Intel Product Security. Reported-by: Martin Hodo <martin.hodo@intel.com> Fixes: 1026c1a73a96 ("drm/xe: Implement DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE") Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260624111421.1258364-1-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2026-08-03drm/xe: Add debugfs for IA/GT biasVinay Belgaumkar
GT_IA_PERF_BIAS_REG indicates power budget between IA and GT. Lower 16 bits correspond to IA and upper to GT. Higher value indicates more bias towards that plane. The values are in U1.15 format. $ cat /sys/kernel/debug/dri/0/gt0/gt_ia_bias 0x80004000 (GT: 1.0000, IA: 0.5000) This interface will allow us to observe power budget changes while running workloads and also, if needed, tune it. Minimum allowed value for each of GT/IA bias is 0x10, and max is 0x8000 which corresponds to a bias ratio of 1. Bspec: 51878 v3: Add a helper function for U1.15 decode (Michal) v4: Validate input values (Rodrigo) v5: Comments (Michal, Rodrigo) v6: Rename to gt_ia_bias (Anirban), check lower bound (Michal) v7: Update filename in commit message Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Sk Anirban <sk.anirban@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Assisted-by: Copilot:auto Reviewed-by: Sk Anirban <sk.anirban@intel.com> Link: https://patch.msgid.link/20260729221629.593195-3-vinay.belgaumkar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-08-03drm/xe: Use IBC v3 on PTLVinay Belgaumkar
Intelligent Bias Control (IBC) v3 algorithm in GuC has PTL specific optimizations. This version selection param is only available GuC 70.48.0 onwards. v4: Fix sashiko.dev review issue v5: Don't cascade return checks (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20260729221629.593195-2-vinay.belgaumkar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-08-03drm/panel-edp: Add Sharp LQ120P1JX51 (Surface Pro 12in 1st Ed.)François Roux
The internal eDP panel of the Microsoft Surface Pro 12in 1st Edition (Snapdragon X Plus, X1P42100) is not in edp_panels[], so every boot produces the deliberate WARN_ON splat in panel_edp_probe() and the panel falls back to conservative timings: WARNING: drivers/gpu/drm/panel/panel-edp.c:814 panel_edp_probe+0x53c/0x56c panel-simple-dp-aux aux-aea0000.displayport-controller: Unknown panel SHP 0x15a7, using conservative timings EDID, read over the panel's DP AUX DDC bus: 00 ff ff ff ff ff ff 00 4d 10 a7 15 a0 00 00 1f 31 22 01 04 a5 19 11 78 07 ee 91 a3 54 4c 99 26 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 62 53 94 a0 80 b8 2e 50 18 10 3a 00 fe a9 00 00 00 18 13 7d 94 a0 80 b8 2e 50 18 10 3a 00 fe a9 00 00 00 18 00 00 00 fd 00 18 5a 88 88 21 01 00 00 00 00 00 00 00 00 00 00 fc 00 4c 51 31 32 30 50 31 4a 58 35 31 0a 20 00 69 Manufacturer: SHP Model: 0x15a7 Made in: week 49 of 2024 Display Product Name: 'LQ120P1JX51' DTD 1: 2196x1464 60.001799 Hz 3:2 (254 mm x 169 mm) DTD 2: 2196x1464 90.002698 Hz 3:2 (254 mm x 169 mm) Timings are deliberately cautious rather than datasheet-derived. The conservative fallback sets unprepare=2000 and enable=200; unprepare=2000 is a safety margin for unknown panels only and is the single occurrence of that value in the file -- no real panel entry uses it. delay_200_500_e200 keeps the same generous 200 ms enable delay while using the 500 ms unprepare shared by every actual panel in the table. A shorter enable delay may well be fine, but has not been validated here. Signed-off-by: François Roux <info@humanlearning.ch> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20260802135107.4420-1-info@humanlearning.ch
2026-08-03drm/xe/mert: Rate limit VF LMTT fault debug logPiotr Piórkowski
A faulty or malicious VF may repeatedly trigger LMTT faults and generate many identical CATERR debug messages. Use xe_sriov_dbg_ratelimited() to reduce log spam while keeping useful debug information available. Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260721093116.4011940-3-piotr.piorkowski@intel.com Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
2026-08-03drm/xe: Add dbg_ratelimited printk wrappersPiotr Piórkowski
Add dbg_ratelimited() wrappers for Xe logging helpers. These wrappers provide a debug logging equivalent of the existing rate-limited error messages and allow callers to limit repeated debug prints to reduce log spam and makes debugging easier. Reviewed-by: Lukasz Laguna <lukasz.laguna@intel.com> Link: https://patch.msgid.link/20260721093116.4011940-2-piotr.piorkowski@intel.com Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
2026-08-03drm/imagination: Reuse layout check macros for MIPS FW structuresAlessio Belle
Replace static asserts on MIPS firmware structures offsets and sizes with more compact macros that are already used for similar checks on common firmware interface structures. Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260729-fwif-checks-updates-v1-2-af65e9606a7e@imgtec.com Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
2026-08-03drm/imagination: Move all FW interface check macros to pvr_checks.hAlexandru Dadu
The same macros are redefined in three places, so move them to a common file to reduce duplication and make it easier to reuse them. Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com> Co-developed-by: Alessio Belle <alessio.belle@imgtec.com> Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com> Link: https://patch.msgid.link/20260729-fwif-checks-updates-v1-1-af65e9606a7e@imgtec.com Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
2026-08-03drm/{i915,xe}/display: move transient data flush call to display parent ↵Jani Nikula
interface Move the core driver TDF call to display parent interface to avoid direct calls from display to xe driver. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260728170029.608289-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-08-03drm/xe/ras: Validate sysctrl responseRaag Jadav
Validate errors raised by sysctrl firmware instead of blindly trusting them. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260722143142.675658-1-raag.jadav@intel.com Signed-off-by: Riana Tauro <riana.tauro@intel.com>
2026-08-03drm/i915/display: Switch DG2 to use DPLL frameworkMika Kahola
Now that DG2 has a DPLL manager and its users are prepared to obtain clock state through the framework, switch the platform over to use the shared DPLL manager. Remove specific MPLLB state verification and use .compare_hw function hook to compare HW and SW PLL states. Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260630115336.1059976-5-mika.kahola@intel.com
2026-08-03drm/i915/display: Prepare DG2 DDI and compute paths for DPLL frameworkMika Kahola
Prepare DG2 users to obtain clock state and reserve PLLs through the shared DPLL framework. Replace the DG2-specific compute hook with the generic framework-backed helpers. Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260630115336.1059976-4-mika.kahola@intel.com
2026-08-03drm/i915/display: Add DG2 MPLLB DPLL manager supportMika Kahola
Add DG2-specific DPLL manager infrastructure for MPLLB-backed port PLLs. Introduce PLL id mapping, DG2-specific DPLL callbacks for enable/disable/readout/frequency calculation, and manager callbacks for compute/get/dump/compare. The platform is not switched over yet. DG2's PLL-to-encoder lookup prefers the active encoder using the PLL, but fall back to a matching encoder for the fixed port-to-PLL mapping when no active user can be identified. This keeps the active-user fix for operational paths while allowing readout and verification paths to resolve the PHY even when pll->active_mask does not identify an active user. v2: Use intel_encoder_is_dig_port() to filter out MST virtual encoders (Imre) Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> (v1) Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/20260630115336.1059976-3-mika.kahola@intel.com
2026-08-03drm/i915/display: Split out DG2 MPLLB enable helperMika Kahola
Refactor the DG2 MPLLB enable path by splitting out a helper that programs the PHY directly from an intel_mpllb_state. This is preparatory work for moving DG2 MPLLB handling under the DPLL framework, where callbacks operate on dpll_hw_state rather than the full crtc_state. Assisted-by: Copilot:claude-sonnet-4-6 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260630115336.1059976-2-mika.kahola@intel.com
2026-08-03drm/i915/vrr: Enable CMRRMitul Golani
Set crtc_state->vrr.cmrr.enable at the end of intel_vrr_cmrr_compute_config() so that CMRR is actually enabled once the M/N parameters have been computed. This is the final step that turns on CMRR, with all the parameter computation handled in the earlier patches. --v2: - Everything else except enable compute to handle before this patch (Chaitanya) --v3: - Remove redundant return from compute config --v4: - Update CMRR commit message (Chaitanya) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-11-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Dump CMRR state in the crtc state dumpMitul Golani
Add crtc state dump for CMRR. --v2: - Remove video mode state checker. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-10-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Program CMRR enable/disable from transcoder timingsMitul Golani
Move the CMRR M/N register writes into a new intel_vrr_set_cmrr_timings() helper called from intel_vrr_set_fixed_rr_timings(), so CMRR is programmed together with the fixed rr timings for both the CMTG and CPU transcoder, instead of being open-coded in intel_vrr_set_transcoder_timings(). Drop the now-unused cmrr_enable argument to intel_vrr_tg_enable(). No functional change intended for non-CMRR configurations. --v2: - Commit message changes. - Added Simplified enable/disable sequence. (Chaitanya) --v3: - Guard CMRR enable condition (Chaitanya) - Comment changes updated (Chaitanya) - Squash register write commits together and avoid double writing issue. (Chaitanya) --v4: - Guard CMRR enable/disable with platform check --v5: - Update CMRR in enable/disable path --v6: - Simplify enable/disable calls (Chaitanya) - Make function usable for common cmtg and cpu transcoder (Chaitanya) --v7: - Update commit message (Chaitanya) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-9-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Latch CMRR ratio via atomic commit on debugfs writeMitul Golani
Writing the per-CRTC "intel_vrr_target_refresh_rate" debugfs file only updates crtc->force_cmrr, a side channel that is not tracked by the atomic state. The requested ratio therefore does not reach the hardware until some unrelated commit recomputes the pipe config. Kick an internal atomic commit for the CRTC from the debugfs write and mark the CRTC mode as changed so the pipe config is recomputed. Note that this commit may or may not be downgraded to a fastset, depending on whether the computed vblank value (with LRR disabled) changes, so it is not characterised as a fastset. If the commit fails, restore the previous numerator/denominator so that force_cmrr does not hold on to bad values, which would otherwise make all subsequent commits fail. --v2: - Commit message and code comment update (Chaitanya) - Commit header update - Restore to old known debugfs values when commit fails (Chaitanya) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-8-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Compute CMRR fractional timings genericallyMitul Golani
Rework the fractional CMRR computation into a generic, transcoder-agnostic helper driven by an explicit per-CRTC debugfs target, replacing the previous disabled, eDP-only code path. Compute CMRR_M and CMRR_N timings based on the video mode requirements. A 1:1 ratio (denominator == 1000) means no video timing is required. Note that the CMRR enable path is wired up separately; this patch only lays down the generic computation. Remove computation of mode_flags, I915_MODE_FLAG_VRR, as CMRR is being moved to the fixed refresh rate path. Also return early from the CMRR computation if the existing computation is already sufficient. --v2: - Derive video_mode locally instead of caching it in the persistent struct intel_crtc state (Jani, Chaitanya) - Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya) - Fix "requirement" typo and clarify that CMRR is not yet enabled in the commit message (Chaitanya) - Fix precision issue while computing the M/N ratio (Chaitanya) - Rename multiplier_m and multiplier_n to improve readability (Chaitanya) - Compute vtotal as it is required for dithering as per the algorithm implementation (Chaitanya) - Replace the misleading adjusted_pixel_rate with dividend, which is more descriptive --v3: - Mention the rationale for not computing I915_MODE_FLAG_VRR (Chaitanya) - Remove the redundant return statement at the end of the CMRR computation (Chaitanya) - Correct cmrr_n calculation (Chaitanya) - Add an early return if the current computation is already sufficient to drive the mode without CMRR (Chaitanya) - Round up requested_refresh_rate (Validation) - Fix integer overflow --v4: - Update cmrr_n calculation to avoid aggressive dithering - Use div64_u64 to truncate to the floor value instead of DIV_ROUND_UP_ULL, which rounds up to the ceiling value - Add a TODO comment to the cmrr_n calculation - Add a condition for custom refresh rate requests - Update the CMRR computation comment block in compute_config --v5: - Simplify computation - Correct typo in commit message (Chaitanya) - Compute early return condition (Chaitanya) --v6: - Simplify commit message - Simplify video timing requirement compute function (Chaitanya) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-7-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/display: Move CMRR crtc_state members under VRRMitul Golani
Move CMRR crtc state members under VRR infrastructure as it is enabled during fixed-refresh-rate VRR timing generator is enabled. --v2: - Move cmrr structure under vrr umbrella. - Remove dups. (Jani) --v3: - Update commit message Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-6-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config requestMitul Golani
Compute AS_SDP target_rr_divider based on actual CMRR request requirement. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-5-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs controlMitul Golani
Add a per-CRTC debugfs file 'intel_vrr_target_refresh_rate' that lets the user force a CMRR target refresh rate and video-mode requirement. The file uses a "numerator/denominator" format: - numerator: requested refresh rate in milli-Hz (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz) - denominator: 1000 for a 1:1 ratio (no video timing) or 1001 for the 1000/1001 video timing Reading the file reports the currently stored values; writing updates them. The file is created only on platforms with VRR and CMRR support. --v2: - Drop the "vrr" debugfs subdirectory and expose a single flat, intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula) - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose explicit (Chaitanya) - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya) - Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya) - Expand commit message with debugfs entry semantics (Chaitanya) --v3: - Rename debugfs function and file name (Chaitanya) - Remove railing new line at EOF (Chaitanya) - Update CMRR guard conditions (Chaitanya) - Add 0/0 default case. (Ramanaidu) --v4: - Correct CMRR guard check while creating debugfs --v5: - Commit message update (Chaitanya) - Add support for 0/0 writing (Validation) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-4-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default platformsMitul Golani
CMRR is currently advertised on all HAS_CMRR platforms, but it depends on the VRR timing generator being the default timing generator, which currently only applies to DISPLAY_VER >= 30. Gate the CMRR enable condition and readout accordingly so CMRR is only reported on supported platforms. No functional change. --v2: - Create a separate function to check if CMRR possible --v3: - Simplify commit message (Chaitanya) - Remove redundant outer parenthesis (Chaitanya) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-3-mitulkumar.ajitkumar.golani@intel.com
2026-08-03drm/i915/psr: Do not enable PSR2 when CMRR is enabledMitul Golani
CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is enabled. --v2: - Restrict selective update config check (Ankit) - Commit message change --v3: - Commit changes --v4: - Add check to psr2_config_valid (Jouni) --v5: - Correct debug message --v6: - Commit message update Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260730105919.3913412-2-mitulkumar.ajitkumar.golani@intel.com
2026-08-02drm/xe/oa: Extend OAM unit hwe assignment for new dGfxAshutosh Dixit
dGfx vecs hwe's for media version 35.00 and later follow the same assignment to OAM units as vcs engines. Bspec: 77977 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patch.msgid.link/20260729230645.3052178-3-ashutosh.dixit@intel.com
2026-08-02drm/xe/mcr: Take vcs1/vecs1 into account for first media sliceAshutosh Dixit
vcs1 and vecs1 may also be present on the first media slice, so take vcs1/vecs1 also into account when determining if the first media slice is absent. Bspec: 67103, 77977 Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260729230645.3052178-2-ashutosh.dixit@intel.com
2026-08-02drm/v3d: Serialize the scheduler timeout handlersMaíra Canal
V3D exposes several independent hardware queues (BIN, RENDER, TFU and CSD) but has only a single, global reset. A timeout on any one queue therefore has to stop, reset and restart the schedulers of every other queue as well. That makes concurrent timeout handlers unsafe. `reset_lock` was never able to make them safe, as a driver-side lock can only cover the driver's &drm_sched_backend_ops.timedout_job callback. The scheduler handles the timed out job and its pending list around that callback, outside of the driver's control, so a global reset triggered by one queue can still interfere with another queue that is in the middle of handling a timeout of its own. Consequently, if a reset happens in the CSD queue while a CL-intensive application is running, the global reset stops and restarts the CL queue's scheduler while that queue is handling a timeout of its own. As drm_sched_stop() and drm_sched_start() subtract and add the credits of every job sitting on the pending list of the scheduler they are called on, and as the CL queue's handler concurrently takes its job off that same list and puts it back, the stop and the start no longer see the same set of jobs. The CL queue is left with more credits in flight than its limit: [ 327.302739] ------------[ cut here ]------------ [ 327.302744] WARNING: CPU: 2 PID: 43 at drivers/gpu/drm/scheduler/sched_main.c:102 drm_sched_run_job_work+0x238/0x4d0 [gpu_sched] [ 327.302884] CPU: 2 UID: 0 PID: 43 Comm: kworker/u16:1 Not tainted 6.18.39-v8-16k+ #3 PREEMPT [ 327.302889] Hardware name: Raspberry Pi 5 Model B Rev 1.0 (DT) [ 327.302893] Workqueue: v3d_bin drm_sched_run_job_work [gpu_sched] [ 327.302984] Call trace: [ 327.302987] drm_sched_run_job_work+0x238/0x4d0 [gpu_sched] (P) [ 327.302997] process_scheduled_works+0x180/0x3d0 [ 327.303010] worker_thread+0x268/0x3e8 [ 327.303016] kthread+0x140/0x250 [ 327.303022] ret_from_fork+0x10/0x20 [ 327.303031] ---[ end trace 0000000000000000 ]--- From that point on, the credit count of the CL queue is broken, causing a complete GPU hang and UI freeze. The DRM scheduler already provides a mechanism to serialize the timeout handlers of different schedulers: an ordered workqueue passed as drm_sched_init()'s @timeout_wq parameter. By default, each scheduler queues its timeout work on the system workqueue, which runs the handlers concurrently. Give all of the queues a shared ordered workqueue instead, as recommended by the DRM scheduler documentation for hardware that has distinct queues but resets globally. Cc: stable@vger.kernel.org # 6.15 Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Link: https://patch.msgid.link/20260728-v3d-order-global-reset-v1-1-e47be838158d@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2026-08-02drm/exynos: hdmi: take i2c adapter module referenceJohan Hovold
The i2c subsystem currently blocks during adapter deregistration whenever there are consumers holding a reference. Switch to using of_get_i2c_adapter_by_node() which also takes a reference to the adapter module so that an attempt to unload the module while in use fails gracefully instead of blocking uninterruptibly. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-08-02drm/exynos: Add error handling to drm_encoder_init()Diogo Silva
Not handling the return code on drm_encoder_init can lead to silent failure and/or a drm_encoder_cleanup on a non-initialized encoder. This patch adds error handling to the drm_encoder_init calls to prevent that from happening. Signed-off-by: Diogo Silva <diogompaissilva@gmail.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-08-02drm/exynos: Remove dependency on DRM simple helpersDiogo Silva
Simple KMS helper are deprecated since they only add an intermediate layer between drivers and the atomic modesetting. This patch removes the dependency on drm simple helpers from exynos DRM drivers. Signed-off-by: Diogo Silva <diogompaissilva@gmail.com> Dropped unnecessary blank line and reorder header definition. Signed-off-by: Inki Dae <inki.dae@samsung.com>
2026-08-01Merge tag 'drm-xe-next-2026-07-30' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next - Wait on external BO kernel fences in exec IOCTL (Brost) - General clean-up (Anas) - Documentation fix (Rafael) - Add a debugfs for pcode information (Karthik) - Free madvise VMA array on L2 flush failure (Guangshuo) - Page Table related fixes (Shuicheng, Zongyao) - Improvements GuC error handling and GuC small fixes (Sk, Zhanjun, Arvind) - Add new W/As (Daniele, Harish) - GuC paging engine support (Auld) - Add and use more KLV helpers (Michal) - Balance exec queue suspend/resume (Niranjana, Thomas) - Fix BO prefetch with CONSULT_MEM_ADVISE_PREF_LOC (Himal) - SRIOV: Disable display in admin only PF mode (Satya) - Fix writable override for CRI NVM (Sasha) - Fix VF CCS attach/detach race with in-flight BO moves (Brost) - Introduce Xe Uncorrectable Error Handling (Riana) - Fix WOPCM size for LNL+ (Daniele) - Consolidate debugfs fault injection functions (Mallesh) - Multi-queue related fixes and improvements (Niranjana, Jagmeet, Shuicheng) - Add RAS GPU health indicator (Soham) - PAT related improvements (Roper, Sanjay) - NULL deref fix on migration on VF (Satya) - i2c related fix (Raag) - Fix SVM leak and clean up xe_vm_create (Shuicheng) - Drop force_probe requirement for NVL-s (Gustavo) - Optimise TT population for DONTNEED BOs (Auld) - Add page size allocation mode control and coverage (Himal, Nareshkumar) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/amt2kDVdyBK6VEyU@intel.com
2026-08-01Merge tag 'drm-intel-next-2026-07-28' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next drm/i915 feature pull #2 for v7.3: Features and functionality: - Enable UHBR link rates on Thunderbolt tunneled links (Imre) - Reduce Xe3+ PM demand peak bandwidth for power savings (Vinod) - Add the blend mode property to all planes that support alpha blending (Chaitanya) - Enable pipe DMC error interrupts for display 30+ (Dibin) - Add KUnit tests for DP link config selection and fallback (Imre) Refactoring and cleanups: - Refactor DP link config selection and unify across use cases (Imre) - Unify i915 and xe display runtime PM calls (Jani) - Refactor BIOS framebuffer takeover (Ville) Fixes: - Fix HD audio on DP UHBR SST (Kai Vehmanen) - Fixes to xe driver BIOS framebuffer takeover (Ville) - Fix 2 pixels-per-clock CDCLK calculation to avoid underruns (Ville) - Fix incorrectly set VSC SDP Main Stream Attribute (Chaitanya) - Fix BPC and DSC selection for HDMI sinks (Alexander Kaplan) - Fix PCON max FRL rate selection (Alexander Kaplan) - Workaround Xe3P PSR2 screen corruption (Dibin) - Fix NVL A & B stepping vtotal setting (Suraj) - Fix xe DPT allocation paths (Maarten) - Prefer system memory instead of stolen for new framebuffers in xe (Maarten) - Fix transcoder mask sizes (John Harrison) - Clear stale UV/Y plane DDB entries on plane disable (Vinod) - Fix some DP AUX backlight control issues, again (Suraj) - Fix switching between HDCP 1.4 and 2.2 authentication (Suraj) - Remove unnecessary Xe2_LPD+ FBC plane width and surface size limits (Vinod) - Ensure non-zero DSB safe window for PTL+ (Ankit) - Fix bandwidth calculation to account for 16 DRAM channels (Uma) - Fix NV12 ceiling division for bigjoiner case (Vidya) DRM core changes: - Add Thunderbolt UHBR tunneling support (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/cb1b5a644d75589cbcdcc8ec8160968140426439@intel.com
2026-07-31drm/msm: detach the ARM DMA mapping before attaching our own domainDmitry Baryshkov
On ARM32 with CONFIG_ARM_DMA_USE_IOMMU, arch_setup_dma_ops() creates a dma_iommu_mapping for every IOMMU-backed device and attaches its domain to the device's IOMMU group. That domain is neither the group's default nor its blocking domain, so when msm_iommu_new() later attaches the domain the driver manages itself, __iommu_attach_group() refuses it: if (group->domain && group->domain != group->default_domain && group->domain != group->blocking_domain) return -EBUSY; Both the GPU and the display controller are hit by this on apq8064 (IFC6410), leaving the board with no GPU and no display: adreno 4300000.gpu: failed to load adreno gpu adreno 4300000.gpu: probe with driver adreno failed with error -16 mdp4 5100000.display-controller: [drm:msm_drm_kms_init] *ERROR* failed to load kms mdp4 5100000.display-controller: adev bind failed: -16 Other ARM32 DRM drivers that manage their own domains (tegra, rockchip, exynos) drop the arch mapping first. Do the same in msm_iommu_new(), which both the display and the GPU paths go through. With this the GPU and the KMS device both initialise: [drm] Initialized msm 1.13.0 for 4300000.gpu on minor 0 [drm] Initialized msm-kms 1.13.0 for 5100000.display-controller on minor 1 Assisted-by: Claude:claude-opus-5 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/743333/ Link: https://lore.kernel.org/r/20260730-fix-qcom-smmu-v2-3-18e0daf2d836@oss.qualcomm.com
2026-07-31drm/msm/dsi: Drop dev_pm_opp_set_rate(0)Konrad Dybcio
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but does not actually park the clock, making it run without the necessary power backing. Drop the explicit call to it. Every call site of ops->link_clk_disable() is followed by pm_runtime_put(), so the power vote will be rescinded if deemed safe. Fixes: 32d3e0feccfe ("drm/msm: dsi: Use OPP API to set clk/perf state") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742783/ Link: https://lore.kernel.org/r/20260728-topic-dpu_power-v1-3-e7783b859a70@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: Drop dev_pm_opp_set_rate(0)Konrad Dybcio
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but does not actually park the clock, making it run without the necessary power backing. Drop the explicit calls to it. Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742781/ Link: https://lore.kernel.org/r/20260728-topic-dpu_power-v1-2-e7783b859a70@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dpu: Drop sneaky dev_pm_opp_set_rate(0)Konrad Dybcio
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but does not actually park the clock, making it run without the necessary power backing. Prevent that from happening when _dpu_core_perf_get_core_clk_rate() returns 0. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742779/ Link: https://lore.kernel.org/r/20260728-topic-dpu_power-v1-1-e7783b859a70@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: pass panel to display enable/disable helpersYongxing Mou
Pass struct msm_dp_panel to the display enable/disable helpers to make them easier to reuse for MST stream handling. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742752/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-14-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: make bridge helpers use dp_display to allow re-useAbhinav Kumar
dp_bridge helpers take drm_bridge as an input and extract the dp_display object to be used in the dp_display module. Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742750/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-13-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: simplify link and clock disable sequenceYongxing Mou
Move the common disable steps out of the sink_count check to make the flow easier to follow. No functional change intended. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742749/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-12-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: split dp_ctrl_off() into stream and link partsAbhinav Kumar
Split dp_ctrl_off() into stream and link parts so that for MST cases we can control the link and pixel parts separately. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742746/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-11-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to itAbhinav Kumar
With MST, multiple sinks share a single DP controller, so a cached panel in msm_dp_ctrl_private can no longer represent the per-stream sink. Drop the cache and pass panel explicitly to all stream-related dp_ctrl APIs. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742745/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-10-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: re-arrange dp_display_disable() into functional partsAbhinav Kumar
dp_display_disable() handles special case of when monitor is disconnected from the dongle while the dongle stays connected thereby needing a separate function dp_ctrl_off_link_stream() for this. However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742742/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-9-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: break up dp_display_enable into two partsAbhinav Kumar
dp_display_enable() currently re-trains the link if needed and then enables the pixel clock, programs the controller to start sending the pixel stream. Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742740/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-8-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: move the pixel clock control to its own APIYongxing Mou
Enable/Disable of DP pixel clock happens in multiple code paths leading to code duplication. Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742738/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-7-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: split link setup from source paramsYongxing Mou
msm_dp_ctrl_configure_source_params() should only handle stream-related configuration. Move the link setup out of it so MST can program link and stream settings separately. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742737/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-6-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: extract MISC1_MISC0 configuration into a separate functionYongxing Mou
Refactor the MISC1_MISC0 register configuration into a standalone helper function to support MST. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742735/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-5-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31drm/msm/dp: split msm_dp_ctrl_config_ctrl() into link parts and stream partsYongxing Mou
The DP_CONFIGURATION_CTRL register contains both link-level and stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures all of them together. Separate the configuration into link parts and stream parts to support MST. Clear the stream-specific fields before OR-ing new values in the stream path to avoid bit accumulation across repeated calls. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742733/ Link: https://lore.kernel.org/r/20260728-dp_mstclean-v9-4-f7779fce10f4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>