| Age | Commit message (Collapse) | Author |
|---|
|
[WHAT]
Add KUnit tests for dm_update_mst_vcpi_slots_for_dsc(), covering an
empty commit and the writeback, non-MST and unmatched stream skips.
[HOW]
The tests build a commit holding a single connector and vary its type
and MST output port so every early-skip branch is reached without an MST
topology or a matching DC stream.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for fill_dc_plane_attributes(), covering the copy of the
plane info into the DC plane state and the scaling, pixel format and 3D
LUT rejection paths.
[HOW]
Reuse the plane info fixture and add a CRTC state complete enough for
the colour management update. A scaling factor of 1 in the plane caps
means no scaling, which matches the 1:1 geometry of the fixture.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for fill_dc_plane_info_and_addr(), covering every
graphics and video pixel format mapping, all rotations, the unsupported
format and invalid colour encoding rejections, and the z-order and
blending forwarding.
[HOW]
A linear GFX9 framebuffer is the simplest input that lets the buffer
attribute helper succeed, so the format switch can be walked without a
live display core.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_early_init(), covering the display counts of the
legacy ASICs and the DCN IP versions, a BIOS without an object header,
and an unsupported IP version.
[HOW]
Add a fake ATOM BIOS image whose master data table reports a present
entry, which is all amdgpu_atom_parse_data_header() checks here. Only IP
versions without DMUB firmware are used, so dm_init_microcode() does not
reach a firmware request.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_mode_config_init() and initialize_plane(),
covering the mode config defaults, the Hawaii preferred shadow quirk,
the DM private object state, and primary and overlay plane creation.
[HOW]
drm_atomic_private_obj_init() builds the private state through
dm_atomic_create_state(), so a current DC state is enough to exercise
it. Audio is disabled for the duration of the test so no audio component
is left registered on the mock device.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_late_init(), covering a DC without a DMCU, and
the boot time CRC init with and without a DMUB service.
[HOW]
An empty resource pool leaves the DMCU NULL and an empty link list
leaves no eDP, so the ABM configuration is skipped and only the MST
detection sweep runs. A stub reports the boot time CRC as disabled.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_sw_init() on an ASIC without a DMUB, and for the
DMUB bounding box release in dm_sw_fini().
[HOW]
An ASIC without DMUB support makes dm_dmub_sw_init() return early. The
bounding box allocation is left without a buffer object, which
amdgpu_bo_free_kernel() short-circuits.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for load_dmcu_fw(), covering the ASICs and DCN IP
versions without a DMCU, an unsupported IP version, the three Raven
revisions, and a missing firmware image.
[HOW]
No firmware is installed in the test environment, so
amdgpu_ucode_request() reports -ENODEV and the missing image is treated
as non-fatal.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
The vline0 interrupt handling in amdgpu_dm_crtc_set_vblank() sits
inside a CONFIG_DRM_AMD_SECURE_DISPLAY block. That symbol depends on
CONFIG_DRM_AMD_DC_FP, which cannot be enabled on UML because UML does
not select ARCH_HAS_KERNEL_FPU_SUPPORT, so the logic is never built by
the KUnit tests and stays uncovered.
[HOW]
Move the block into amdgpu_dm_crtc_set_vline0_irq() and build it
whenever CONFIG_DRM_AMD_SECURE_DISPLAY or the KUnit tests are enabled.
The DCN-only check becomes an early return. Behaviour of
amdgpu_dm_crtc_set_vblank() is unchanged.
Add tests for amdgpu_dm_crtc_set_vline0_irq() covering the DCE no-op
path, error propagation from amdgpu_irq_get() and the enable/disable
refcount round-trip.
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_init_power_module(), covering the skip
when no eDP is detected and the backlight parameter setup loop followed
by the allocation failure report.
[HOW]
mod_power_create() rejects a NULL DC, which walks the full parameter
setup loop without needing a live display core.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for the system aperture and GART configuration built by
mmhub_read_system_context(), covering the enabled and disabled AGP
aperture branches, the Raven2 and Renoir aperture workarounds, and the
GPUVM support flag.
[HOW]
Add struct amdgpu_dm_kunit_ops, a KUnit-only indirection table for
amdgpu_gmc_pd_addr(), which walks a live TTM buffer object back to its
device. Tests install a stub returning a fixed page directory address,
which makes the arithmetic reachable in the UML test environment. The
default table points at the existing AMDGPU function, so no test-only
wrapper is introduced.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_atomic_setup_commit() covering an empty
commit, changed color management, a modeset-only color update, and an
invalid degamma LUT.
[HOW]
Reuse the modeset fixture for active CRTC paths and attach a one-entry LUT
to exercise size validation without hardware programming.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_mod_power_update_streams() covering empty
and fast commits plus CRTC enable, replacement, and disable, and for
amdgpu_dm_mod_power_setup_streams() covering empty, modeset, and fast
updates.
[HOW]
Leave dm->power_module NULL and PSR/Replay feature bits clear so the DM
stream transition logic runs without a live power module.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_early_fini() with audio never enabled, for
dm_sw_fini() releasing the DMUB software state, for dm_oem_i2c_hw_init()
when the resource pool has no OEM device, for dm_gpureset_commit_state()
with an empty DC state, and for amdgpu_dm_emulated_link_detect() rejecting
an unknown connector signal.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_trigger_timing_sync() covering a DC without
a current state and the propagation of the force flag to every stream, and
for dm_acpi_process_phy_transition_interlock().
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for do_aquire_global_lock() covering a device without
CRTCs, a CRTC with no pending commit, and a CRTC whose commit has already
completed.
[HOW]
Pre-signal the commit completions so the waits return immediately. The
extra reference the loop takes is released again, so the commit never
reaches zero and stays test-managed.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_update_hdcp() covering a missing workqueue,
a skipped writeback connector, and an unchanged DisplayPort connector.
[HOW]
Keep content protection unchanged and provide only the sink, connector,
and CRTC state needed for the connector walk, avoiding HDCP operations.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_dump_links_and_sinks() covering a device
without DC, a DC without links, named local and remote sinks, and missing
or unnamed sinks.
[HOW]
Build lightweight DC link and sink objects so the dump walks each naming
and skip path without display hardware.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for should_reset_plane() covering the pre-DCN3.2 modeset
hack, a writeback commit, a plane moved between CRTCs, a plane outside the
context, a missing new CRTC state, a cursor mode switch, color management,
z-order, modeset, and the fast update baseline.
Also cover the cross-plane loop: cursor planes and planes on other CRTCs
are skipped, while a moved plane, source or destination size, rotation,
blend mode, alpha, colorspace, transfer function, pixel format and
modifier changes each force a reset, and a plane missing one framebuffer
is skipped.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for fill_dc_dirty_rects() covering the cursor plane
bypass, the full frame update fallbacks taken on rotation, on a
damage-unaware client, on ignored damage clips, on exceeding
DC_MAX_DIRTY_RECTS and on PSR SU in auto damage mode, the verbatim copy of
damage clips, and the MPO paths for a moved plane, a flipped plane, stable
clips and clips that overflow together with the bounding boxes.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_crtc_mem_type_changed() covering an empty
plane mask, a plane missing one of its states, framebuffers in the same
memory domain, and a framebuffer migrated between domains.
[HOW]
Back the framebuffers with fake buffer objects carrying a TTM resource, so
get_mem_type() resolves a memory domain without a live TTM device.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_update_pflip_irq_state() covering DCN, where there
is nothing to reapply, and DCE, where the current interrupt state is
reapplied to the pageflip source.
[HOW]
Add a spy for the pageflip IRQ source. amdgpu_irq_update() always
dispatches through src->funcs->set(), which needs a registered IH ring on
real hardware, so the spy records the requested type and state instead.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_arm_vblank_event() and
dm_arm_vblank_event_pre_programming() covering missing events, inactive
CRTCs, page-flip and cursor updates, and vblank reference acquisition.
[HOW]
Use one pending-event fixture. Initialize DRM vblank state only for the
pre-programming tests and release every acquired reference.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for amdgpu_dm_commit_cursors() covering an empty commit,
a non-cursor plane, and a cursor update, and for amdgpu_dm_update_cursor()
covering missing framebuffers and removal of an active stream cursor.
[HOW]
Reuse the single-plane commit fixture. The disable path uses the real
state-only DC cursor position setter without hardware programming.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for add_affected_mst_dsc_crtcs() covering an empty commit,
a writeback connector, a connector that is not behind an MST branch, a
connector bound to a different CRTC, and a disabled connector whose old
state decides which CRTC is affected.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_atomic_get_state() covering the return taken when
the caller already holds the DM state, and for dm_atomic_duplicate_state()
covering the failure path when the old private state has no DC context.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
Add KUnit tests for dm_vblank_get_counter() and dm_crtc_get_scanoutpos()
covering a CRTC whose stream is not owned by any pipe in the resource
context, and the branch that disables idle optimizations before reading
the scanout position.
[HOW]
Wire a DC context, a current DC state and a logger to the device so both
callbacks walk the resource context instead of returning early.
Assisted-by: Copilot:Claude-Opus-5 GPT-5.6-Sol
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
DML wrapper is used to bridge between DC and DML.
Put DML wrapper files in their own folder to help
distinguish the boundary between DC and DML.
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
dm_test_backlight_caps_aux_support_noop() covers the !CONFIG_ACPI
branch of amdgpu_dm_update_backlight_caps() and is wrapped in #if
!defined(CONFIG_ACPI). An ACPI build silently drops it from the
suite and never compiles it.
dm_test_backlight_caps_non_aux_sets_defaults() adds nothing: the
defaults block it asserts is already exercised by
dm_test_register_backlight_device_success().
[HOW]
Compile dm_test_backlight_caps_aux_support_noop() unconditionally and
call kunit_skip() when CONFIG_ACPI is enabled, so it is reported as
skipped instead of disappearing. Drop the redundant test and group the
remaining KUNIT_CASE entries under amdgpu_dm_update_backlight_caps().
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
The sanity check applied to the backlight caps reported by the
firmware sits inside a CONFIG_ACPI block. The UML KUnit build cannot
enable CONFIG_ACPI, so that logic is never built and stays uncovered.
[HOW]
Move the check into amdgpu_dm_validate_backlight_caps() and build it
whenever CONFIG_ACPI or the KUnit tests are enabled. Behaviour of
amdgpu_dm_update_backlight_caps() is unchanged.
Add a parameterized test for amdgpu_dm_validate_backlight_caps()
covering sane caps, a max above the 8-bit range, a negative min and a
spread narrower than AMDGPU_DM_MIN_SPREAD.
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY&HOW]
RBBMIF timeout should not be disabled to prevent register access
hang.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
Rename function and updated comments to remove internal references.
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
Hwss executors shouldn't be coupled to complex dc structs such as pipe_ctx.
[HOW]
- Use mpc function instead of hwseq extension.
- Swap pipe_ctx for tg_color struct as BLS param.
Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
- Updated switch cases to handle new link rates
- Reverted set stream attribute behaviour to DCN401 version to unblock
DSC on DCN 60
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHAT]
ASSERT() and ASSERT_CRITICAL() expand to a WARN_ON() test that falls
through, because dc_breakpoint() is a no-op unless
CONFIG_DEBUG_KERNEL_DC is set.
Static analysers read that test as proof the asserted condition can
fail, then keep walking the failing path because nothing stops it. The
assert therefore manufactures the very defect it guards against, and
Coverity reports DIVIDE_BY_ZERO defects whose entire path is the assert
itself.
[HOW]
Redefine both macros to call a declaration-only __coverity_panic__()
when the asserted condition fails, which marks the failing path as
unreachable and leaves only genuinely reachable defects.
The override is guarded by __COVERITY__, which is defined only while
the analyser captures the build, so the code emitted by a normal build
is unchanged.
Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
Integer values for
dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params
should not have the const qualifier.
This prevents using different values of the inputs when the
function is called again.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
Tno_bw_flip is a time so it should be a part of the denominator in
the bandwidth calculation.
Fix order of operation so Tno_bw_flip is properly accounted for
when calculating the lower bandwidth bound.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
Deprecate original organization in favor for the organization used by v2.
External usages no longer used so it can be removed entirely.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY&HOW]
DCN5+ supports multi-dwb per stream.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
The maximum source viewport width the ASIC can downscale from is held in
dc->debug.max_downscale_src_width and is not visible to userspace. Tests
(e.g. IGT amd_cursor_overlay scaling subtests) that downscale a plane
cannot tell whether a given source width is a genuine hardware
limitation or a driver defect, so they cannot correctly distinguish a
SKIP from a FAIL.
[HOW]
Add a read-only per-connector max_downscale_src_width debugfs file that
reports dc->debug.max_downscale_src_width, following the existing
internal_display debugfs entry. A value of 0 means no limit.
Assisted-by: Claude:opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Tony Qi <Haoming.Qi@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
Panel Replay has different index definition from other
eDP features. So we should avoid using panel_index in
pr.
[HOW]
Rename the it to pr_panel_inst
Reviewed-by: Leon Huang <leon.huang1@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY&HOW]
Not all ASIC revisions support the DAL port idle optimizations. Guard
the code with a check for ASIC rev.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
DML wrapper has dependencies on both DC and DML.
Therefore it should be in its own component instead of under the
DML2 folder.
A series of changes are required to move the files without breaking
compilation
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
Cursor SDR white level calculation is common across DCN generations
and does not require an ASIC-specific HWSS implementation.
Keeping it in the DCN10 HWSS extension duplicated generic policy
in generation-specific code and made block sequence execution
depend on mutable pipe context.
[HOW]
Move cursor SDR white level calculation into dc_hw_sequencer. Store the
calculated DPP cursor attributes in the block sequence so execution
only invokes set_optional_cursor_attributes.
Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
dcn60 uses dpp50_set_pregam_state, which reads PRE_GAM through the
dcn50_dpp_registers layout. PRE_GAM sat at a different offset in
dcn50 (based on DCN401) vs dcn60 (based on DCN42), so the cast
landed on the wrong register which causes the wrong address to be
used
[HOW]
Rebase the DPP macro inheritance so PRE_GAM shares a common offset:
DCN50 lists now inherit from DCN42, and DCN60 lists inherit from
DCN50. The dcn60 struct layout is unchanged, so PRE_GAM aligns
between the two and dpp50_set_pregam_state programs the correct
address.
Reviewed-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY/HOW]
fixpt31_32 and custom_float code is duplicated in SPL
Remove duplicated code and refer back to dc
Cleaned up swap, div64_s64
Move namespace defines to spl_namespace.h
Suggested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Previous fix converted most mpcc_id assignments in dc_hw_sequencer.c
from pipe_ctx->plane_res.hubp->inst to plane_res.mpcc_inst, but missed
the update_visual_confirm and power_on_mpc_mem_pwr paths in
hwss_build_fast_sequence(). On DCE ASICs the pipe owns no HUBP, so those
two remaining hubp->inst reads can NULL-deref.
Use mpcc_inst for the remaining two assignments, matching the rest of
the function and avoiding the NULL pointer dereference (same issue
addressed upstream by "avoid NULL hubp deref when filling mpcc_id on
DCE").
Fixes: 8e4670efd6dd ("drm/amd/display: Use mpcc_id instead of hubp instance")
Reviewed-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: James Lin <PingLei.Lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
Currently it needs to include opp.h to access custom_float structures,
which pulls in additional include files that are not necessary.
[HOW]
Move custom_float structures to custom_float.h, and include this header in
opp.h. Add only os_types.h and fixed31_32.h in custom_float.h
Suggested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
Splash screen corruption on some 8K monitors.
[HOW]
Set GPUVM min page size to 4K for DCN35/36 to use the correct DML2
calculations, avoiding the corruption path observed during splash.
Fixes: 115009d11ccf ("drm/amd/display: Add DCN35 DML2 support")
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
[WHY]
A kernel compilation warning was reported caused by upstream of DCN5/6.
[HOW]
Using plain integer as NULL pointer. Assign NULL to the
VActiveLatencyHidingMargin/VActiveLatencyHidingUs pointer members in
dml2_core_dcn5_funcs_mode_programming.c, and pass NULL for the pointer
arguments to calculate_first_second_splitting() in
dml2_pmo_dcn6_stage_optimizers.c.
Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6")
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
