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path: root/drivers/gpu/drm/amd/amdgpu
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2026-09-02drm/amdgpu/userq: use fence_val instead or rptrSunil Khatri
In function amdgpu_userq_fence_signaled rptr is a confusing variabile name as it is a fence value written by the cp in the fence address and no where related to the rptr. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amdgpu/userq: use fence_val instead or rptrSunil Khatri
In function amdgpu_userq_fence_driver_process rptr is a confusing variable name as it is a fence value written by the cp in the fence address and no where related to the rptr. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amdgpu: use underscores in TLB fence driver and timeline namesPrike Liang
Replace spaces with hyphens in amdgpu_tlb_fence_get_driver_name() and amdgpu_tlb_fence_get_timeline_name(). Returning string literals with spaces makes ftrace fence events and debugfs fence entries visually ambiguous and harder to parse using standard log analysis tools. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-28Merge tag 'drm-next-2026-08-29' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull more drm updates from Dave Airlie: "As mentioned last week, an msm pull request fell down the side of the couch or whatever the email equivalent of that is. This has the msm next stuff + the usual fixes for amd/intel. core: - use drm_warn instead of warn msm: - Bindings: - Added Shikra support - Document a840, a704, a722 - Core: - Use drm_client buffers for fbdev emulation - teardown fixes - ARM32 DMA fixup - Remove objects from evict list when re-validated - Bunch of corner case and error path fixes - DPU: - Dropped dev_pm_opp_set_rate(0) preventing burnout - Fixed SSPP offsets of Kaanapali - DP: - Dropped dev_pm_opp_set_rate(0) preventing burnout - Cleaned up core code in preparation for MST support - Fixed prepare() to let Pipewire continue in case of the unplugged cable - GPU: - Add support for a704 - Add support for a722 - HDMI: - Simplifed register access amdgpu: - eGPU fixes - Runtime PM fix - UserQ fixes - Backlight fix - Discovery sysfs fix - Reset handling fixes - Buffer func handling fix for xgmi - VCN boundary check fix - DC lut handling fixes - MES fixes - UVD fix - VCE 3 fix - Enforce isolation fix - HPD fix for VGA/LVDS - DML fix - DCN 6 fixes - DC gpu reset fix amdkfd: - Fix return value - CU occupancy for GFX 11 - CU occupancy for GFX 12/12.1 - Queue bounds checking fix - SVM fixes - CRIU bounds checking fix radeon: - iMac display fix xe: - error message cleanups - i2c global register definitions as dependency for xe/i2c fixes - Media workardound - Add CCS to gt_idle debugfs print - Page fault related fix - i2c related fixes - System Controller mailbox bit fix" * tag 'drm-next-2026-08-29' of https://gitlab.freedesktop.org/drm/kernel: (121 commits) drm/xe/sysctrl: Read mailbox phase bit from hardware drm/xe/i2c: Keep the i2c controller always enabled drm/xe/i2c: Fix the interrupt handling i2c: designware: Global register definitions drm/xe: Reject page faults from non-fault-mode scratch VMs drm/xe/xe_gt_idle: Add CCS to the powergating info print drm/xe: Do not apply WA 14025883347 to media 3503 drm/amd/display: fix dc_lock leak on GPU reset error paths drm/amd/display: Fix redundant GPUVMEnable checks in dcn6 flip schedule drm/amd/display: Fix wrong bytes-per-pixel value for dml2_422_packed_10 drm/amdkfd: guard against NULL restore_mqd in CRIU queue restore drm/amdgpu/userq: fix lock missing for userq fence error set drm/amdkfd: Fix the case that vm range is hole at svm_migrate_copy_to_vram drm/amdkfd: Fix error path at svm_migrate_copy_to_ram drm/amd/display: Log details when failing to register HPD IRQ drm/amd/display: Fix HPD consideration for VGA/LVDS connectors on DCE drm/amdgpu: clamp the isolation index for rings outside a partition drm/amdkfd: Reject zero-sized AQL queue allocations after size halving drm/amdgpu: Fix VCE 3 ring align_mask drm/kfd: Add CU occupancy support to GFX12.1 ...
2026-08-27Merge tag 'mm-stable-2026-08-26-15-22' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull more MM updates from Andrew Morton: - "mm/rmap: index MAP_PRIVATE file-backed folios by anonymous pgoff" (Lorenzo Stoakes) Index MAP_PRIVATE file-backed folios by their anonymous page offset to resolve confusion around reverse mapping for zeroed and CoW'd file-backed memory. Use this new VMA anonymous page offset tracking to eliminate index conflicts and lay the foundation for scalable CoW performance improvements. - "promote mapped executable folios after first usage for MGLRU" (Baolin Wang) Make MGLRU's protection of mapped executable file folios more reliable. Follow the classical LRU's logic, promoting mapped executable file folios after their first usage to give executable code a better chance to stay in memory and improve workload performance. - "mm: vmscan: fix node reclaim ignoring swappiness parameter" (Ridong Chen) Fix per-node proactive reclaim interface's ignoring the swappiness parameter when CONFIG_MEMCG is disabled by consolidating sc_swappiness() into a single function that checks proactive_swappiness regardless of kernel configuration. - "mm/vmscan: reduce lru_lock contention via vmstat-derived scan-balance cost" (Usama Arif) Reduce lru_lock contention in the reclaim path by deriving scan-balance costs from vmstat counters rather than lock-acquired producer updates. Read and decay these cost signals on the reclaim side under a dedicated per-lruvec lock, reducing total LRU lock wait time by over 60% without impacting scan throughput. - "zram: fix zram issues reported by sashiko" (Sergey Senozhatsky) Fix two low-risk zram bugs which Sashiko spotted in drive-by review. - "Honor XA_FLAGS_ACCOUNT in xas_split_alloc() and charge to folio's memcg" (Zi Yan) Fix xas_split_alloc() by enabling target folio memcg charging during splits and adding the missing __GFP_ACCOUNT flag for proper XArray node memory accounting. - "selftests/mm: use pattern matching in .gitignore" (Pratyush Mallick) Replace hardcoded binary names in selftests/mm/.gitignore with a generic pattern-matching rule to automatically ignore generated test files and avoid manual updates when adding new tests. - "mm/page_ext: remove pgdat_page_ext_init()" (Sang-Heon Jeon) Make the incompatibility between FLATMEM and NUMA explicit in mm/Kconfig and remove the unused pgdat_page_ext_init() function. - "zram: fix zstd error paths and add parameter validation" (Haoqin Huang) Clean up zram compression backends by removing redundant error cleanup, adding parameter and dictionary validation, auto-prefixing algorithm error logs, and resetting parameters prior to reinitialization. - "zram: fix stale scan bounds after reinitialization" (Longlong Xia) Prevent out-of-bounds slot accesses during concurrent zram resets by moving table scan bound calculations under dev_lock in writeback_store() and read_block_state(). - "add anon mTHP collapse test cases" (Baolin Wang) Extend selftests helper functions to support arbitrary page orders and add new test cases and options for mTHP collapse in khugepaged. - "selftests/mm: Handle unsupported and transient test conditions" (Muhammad Usama Anjum) Update MM selftests to report a SKIP status instead of a failure when required kernel or filesystem features are unsupported, while adding retry logic for transient page migration errors. - "mm/zswap: Fixes and improves the zswap shrink" (Hao Jia) Fix the missing zswap global shrinker when CONFIG_MEMCG is disabled and extend shrink_memcg() to support batch writeback for improved writeback efficiency. - "alloc_tag: introduce IOCTL-based filtering for MAP" (Suren Baghdasaryan) Introduce an IOCTL-based binary interface for memory allocation profiling that enables kernel-side filtering before per-CPU counter aggregation. This eliminates the text-parsing overhead of /proc/allocinfo and provides up to a 20x speedup by transferring only filtered allocation data to userspace. - "better block swap batching and a different take on swap_ops v5" (Christoph Hellwig) Refactor block swap I/O to use swap_iocb for batching instead of single-bio requests and rebase the swap_ops interface, achieving faster swap throughput during kernel builds. - "mm: kmemleak: reduce transient false positives by confirming leaks" (Catalin Marinas) Reduce false-positive kmemleak reports by combining two kmemleak enhancements that add a second confirmation scan and a configurable minimum unreferenced scan count module parameter. - "mm: kmemleak: default min_unref_scans to 2 for verbose kernels" (Breno Leitao) Auto-scanning kernels can generate false-positive memory leak reports on single scans, so this patch defaults min_unref_scans to 2 when CONFIG_DEBUG_KMEMLEAK_VERBOSE is enabled to require a second confirming scan. - "swap_ops updates" (Christoph Hellwig) Batching I/O for synchronous swap devices causes performance regressions and filesystem-based swap suffers from double-indirection overhead. This series resolves both issues by reintroducing per-folio writes for synchronous swap and allowing filesystems to directly export their own swap_ops. - "mm/khugepaged: several cleanups" (Nico Pache) khugepaged accumulated redundant state-checking patterns and outdated comments following mTHP integration. Introduce dedicated helpers for PTE validation and event counting while refreshing the internal documentation. - "maple_tree: lock checking and clean ups" (Liam Howlett) Syzbot reports incorrectly blame memory management exit paths for locking bugs, maple tree erase operations risk allocation failures without gfp flags and internal documentation lacks clarity. Improve lock error detection, update docs, fix race and allocation edge cases and optimize erase allocations using a fallback to GFP_KERNEL | GFP_NOFAIL. * tag 'mm-stable-2026-08-26-15-22' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: (172 commits) selftests/proc: make proc-maps-race work with READ_IMPLIES_EXEC memcg: move LRU size accounting on reparenting instead of copying it mm/vmscan: fix comment logic in balance_pgdat maple_tree: add helper mas_make_walkable() maple_tree: avoid extra gap calculation maple_tree: fix argument name in header maple_tree: change two GFP flags in tests maple_tree: document erase and allocations better maple_tree: avoid mas_erase() and mtree_erase() failures maple_tree: document that erase may use GFP_KERNEL for allocations maple_tree: catch race in mas_alloc_cyclic() maple_tree: add bulk parent set helper maple_tree: micro optimisation of mas_wr_store_type() maple_tree: optimise mas_wr_node_store() when not in rcu mode maple_tree: use prefetched value in mas_wr_store_type() maple_tree: clarify comments on mas_nomem() maple_tree: drop MAPLE_ALLOC_SLOTS maple_tree: drop dead code from mas_extend_spanning_null() maple_tree: documentation fix maple_tree: add write lock checking with lockdep sequence numbers ...
2026-08-25drm/amdgpu: correct mcm_addr_lut value for gc v12_1Likun Gao
Correct GFX_IMU_MCM_ADDR_LUT_PF register value to suit for xcc harvest situation. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jinzhou Su <jinzhou.su@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: update mcm_addr_lut data for imu v12_1Likun Gao
Support for partition mode to program MCM_ADDR_LUT. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Init mcm_addr look up tableHawking Zhang
Encode mcm address look up table in SPX mode as a temp solution. v2: fill in when interface is ready (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: update mcm_addr_lut data for imu v12_1Likun Gao
Support for partition mode to program MCM_ADDR_LUT. v2: clean up (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Skip showing available NPS modesLijo Lazar
Dynamic memory partition switch is not supported on CPU-GPU xgmi connected configurations. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: skip DPX mode for unsupported GC partsMangesh Gadre
DPX is unsupported on GC 9.4.3/9.4.4/9.5.0 skip these 6-XCC parts,so do not advertise it. Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add DPX mode for 6-XCC configurationMangesh Gadre
Add DPX to the 6-XCC supported mode mask This allows DPX to be advertised and selected Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add NPS2 memory cap for soc v1.0 DPX modeLe Ma
DPX currently advertises only NPS1 as a compatible memory partition mode in soc_v1_0_get_xcp_res_info(). As a result, supported_nps_configs and amd-smi partition --accelerator report NPS1 for the DPX profile even when the device supports both NPS1 and NPS2. Include NPS2 in the DPX compatible NPS mask so the reported profile capabilities match the supported memory partition modes. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: free memory partition info on gmc v12 sw_finiLe Ma
Reset the partition count and free the buffer on gmc v12 sw_fini during driver unload. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add memory partition sysfs init/fini for GC 12.1.0Le Ma
Add the nps sysfs node for GC 12.1.0 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: init NPS supported modes for GC 12.1.0Le Ma
Add nps supported modes init for gc 12.1.0 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Init soc_v1_0 rev_id from IP discovery die_idHoratio Zhang
Software components need to detect die revisions in order to apply the correct software workarounds. During system boot, ASP firmware reads the IDCODE values from the MID, AID and XCD fuses and encodes the die revision into die_info[0].die_id in the IP discovery blob. v2: Default die_rev_id to 0 and warn instead of failing probe when IP discovery does not provide a die rev id. v3: Update names for external_rev_id enumerators. Signed-off-by: Horatio Zhang <hongkun.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: handle LSDMA instance and harvest information from ip discoveryLe Ma
Track discovered LSDMA instances in inst_mask and clear harvested instances when processing the harvest table. Report the harvest state through IP discovery sysfs for LSDMA v7.1.0. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: handle MMHUB harvest information from ip discoveryLe Ma
Clear harvested MMHUB instances from mmhub.inst_mask when processing the harvest table. Report the harvest state through IP discovery sysfs for MMHUB v4.2.0. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu/discovery: skip MEM_RESERVED_INFO on unsupported ASICsFeifei Xu
Some ASICs' MEM_RESERVED_INFO table_entry may carry non-zero garbage, causing signature check failed thus probe fail. Move signature check in amdgpu_discovery_get_mem_reserved_info_table(), returning -ENOENT when invalid so the table is skipped. v1->v2: Add discovery binary header check before populate the mem_reserved_info table. (Lijo) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Candice Li <candice.li@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add mem_reserved_info sysfs attributeFeifei Xu
Expose the cached MEM_RESERVED_INFO discovery table via a per-device sysfs file: /sys/class/drm/cardX/device/mem_reserved_info The file is read-only and dumps every region as: list_num=<N> [<i>] id=<id> (<name>) size=0x<size> start=0x<start> Only created when the table was successfully resolved at discovery init time. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_dump_mem_reserved_info_tableFeifei Xu
Walk the cached MEM_RESERVED_INFO table once at discovery init time and log every entry (region id, symbolic name, size, start). Add for debugging purpose. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: query the reserved info with get_fw_reserved_infoFeifei Xu
Extend amdgpu_ttm_init_fw_resv_region() to honour the ->get_fw_reserved_info(). Previously the FW carveout was hardcoded and placed at the top of VRAM (real_vram_size - reserve_size): - a hard-coded 144/256 MB for GC 12.1.0; - or DISCOVERY_TMR_OFFSET fallback. The hard-coded GC 12.1.0 path is replaced by ->get_fw_reserved_info(), which returns a (size, offset_within_VRAM) pair derived from the MASTER_DIE_UMF_REGION embedded in IP discovery, and falls back only when the discovery region is missing or invalid. v1->v2: Remove !adev->bios check, and call the get_fw_reserved_info interface when it is available. (suggested by Hawking) Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: set reserve_tmr in amdgpu_discovery_get_tmr_infoFeifei Xu
If reading mmDRIVER_SCRATCH_2 returns non-zero, discovery.reserve_tmr is set to true and driver need reserve tmr for firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add get_fw_reserved_info implementationFeifei Xu
Add asic specific callback ->get_fw_reserved_info() that returns the firmware/UMF VRAM carveout as a (size, offset_within_VRAM) pair, and provide the soc v1.0 implementation. Query MASTER_DIE_UMF_REGION_ID from the discovery MEM_RESERVED_INFO table for the carveout size/start. SPECIFIC_PURPOSE_REGION_ID is used to resolve the VRAM base in multi-die layouts where VRAM may not start at the default base. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_get_mem_reserved_region_by_idFeifei Xu
Add a lookup helper to pass a MEM_RESERVED_REGION_ID and receive the region's start address and size. A static amdgpu_discovery_mem_reserved_region_name() helper is also introduced so debug output can refer to regions by symbolic name rather than raw IDs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_get_mem_reserved_info_tableFeifei Xu
Add interface to query the optional MEM_RESERVED_INFO table: - introduce amdgpu_discovery_get_mem_reserved_info_table() which resolves the table from the discovery binary and caches the pointer in adev->discovery.mem_reserved_table so subsequent lookups are cheap; - invoke it once at init time. Missing/invalid table is non-fatal. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add NPS_INFO case to amdgpu_discovery_table_checkFeifei Xu
Add a NPS_INFO case with check_table=false to skip annoying "invalid ip discovery table id" error. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add amdgpu_discovery_log_bad_signature helperFeifei Xu
Add a helper that prints the actual vs expected signature for debugging purpose. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: enable RAS on psp v15_0_8Candice Li
Enable psp v15_0_8 RAS support. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add PSP v15.0.8 interrupt handlerLijo Lazar
Register and add interrupt handler in PSP v15.0.8. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add psp interrupt handlingLijo Lazar
Add interrupt manager for handling psp interrupts and callbacks to enable/disable psp interrupts. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/amdgpu: Allow reset init for smu_v15_0_8Asad Kamal
Trigger reset init and fini for smu_v15_0_8 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/amdgpu: Add soc_v1_0 reset handlerAsad Kamal
Add soc_v1_0 reset handler for mode2 reset v2: Remove XGMI parallel reset dispatch and xgmi_update_topology() call, reset on soc_v1_0 is per-device only. (Lijo) v3: Remove ras as will be plugged later as separate ip. Remove vcn from ip mask as vcn not part of reset sequence yet (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use 100M as refclock for SOCv1.0Lijo Lazar
When VBIOS is not available, fallback to use 100M for refclock value. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: add get_rom_offset callback for NBIO 6.3.2Le Ma
Add the get_rom_offset callback to retrieve the VBIOS ROM offset from REGS_ROM_OFFSET_CTRL for vbios imaging fetching from spirom. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Enable translate further for gc v12_1 v3Hawking Zhang
Enable translate further for gc v12_1 to resolve the tlb reach issue v2: ensure PTE.P is set to 1 for leaf PTE v3: Do not clear the P bit when it has been set on a PDB0 entry by the common VM update code Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Horatio Zhang <hongkun.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: recompute the dw estimate after allocating a new VM update jobYuBiao Wang
amdgpu_vm_sdma_update() keeps the number of free dwords of the current job in a local variable. When the job runs out of room it is committed and a new one is allocated, but that local variable is not refreshed and still describes the job which was just submitted. The stale value is then used to decide how many PTEs fit into the new job. If it happens to be copy_pte_num_dw + 7, or one more than that, the result is zero. copy_pte() encodes the transfer size as count * 8 - 1, so a count of zero asks the engine for a 1GB copy starting inside the IB pool. That runs off the end of the pool, faults on the first unmapped GART page above it and hangs the ring. Re-initialize the estimate from the newly allocated job, which is empty and therefore has its full budget available. Cc: stable@vger.kernel.org Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Report vm fault status HI32 when avaialbleHawking Zhang
VM fault status is 64 bits on gfxhub v12_1 and mmhub v4_2, with fields such as FED located in the upper status register. Add an optional HI32 fault status callback to help identify FED status on gfxhub v12_1 and mmhub v4_2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Horatio Zhang <hongkun.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use global addr for mmhub v4_2 reg accessHawking Zhang
Use global SMN addresses for MMHUB v4_2_0 register access across all instances. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Drop BUG_ON in PDE address verification for GFX 12.1Mukul Joshi
Update the address mask to support 52-bits addresses when validating the PDE addresses for GFX 12.1. Currently the address mask was incorrect and only permitted 48-bits addresses. Additionally, drop the BUG_ON() and replace it with code to reset the invalid address and valid bit if the address verification fails. This should help generate a page fault instead of crashing the kernel. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: clean up vm flush func for gc v12_1Likun Gao
Clean up gfx_v12_1_ring_emit_vm_flush function, since PFP_SYNC_ME cmd not support on gc v12_1, and it does not have gfx ring. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd: force remote MTYPE_NC on GFX12.1 mtype_local=0Alex Sierra
Work around this in both the amdgpu GMC and KFD SVM paths by explicitly selecting MTYPE_NC for remote memory when amdgpu_mtype_local is 0. Remove this once rev_id-based AID detection is reliable. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25Revert "drm/amdgpu: Set default xnack mode for gfx_v12.1 A0/B0"Alex Sierra
This reverts commit bfeb7b28e9f8c5d16ab00b60b42559791b16a12c. Revert the rev 0x1 (B0) special case for IP_VERSION(12, 1, 0) that forced noretry_default off. Align GFX12.1.0 with the GC >= 10.3.0 noretry default. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Update no-retry PTE flags for GFX12Mukul Joshi
The current combination of PTE flags to translate a retry fault into a no-retry fault is not valid for GFX12. Use a valid no-retry PTE flags combination that works for GFX 12. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use mmhub inst_mask for gmc v12_1 vmhub setupHawking Zhang
gmc v12_1 currently derives the number of mmhub vmhubs from the aid_mask when populating vmhubs_mask. This breaks when mmhub is represented by mid and mmhub inst_mask does not match the aid_mask. Iterate over adev->mmhub.inst_mask instead so vmhubs_mask reflects the discovered mmhub instances. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use discovered mmhub inst_mask for v4_2_0Hawking Zhang
mmhub v4_2_0 used adev->aid_mask as the mid_mask when programming MMHUB instances. That assumption is not valid for products with more AIDs than MIDs. Track discovered MMHUB instances in mmhub.inst_mask and use that mask for mmhub v4_2_0 programming paths. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Fix GMC v12.1.0 MID1 page fault vmhub selectionPhilip Yang
For GMC v12.1.0, the IH cookie NodeID spacing is 8 (MID0=0x0, MID1=0x8), not 4. The wrong divisor caused NPA page faults (node_id=8) to select mmhub2 instead of the correct mmhub1. Fix the divisor from 4 to 8, and add a comment documenting the NodeID to DIE mapping for reference. Warn once if page fault from the vmhub but vmhub print fault status function not initialized because not all hubs are initialized. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Fix MES wb status pointer overwriting adjacent wb slotPhilip Yang
status_ptr was declared as u64 * but the WB allocation is only one u32. Writing through a u64 * pointer zeroed 8 bytes, corrupting the adjacent WB slot. Fix by using u32 * to match the actual allocation size. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: move tlb invalidation to mes sched pipeShaoyun Liu
The heavy weight shootdown need special handling in MES sched pipe Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>