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path: root/drivers/gpu/drm/amd/amdgpu
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2026-10-01drm/amdgpu/mes12: gate gfx pipe reset on PER_PIPEJesse Zhang
Replace the disabled pipe-reset stub with the shared PER_PIPE capability check, so GFX MMIO pipe reset follows gfx_supported_reset. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/mes11: gate gfx pipe reset on PER_PIPEJesse Zhang
Replace the disabled pipe-reset stub with the shared PER_PIPE capability check, so GFX MMIO pipe reset follows gfx_supported_reset. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/userq: preserve kernel rings during gfx pipe resetJesse Zhang
Route GFX user queue resets through amdgpu_gfx_reset_mes_gfx() when HQD detection and PER_PIPE are available, preserving collateral kernel rings across a pipe reset. If the HQD cannot be located, use MES packet reset and protect kernel rings on all GFX pipes. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/userq: fix reading the WPTR at a non-zero BO offsetJesse Zhang
The user queue UAPI permits the WPTR at any 8-byte aligned offset within a BO. amdgpu_userq_fence_read_wptr() locates the mapping containing the WPTR address, but amdgpu_bo_kmap() returns the start of the BO, so the code read the first u64 regardless of the WPTR offset. USERQ_SIGNAL uses this value as the exported fence seqno, so a wrong read makes the fence signal early (or never), breaking dependency synchronization. Translate the WPTR GPU address to a byte offset within the BO, accounting for the VA mapping start and the mapping's BO offset, before reading it. Fixes: a292fdecd728 ("drm/amdgpu: Implement userqueue signal/wait IOCTL") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gmc12: properly pass flush_type to gmc_v12_0_flush_vm_hub()Alex Deucher
In gmc_v12_0_flush_gpu_tlb(), flush_type was not properly passed to gmc_v12_0_flush_vm_hub(). This only affected the MMIO path. In most cases the flush would go through MES. Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Fix BO reference leak in UALink export error pathMukul Joshi
amdgpu_ualink_export_handle() takes an explicit amdgpu_bo_ref() before building the exporter node, and the out: label only drops the reference from drm_gem_object_lookup(). The xarray insert failure path unrefs the BO, but the drm_gem_prime_handle_to_dmabuf() failure path does not. Userspace can hit that path at will, for example by exhausting its file descriptor table so the dmabuf export returns -EMFILE, leaking a BO reference and its pinned VRAM on every attempt. Fixes: c67cb19811ec ("drm/amdgpu: Implement UALink handle export") Reported-by: Sashiko-bot <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1 Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx: preserve collateral rings during gfx pipe resetJesse Zhang
Route kernel GFX resets through amdgpu_gfx_reset_mes_gfx() when PER_PIPE is supported, so collateral kernel rings are preserved across a pipe reset. Keep the existing queue reset path otherwise. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Reject UALink handle ioctl on devices without UALinkMukul Joshi
amdgpu_gem_ualink_handle_ioctl() dereferences adev->ualink.info before validating it, but that structure is only allocated when the UALink IP block is present, which is currently added only for GFX 12.1 only. The ioctl is registered for every amdgpu device with DRM_RENDER_ALLOW, so on any other ASIC a render node user can oops the kernel with a single call. Return -EOPNOTSUPP when the UALink software state is absent. Fixes: 15d1c306d829 ("drm/amdgpu: Add ioctl infra for exporting/importing UALink handles") Reported-by: Sashiko-bot <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1 Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: implement workaround for sdma dcc corruptionPierre-Eric Pelloux-Prayer
For unknown reasons, on gfx12 using multiple entities can causes random corruption of BOs with DCC. This workaround seems to prevent the issue until the root cause is understood and fixed. Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5663 Fixes: 3a6f6eeb3db5 ("drm/amdgpu: give ttm entities access to all the sdma scheds") Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Delete unimplemented GMC v9 soft_reset() codeTimur Kristóf
The soft_reset() function for GMC (memory controller) block of Vega has never been implemented, and there are no plans to implement it. Let's delete this function, it doesn't do anything and also isn't called from anywhere. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Delete GMC v6-v7 soft_reset() codeTimur Kristóf
Note that the soft reset code for GMC v6-v7 was never called from anywhere, so there is no loss of functionality from this commit. The implementation looks plausible but it was never enabled or tested, and unlikely to be useful. We should only reset the memory controller during ASIC reset and otherwise leave it alone. Resetting the memory controller can break everything and risks losing the contents of VRAM (it's unclear if VRAM is lost or not, but it's likely). Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx: add a gfx ME pipe reset capability helperJesse Zhang
Use gfx_supported_reset's PER_PIPE bit to report GFX pipe reset support through a shared helper. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: specify cwsr_enable usage docEric Huang
to prevent misunderstanding in cwsr off case. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0 supportHawking Zhang
Add initial implemenation for the new generation of mmhub Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: skip vpe dpm enable if dpm_enabled flag is falseLin Cao
amdgpu_dpm_enable_vpe() should be skipped if dpm_enabled is false Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Allocate VPE cmdbuf from VRAMLin Cao
PSP should not accept a GART VA directly from VF Add logical to allocate VPE cmdbuf from VRAM Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.1 supportCaden Chien
This initializes VPE IP version 3.0.1 Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.0 supportCaden Chien
This patch adds support for vpe v3.0.0 with new structs and ip functions Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/psp: wait for TOS ready on all AIDs in v15_0_3 ring createEmily Deng
When aid_mask is set, poll MP0 C2PMSG_64 on each AID instance before creating the PSP GFX command ring. Single-die paths are unchanged. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add VPE FW list to PSP_15_0_3 under SRIOVLin Cao
Add VPE FW list including VPE_CTX and VPE_CTL Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add GFX FW list to PSP_15_0_3 under SRIOVLin Cao
[Why] Under SRIOV VF, GFX firmware are required to loaded. [How] Add GFX FW list. FW contains: PFP ucode, PFP data P0-P1 ME ucode, ME data P0-P1 MEC ucode, MEC data P0-P7 MES SCH ucode and data MES KIQ ucode and data Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add new MEC2 firmware loading frameworkLin Cao
Add ucode loading support for MEC pipe stacks P4-P7: - add GFX_FW_TYPE_RS64_MEC_P4..P7 firmware types - add AMDGPU_UCODE_ID_CP_RS64_MEC_P4..P7 ucode ids - handle P4-P7 in ucode name/init, psp fw type Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Yiqing Yao <yiqing.yao@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: support MP5 in firmware info queriesYang Wang
Handle AMDGPU_INFO_FW_MP5 in the firmware query path and report the MP5 firmware version in the debugfs firmware_info output. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: expose MP5 firmware version in sysfsYang Wang
Add an mp5_fw_version attribute to the fw_version sysfs group, so userspace can read the MP5 firmware version. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add infrastructrure for handling mp5 firmwareFrank Min
Add framework for MP5 firmware. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add ta loading in psp v15_0_3Gangliang Xie
add ta loading in psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix ASP 15.0.3 runtime DB offsetYang Wang
ASP 15.0.3 stores the PSP runtime database at a fixed 64KB offset from the IP discovery table, not at the legacy offset from the end of VRAM. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add firmware type retrieval in PSP v15.0.3Frank Min
Add firmware type retrieval in PSP v15.0.3 to adapt psp fw updates Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add support for PSP version 15.0.3Frank Min
Add support for PSP version 15.0.3 v2: fix psp 15.0.3 C2P message reg access issue Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add support for lsdma v8Likun Gao
Add support for LSDMA v8 v2: fix wait_pio_status() per Philip's comments. Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add hdp v8 ip blockFrank Min
add hdp v8 ip block Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add smuio v15_0_3 supportHawking Zhang
Add initial implementation for the new generation of smuio v2: squash in clock counter changes Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fall back to RCC_HW_DEBUG for VF frame buffer sizeZhenGuo Yin
On some SR-IOV VFs RCC_CONFIG_MEMSIZE reads back 0. Fall back to RCC_HW_DEBUG for the frame buffer size in the nbif get_memsize() callback and in the early-init paths that read the register directly. Only VFs that read back 0 are affected. Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com> Reviewed-by: Frank Min <frank.min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add nbif v7_10 supportHawking Zhang
Add initial implementation for the new generation of nbif v2: squash in HDP, VPE, RLC/IH, SDMA fixes Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/discovery: Add ih v8_0 ip blockHawking Zhang
Add ih v8_0 ip block Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add ih v8_0 supportHawking Zhang
Add initial implementation for the new generation of ih v2: squash in flood control fix Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add soc v2_0 ih client id tableHawking Zhang
To acommandate the specific ih client for soc v2_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix ip discovery table validationLin Cao
Fix ip discovery table_check, get_mall_info, and get_vcn_info to guard on both offset and size being non-zero before parsing. Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix atomics on DF 5.0.2Eric Huang
DF 5.0.2 needs to program DF config register as DF 4.15.x, so share the functions, they have the same register layout. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: David Belanger <david.belanger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add gc_info_v1_4 table supportLikun Gao
Initialize amdgpu_gfx_config using values from gc_info_v1_4. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: update FIRMWARE ID for soc24Frank Min
Update firmware ID for SOC24 to support more firmware. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add debug info for psp ip key mgr ucodeFrank Min
Add debug info for psp ip key mgr ucode. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add GDDR7 vram nameFrank Min
Add GDDR7 vram name. Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: use pm_runtime_resume_and_get amdgpu_gem_create_ioctlPierre-Eric Pelloux-Prayer
This ioctl might trigger GPU work through ttm so make sure the GPU is awake. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Co-developed-by: Shahyan Soltani <shahyan.soltani@amd.com> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx: add a shared gfx pipe reset helperJesse Zhang
Serialize GFX recovery with mec.reset_mutex and attempt MES suspend before locating a user HQD. Back up collateral kernel rings before reset, then resume MES before testing and replaying rebuilt rings. Allow reset to proceed if suspend fails. Always attempt resume, report reset or resume errors, and leave schedulers stopped on failure. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: factor out the MES user queue reset bodyJesse Zhang
Extract mes_userq_reset_hw() for reuse by GFX recovery. Keep reset and MES queue removal together, marking the queue HUNG only after both operations succeed. The existing reset entry point uses the same helper. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx11: set KMD_QUEUE for kernel gfx queuesJesse Zhang
Set KMD_QUEUE in the GFX MQD and kernel ring control registers so CP preserves kernel IB VMIDs instead of replacing them with the queue VMID. Use prop->kernel_queue to distinguish kernel and user MQDs. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx12: set KMD_QUEUE for kernel gfx queuesJesse Zhang
Set KMD_QUEUE in the GFX MQD and kernel ring control registers so CP preserves kernel IB VMIDs instead of replacing them with the queue VMID. Use prop->kernel_queue to distinguish kernel and user MQDs. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/mes12: read the gfx user queue VMID for MMIO resetJesse Zhang
Read the MES-assigned VMID from CP_GFX_HQD_VMID under srbm_mutex when resetting a GFX user queue over MMIO. Kernel queues keep the IB VMID supplied by the caller. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/mes11: read the gfx user queue VMID for MMIO resetJesse Zhang
Read the MES-assigned VMID from CP_GFX_HQD_VMID under srbm_mutex when resetting a GFX user queue over MMIO. Kernel queues keep the IB VMID supplied by the caller. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>