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2026-10-13clk: qcom: dispcc-sm8250: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-10-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm7150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-9-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm6115: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-8-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sm4450: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-7-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sc8280xp: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Share the CBCR data between the two display controller descriptors. The XO branch is now enabled by the common probe before clock registration. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-6-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: dispcc-sc7280: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-5-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sm8150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-4-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sm7150: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-3-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sc8280xp: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-2-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: camcc-sa8775p: Use common probe handling for always-on clocksAbel Vesa
Describe the always-on branches in a critical_cbcrs array and reference it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these branches instead of programming them directly in the driver's probe. Keep separate CBCR arrays for SA8775P and QCS8300 to preserve their different CAMNOC XO, GDSC and sleep clock register offsets. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-1-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Clear force enable after rate failureKonrad Dybcio
Shared RCG rate changes assert force-enable before programming the new configuration. If programming fails, the function returns without clearing force-enable, leaving the root running while CCF can release temporary parent and resource references. Attempt to clear force-enable on the configuration error path before returning the original programming error. This restores the same cleanup performed after a successful configuration while preserving the primary failure for callers. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-3-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Propagate force-enable status errorsKonrad Dybcio
clk_rcg2_is_enabled() returns either a hardware status or a negative regmap error. The force-enable polling loop treats every nonzero return as an enabled clock, so a failed status read is incorrectly reported as success and clock reconfiguration can continue with unknown hardware state. Check for negative returns before testing the enabled status and propagate the read error to the caller. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-2-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rcg2: Initialize shared floor clock stateKonrad Dybcio
Shared floor RCGs use the cached parked_cfg whenever CCF considers the clock disabled. Unlike the other shared RCG variants, their ops do not initialize that cache, leaving it zeroed until the first disable or rate change. This can make registration report an undivided XO configuration instead of the boot-programmed parent and divider. Initialize parked_cfg from CFG_REG without parking or otherwise changing the hardware. Propagate read failures so a clock with unknown initial state is not registered. Fixes: aec8c0e28ce4 ("clk: qcom: rcg2: add clk_rcg2_shared_floor_ops") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-qc_clk_fixes-v1-1-5531cb00514b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-msm8960: Configure PLL15 only on APQ8064Abel Vesa
PLL15 is specific to APQ8064, but the shared probe function configures it unconditionally, including on MSM8960. Its configuration registers at offsets 0x33c through 0x348 exceed the MSM8960 regmap maximum of 0x334, so regmap rejects these accesses. The PLL configuration helper ignores the errors and probe continues. Only configure PLL15 when the selected descriptor is for APQ8064, matching the existing variant check for the GFX3D clock adjustments. Fixes: e216ce60a9e0 ("clk: qcom: Add support for APQ8064 multimedia clocks") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-msm8960-fix-pll15-config-v1-1-11fae0be111d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-sdm660: Fix MDSS AHB clock HWCG register offsetAbel Vesa
The MDSS AHB clock HWCG bit resides in the same register as the branch enable and halt status bits, at offset 0x2308. The current HWCG register offset of 0x8a004 exceeds the regmap maximum of 0x40000, so regmap rejects the read in clk_branch_in_hwcg_mode(). Since the read error is ignored, the helper uses an uninitialized value to decide whether to skip the halt status check. Correct the HWCG register offset so the helper reads the actual hardware clock gating state. Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-sdm660-fix-mdss-ahb-hwcg-offset-v1-1-30dcf09d907c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: mmcc-msm8996: Fix FD AHB clock register offsetAbel Vesa
The FD AHB clock branch register is at offset 0x3b74, not 0x3ba74. The incorrect offset exceeds the regmap maximum of 0xb008, so regmap rejects accesses to it and the clock cannot be enabled. Correct both the enable and halt register offsets so the driver can enable the branch and check its status. Assisted-by: LLM Fixes: c252659770db ("clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-mmcc-msm8996-fix-fd-ahb-offset-v1-1-a575e1b9112c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-ipq5424: Fix TME reset register offsetsAbel Vesa
The GCC_TME_BCR and GCC_TME_SEC_BUS_BCR offsets exceed the regmap maximum of 0x3f024. Regmap therefore rejects accesses to both registers, leaving the resets ineffective while the reset operations report success. The offsets appear to contain typographical errors. Use 0x10000 for GCC_TME_BCR, matching the offset used on IPQ9574 and the surrounding register layout. Use 0x1a030 for GCC_TME_SEC_BUS_BCR, placing it in the same register block as GCC_SEC_CTRL_BCR at 0x1a000. Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC") Assisted-by: LLM Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260916-clk-qcom-gcc-ipq5424-fix-tme-bcrs-offsets-v1-1-0fa10674908a@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLKKonrad Dybcio
These clocks are PHY-sourced and their halt bits seem not to update reliably. Ignore it to prevent spurious warnings. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-topic-hamoa_clk_usb4-v1-1-5d8d5225b598@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-glymur: Use clk_regmap_phy_mux_ops for GCC UFS muxesJagadeesh Kona
Use clk_regmap_phy_mux_ops for GCC UFS muxes so these muxes are automatically switched to UFS external symbol clocks during enable and safely parked at XO clk during disable. Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-glymur-ufs-clk-changes-v2-2-d0aa1c60c269@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rpmhcc: Add LNBB clocks support for GlymurJagadeesh Kona
Add support for rpmh LN_BB_CLK2 and LN_BB_CLK3 clocks on Qualcomm Glymur platform. Fixes: ebcb9db98bda ("clk: qcom: rpmh: Add support for Glymur rpmh clocks") Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-glymur-ufs-clk-changes-v2-1-d0aa1c60c269@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Assign .num before accessing .hwsAamir Ahmed
hw_data->hws[] is annotated with __counted_by(num), so hw_data->num must hold the element count before the array is accessed. ipq_cmn_pll_register_clks() assigns it only after storing the fixed rate output clocks and the CMN PLL, and the unwind loop under unregister_fixed_clk reads .hws[] with .num still zero. Both are out-of-bounds accesses under CONFIG_UBSAN_BOUNDS. Move the assignment to right after the allocation. Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Aamir Ahmed <elb12345@hotmail.co.uk> Reviewed-by: Luo Jie <jie.luo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/AS8P251MB000187BDFAD98A21F4C356E9C8BD2@AS8P251MB0001.EURP251.PROD.OUTLOOK.COM Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210Luo Jie
Add the IPQ5210 output clock array and the device match table entry, wiring together all the infrastructure added in the previous patches. The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-10-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocksLuo Jie
Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed rate with enable/disable/is_enabled gate control through the shared regmap for CMN_PLL_OUTPUT_RELATED_1. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). Parent the gated fixed-rate output clocks on `cmn_pll_div2` to reflect the CMN PLL clock hierarchy. Their rates remain fixed constants returned by `clk_fixed_gate_recalc_rate()`. Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-9-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock supportLuo Jie
The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that provides the raw reference clock to the SoC-integrated Ethernet PHY (EPHY), which supports up to 2.5G link speed. The output frequency is selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the CMN_PLL_PON_CONFIG register: - 0: 125 MHz - for 1G/100M/10M link speed - 1: 312.5 MHz - for 2.5G link speed The clock is parented on cmn_pll_div2 to reflect the hardware clock tree, while the exposed output rate is selected by the register bit. Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-8-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add PON reference clock supportLuo Jie
The PON (Passive Optical Network) reference clock's parent is cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a configurable 8-bit divider (1-255). The clock supports two modes: - UNIPHY mode (CMN_PLL_PON_MODE_SEL = 0): fixed 31.25 MHz output - PON mode (CMN_PLL_PON_MODE_SEL = 1): parent_rate / divider The clock output can be independently enabled and disabled via the CMN_PLL_PON_EN bit. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-7-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add PPE clock supportLuo Jie
The PPE (packet process engine) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the NSS clock but uses a different field (bits [5:0]). Register the PPE clock through the ipq_cmn_pll_regmap_div_register() helper introduced for the NSS clock, passing the PPE-specific field mask and reusing the same cmn_pll_div2 parent selection as NSS. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-6-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Add NSS clock supportLuo Jie
The NSS (network subsystem) clock's parent is cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a configurable 6-bit divider. Register the NSS clock through a new ipq_cmn_pll_regmap_div_register() helper, built as a plain struct clk_regmap_div instance instead of hand-rolling recalc_rate/set_rate. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-5-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clockLuo Jie
Most CMN PLL output clocks are derived from the 12 GHz PLL output through a shared, physical /2 stage, ahead of any further per-clock processing: a gated fixed rate (PCS/ETH0/ETH1/ETH2/EPHY/ETH), a configurable divider (NSS/PPE/PON), or a rate-select bit (EPHY-RAW). This /2 stage is present in the CMN PLL block on every SoC supported by this driver. Register this /2 stage once as a fixed-factor clock, "cmn_pll_div2", and store it on struct clk_cmn_pll so the output clock types can parent on it. The two plain fixed-rate outputs, xo-24mhz and sleep-32khz, are the exception on IPQ5210 SoC: they stay parented directly on the main PLL clock. On SoCs other than IPQ5210, every output clock is a plain fixed-rate clock (CMN_PLL_CLK_FIXED_RATE) whose rate is a hardcoded absolute value rather than one computed from the parent rate, so this /2 clock is registered there but currently has no consumers; IPQ5210 is simply the first SoC in this driver whose output clocks are modeled as depending on parent_rate, which is what makes the /2 stage significant. Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-4-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flagsLuo Jie
Add a flags field to struct clk_regmap_div and OR it into the CLK_DIVIDER_ROUND_CLOSEST flag passed to divider_determine_rate(), divider_ro_determine_rate(), divider_get_val(), and divider_recalc_rate(), so that qcom drivers can opt into CLK_DIVIDER_* behavior variants such as CLK_DIVIDER_ONE_BASED. This is additive and backward compatible: existing clk_regmap_div users don't initialize .flags, so it defaults to 0, and CLK_DIVIDER_ROUND_CLOSEST | 0 is identical to current behavior. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-3-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_dataLuo Jie
Replace clk_hw_register_fixed_rate_parent_hw() with the managed devm_clk_hw_register_fixed_rate_parent_data() so the fixed-rate output clocks are automatically unregistered when the device is unbound. Since all clocks in the driver are now registered via devm_ variants, the remove callback 'ipq_cmn_pll_clk_remove()' and the manual 'unregister_fixed_clk' error-path loop are no longer needed and are removed. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-1-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoCLuo Jie
Add the compatible string for the IPQ5210 CMN PLL clock controller and the dt-bindings clock ID header for IPQ5210. The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-2-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: negcc-nord: Add the secondary QUSB2 PHY resetBartosz Golaszewski
Add the secondary USB2 PHY reset which is needed by usb_1_hsphy enabling on Nord platform. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260901035322.654-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13dt-bindings: clock: qcom: nord-negcc: Add the secondary QUSB2 PHY resetBartosz Golaszewski
The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but right now only the primary is registered. Add the secondary, which is required by the usb_1 eUSB2 PHY. Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and is instead reset as a whole via NE_GCC_USB20_PRIM_BCR. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260901035322.654-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoCTaniya Das
Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB access to the two EMAC controllers and are required for register access to the Ethernet MACs. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260824-nords_emac_apb_clk-v1-2-290767386bf5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13dt-bindings: clock: qcom: Add EMAC CNOC APB clocks for NordTaniya Das
Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock controller bindings for the Qualcomm Nord SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260824-nords_emac_apb_clk-v1-1-290767386bf5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: rpmh: Add SM7250 rpmh clocksSreeshankar K
Add the RPMH clocks present in SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260816131646.10551-2-sreeshankar0910@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13dt-bindings: clock: qcom,rpmhcc: Document RPMHCC bindings for SM7250Sreeshankar K
Document RPMHCC bindings for clock rpmh driver on Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260821154030.2514-1-sreeshankar0910@gmail.com Link: https://patch.msgid.link/20260816131646.10551-3-sreeshankar0910@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc: Fix GPLL enable register offset for Nord SoCTaniya Das
The GPLLs in the North-East, North-West and South-East global clock controllers on the Qualcomm Nord SoC were registered with a placeholder enable register offset of 0x0. As a result the shared PLL voting register was never programmed, leaving the PLLs' enable state uncontrolled. Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the North-East and South-East controllers, 0x76008 for the North-West controller). Each PLL continues to select its own vote bit through enable_mask. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-x1e80100: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-27-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8750: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-26-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8650: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-25-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8550: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-24-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8450: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-23-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm8350: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-22-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sm4450: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-21-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sdx75: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-20-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sc7280: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-19-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sar2130p: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-18-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-sa8775p: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-17-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-13clk: qcom: gcc-qcs8300: Tie the CX power domain to controllerAbel Vesa
Enable runtime PM for the controller, allowing CX to be powered down once all GCC consumers have released their clocks and GDSCs. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-16-38732033e5b5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>