Qualcomm Technologies Inc. adreno/snapdragon DSI output

DSI Controller:
Required properties:
- compatible:
  * "qcom,mdss-dsi-ctrl"
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
  * "dsi_ctrl"
- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
  be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
  * "bus_clk"
  * "byte_clk"
  * "core_clk"
  * "core_mmss_clk"
  * "iface_clk"
  * "mdp_core_clk"
  * "pixel_clk"
- vdd-supply: phandle to vdd regulator device node
- vddio-supply: phandle to vdd-io regulator device node
- vdda-supply: phandle to vdda regulator device node
- qcom,dsi-phy: phandle to DSI PHY device node

Optional properties:
- panel@0: Node of panel connected to this DSI controller.
  See files in Documentation/devicetree/bindings/panel/ for each supported
  panel.
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
  driving a panel which needs 2 DSI links.
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
  the master link of the 2-DSI panel.
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
  driving a 2-DSI panel whose 2 links need receive command simultaneously.
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
  through MDP block
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
- port: DSI controller output port. This contains one endpoint subnode, with its
  remote-endpoint set to the phandle of the connected panel's endpoint.
  See Documentation/devicetree/bindings/graph.txt for device graph info.

DSI PHY:
Required properties:
- compatible: Could be the following
  * "qcom,dsi-phy-28nm-hpm"
  * "qcom,dsi-phy-28nm-lp"
  * "qcom,dsi-phy-20nm"
- reg: Physical base address and length of the registers of PLL, PHY and PHY
  regulator
- reg-names: The names of register regions. The following regions are required:
  * "dsi_pll"
  * "dsi_phy"
  * "dsi_phy_regulator"
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
  be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
  * "iface_clk"
- vddio-supply: phandle to vdd-io regulator device node

Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
  regulator is wanted.

Example:
	mdss_dsi0: qcom,mdss_dsi@fd922800 {
		compatible = "qcom,mdss-dsi-ctrl";
		qcom,dsi-host-index = <0>;
		interrupt-parent = <&mdss_mdp>;
		interrupts = <4 0>;
		reg-names = "dsi_ctrl";
		reg = <0xfd922800 0x200>;
		power-domains = <&mmcc MDSS_GDSC>;
		clock-names =
			"bus_clk",
			"byte_clk",
			"core_clk",
			"core_mmss_clk",
			"iface_clk",
			"mdp_core_clk",
			"pixel_clk";
		clocks =
			<&mmcc MDSS_AXI_CLK>,
			<&mmcc MDSS_BYTE0_CLK>,
			<&mmcc MDSS_ESC0_CLK>,
			<&mmcc MMSS_MISC_AHB_CLK>,
			<&mmcc MDSS_AHB_CLK>,
			<&mmcc MDSS_MDP_CLK>,
			<&mmcc MDSS_PCLK0_CLK>;
		vdda-supply = <&pma8084_l2>;
		vdd-supply = <&pma8084_l22>;
		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;

		qcom,dual-dsi-mode;
		qcom,master-dsi;
		qcom,sync-dual-dsi;

		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&mdss_dsi_active>;
		pinctrl-1 = <&mdss_dsi_suspend>;

		panel: panel@0 {
			compatible = "sharp,lq101r1sx01";
			reg = <0>;
			link2 = <&secondary>;

			power-supply = <...>;
			backlight = <...>;

			port {
				panel_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};
		};

		port {
			dsi0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
		compatible = "qcom,dsi-phy-28nm-hpm";
		qcom,dsi-phy-index = <0>;
		reg-names =
			"dsi_pll",
			"dsi_phy",
			"dsi_phy_regulator";
		reg =   <0xfd922a00 0xd4>,
			<0xfd922b00 0x2b0>,
			<0xfd922d80 0x7b>;
		clock-names = "iface_clk";
		clocks = <&mmcc MDSS_AHB_CLK>;
		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy-regulator-ldo-mode;
	};
