/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2026 ROHM Semiconductors. * * Author: Matti Vaittinen */ #ifndef _MFD_BD73800_H #define _MFD_BD73800_H #include enum { BD73800_BUCK1 = 0, BD73800_BUCK2, BD73800_BUCK3, BD73800_BUCK4, BD73800_BUCK5, BD73800_BUCK6, BD73800_BUCK7, BD73800_BUCK8, BD73800_LDO1, BD73800_LDO2, BD73800_LDO3, BD73800_LDO4, }; /* * All regulators except BUCK 5 have full 8-bit register of valid voltage * values, including 0. */ #define BD73800_NUM_VOLTS (0xff + 1) /* * BUCK 5 has two sets of voltage ranges, both having valid voltage selectors * from 0x0 to 0x7f */ #define BD73800_BUCK5_VOLTS (0x80 + 0x80) /* BD73800 interrupts */ enum { /* INT_STAT_1 register IRQs, ADC and RTC */ BD73800_INT_ADC_ACCUM_DONE, BD73800_INT_ADC_ACCUM_OVF, BD73800_INT_ADC_ACCUM_VAL, BD73800_INT_ADC_ACCUM_TW, BD73800_INT_ADC_POW_VAL, BD73800_INT_RTC0, BD73800_INT_RTC1, BD73800_INT_RTC2, /* BUCK reg interrupts */ /* INT_STAT_2 IRQs */ BD73800_INT_BUCK1_DVS_DONE, BD73800_INT_BUCK2_DVS_DONE, BD73800_INT_BUCK3_DVS_DONE, BD73800_INT_BUCK4_DVS_DONE, BD73800_INT_BUCK5_DVS_DONE, BD73800_INT_BUCK6_DVS_DONE, BD73800_INT_BUCK7_DVS_DONE, BD73800_INT_BUCK8_DVS_DONE, /* INT_STAT_3 IRQs */ BD73800_INT_BUCK1_OCP, BD73800_INT_BUCK2_OCP, BD73800_INT_BUCK3_OCP, BD73800_INT_BUCK4_OCP, BD73800_INT_BUCK5_OCP, BD73800_INT_BUCK6_OCP, BD73800_INT_BUCK7_OCP, BD73800_INT_BUCK8_OCP, /* INT_STAT_4 IRQs, power-button, WDG and reset */ BD73800_INT_PBTN_LONG_PRESS, BD73800_INT_PBTN_MID_PRESS, /* * The SHORT_PUSH is generated when button is first pressed (longer * than configured time limit), and then released before the MID_PRESS * time limit. The SHORT_PRESS is generated immediately when button is * pressed for longer than configured limit, whether it is released or * not. */ BD73800_INT_PBTN_SHORT_PUSH, BD73800_INT_PBTN_SHORT_PRESS, BD73800_INT_WDG, BD73800_INT_SWRESET, BD73800_INT_SEQ_DONE, /* INT_STAT_5 IRQs, GPIO */ BD73800_INT_GPIO1, BD73800_INT_GPIO2, BD73800_INT_GPIO3, BD73800_INT_GPIO4, }; #define BD73800_MASK_RUN_EN BIT(2) #define BD73800_MASK_SUSP_EN BIT(1) #define BD73800_MASK_IDLE_EN BIT(0) #define BD73800_MASK_VOLT GENMASK(7, 0) #define BD73800_MASK_BUCK5_VOLT GENMASK(6, 0) #define BD73800_MASK_RAMP_DELAY GENMASK(2, 1) #define BD73800_BUCK5_RANGE_MASK BIT(7) /* BD73800 registers */ enum { BD73800_REG_PRODUCT_ID = 0x0, BD73800_REG_MANUFACTURER_ID, BD73800_REG_REVISION, BD73800_REG_NVMVERSION, BD73800_REG_POR_REASON, BD73800_REG_RESET_REASON1, BD73800_REG_RESET_REASON2, BD73800_REG_RESET_REASON3, BD73800_REG_POW_STATE, BD73800_REG_WRST_SEL, BD73800_REG_PS_CTRL_1, BD73800_REG_PS_CTRL_2, BD73800_REG_RCVCFG, BD73800_REG_RCVNUM, BD73800_REG_CRDCFG, /* 0x0f, followed by undocumented reg */ BD73800_REG_BUCK1_ON = 0x11, BD73800_REG_BUCK1_MODE, BD73800_REG_BUCK1_VOLT_RUN, BD73800_REG_BUCK1_VOLT_IDLE, BD73800_REG_BUCK1_VOLT_SUSP, /* 0x15, followed by undocumented reg */ BD73800_REG_BUCK2_ON = 0x17, BD73800_REG_BUCK2_MODE, BD73800_REG_BUCK2_VOLT_RUN, BD73800_REG_BUCK2_VOLT_IDLE, BD73800_REG_BUCK2_VOLT_SUSP, /* 0x1b */ BD73800_REG_BUCK3_ON = 0x1d, BD73800_REG_BUCK3_MODE, BD73800_REG_BUCK3_VOLT_RUN, BD73800_REG_BUCK3_VOLT_IDLE, BD73800_REG_BUCK3_VOLT_SUSP, /* 0x21 */ BD73800_REG_BUCK4_ON = 0x23, BD73800_REG_BUCK4_MODE, BD73800_REG_BUCK4_VOLT_RUN, BD73800_REG_BUCK4_VOLT_IDLE, BD73800_REG_BUCK4_VOLT_SUSP, /* 0x27 */ BD73800_REG_BUCK5_ON = 0x29, BD73800_REG_BUCK5_MODE, BD73800_REG_BUCK5_VOLT_RUN, BD73800_REG_BUCK5_VOLT_IDLE, BD73800_REG_BUCK5_VOLT_SUSP, /* 0x2d */ BD73800_REG_BUCK6_ON = 0x2f, BD73800_REG_BUCK6_MODE, BD73800_REG_BUCK6_VOLT_RUN, BD73800_REG_BUCK6_VOLT_IDLE, BD73800_REG_BUCK6_VOLT_SUSP, /* 0x33 */ BD73800_REG_BUCK7_ON = 0x35, BD73800_REG_BUCK7_MODE, BD73800_REG_BUCK7_VOLT_RUN, BD73800_REG_BUCK7_VOLT_IDLE, BD73800_REG_BUCK7_VOLT_SUSP, /* 0x39 */ BD73800_REG_BUCK8_ON = 0x3b, BD73800_REG_BUCK8_MODE, BD73800_REG_BUCK8_VOLT_RUN, BD73800_REG_BUCK8_VOLT_IDLE, BD73800_REG_BUCK8_VOLT_SUSP, /* 0x3f */ BD73800_REG_LDO1_ON = 0x41, BD73800_REG_LDO1_VOLT, BD73800_REG_LDO1_MODE, BD73800_REG_LDO2_ON, BD73800_REG_LDO2_VOLT, BD73800_REG_LDO2_MODE, BD73800_REG_LDO3_ON, BD73800_REG_LDO3_VOLT, BD73800_REG_LDO3_MODE, BD73800_REG_LDO4_ON, BD73800_REG_LDO4_VOLT, BD73800_REG_LDO4_MODE, /* 0x4c */ BD73800_REG_GPO_OUT = 0x4e, BD73800_REG_OUT32K = 0x50, BD73800_REG_RTC_SEC, BD73800_REG_RTC_MIN, BD73800_REG_RTC_HOUR, BD73800_REG_RTC_WEEK, BD73800_REG_RTC_DAY, BD73800_REG_RTC_MONTH, BD73800_REG_RTC_YEAR, BD73800_REG_RTC_ALM0_SEC, BD73800_REG_RTC_ALM0_MIN, BD73800_REG_RTC_ALM0_HOUR, BD73800_REG_RTC_ALM0_WEEK, BD73800_REG_RTC_ALM0_DAY, BD73800_REG_RTC_ALM0_MONTH, BD73800_REG_RTC_ALM0_YEAR, BD73800_REG_RTC_ALM1_SEC, BD73800_REG_RTC_ALM1_MIN, BD73800_REG_RTC_ALM1_HOUR, BD73800_REG_RTC_ALM1_WEEK, BD73800_REG_RTC_ALM1_DAY, BD73800_REG_RTC_ALM1_MONTH, BD73800_REG_RTC_ALM1_YEAR, BD73800_REG_RTC_ALM2, BD73800_REG_RTC_CONF, /* 0x69 */ BD73800_REG_ADC_CTRL_1 = 0x6b, BD73800_REG_ADC_CTRL_2, BD73800_REG_ADC_ACCUM_NUM2, BD73800_REG_ADC_ACCUM_NUM1, BD73800_REG_ADC_ACCUM_NUM0, BD73800_REG_ADC_ACCUM_KICK, BD73800_REG_ADC_ACCUM_CNT2, BD73800_REG_ADC_ACCUM_CNT1, BD73800_REG_ADC_ACCUM_CNT0, BD73800_REG_ADC_ACCUM_VAL2, BD73800_REG_ADC_ACCUM_VAL1, BD73800_REG_ADC_ACCUM_VAL0, BD73800_REG_ADC_VOL_VAL1, BD73800_REG_ADC_VOL_VAL0, BD73800_REG_ADC_CUR_VAL1, BD73800_REG_ADC_CUR_VAL0, BD73800_REG_ADC_POW_VAL1, BD73800_REG_ADC_POW_VAL0, BD73800_REG_ADC_TEMP_VAL1, BD73800_REG_ADC_TEMP_VAL0, BD73800_REG_ADC_ACCUM_VAL_INT_TH4, BD73800_REG_ADC_ACCUM_VAL_INT_TH3, BD73800_REG_ADC_ACCUM_VAL_INT_TH2, BD73800_REG_ADC_ACCUM_VAL_INT_TH1, BD73800_REG_ADC_ACCUM_VAL_INT_TH0, BD73800_REG_ADC_WARN_TEMP_INT_TH1, BD73800_REG_ADC_WARN_TEMP_INT_TH0, BD73800_REG_ADC_POW_VAL_INT_TH1, BD73800_REG_ADC_POW_VAL_INT_TH0, /* 0x89 */ BD73800_REG_PBTN_CONF = 0x8b, BD73800_REG_INT_MAIN_EN = 0x8f, BD73800_REG_INT_1_EN, BD73800_REG_INT_2_EN, BD73800_REG_INT_3_EN, BD73800_REG_INT_4_EN, BD73800_REG_INT_5_EN, /* 0x94 */ BD73800_REG_INT_MAIN_STAT = 0x96, BD73800_REG_INT_1_STAT, BD73800_REG_INT_2_STAT, BD73800_REG_INT_3_STAT, BD73800_REG_INT_4_STAT, BD73800_REG_INT_5_STAT, /* 0x9b */ BD73800_REG_INT_MAIN_SRC = 0x9d, BD73800_REG_INT_1_SRC, BD73800_REG_INT_2_SRC, BD73800_REG_INT_3_SRC, BD73800_REG_INT_4_SRC, BD73800_REG_INT_5_SRC, /* 0xa2 */ BD73800_REG_RST_MASK = 0xaf, BD73800_MAX_REGISTER, }; #define BD73800_REG_RTC_START BD73800_REG_RTC_SEC #define BD73800_REG_RTC_ALM_START BD73800_REG_RTC_ALM0_SEC /* BD73800 IRQ register masks */ #define BD73800_INT_MAIN_EN_ALL GENMASK(4, 0) #define BD73800_INT_ADC_ACCUM_DONE_MASK BIT(0) #define BD73800_INT_ADC_ACCUM_OVF_MASK BIT(1) #define BD73800_INT_ADC_ACCUM_VAL_MASK BIT(2) #define BD73800_INT_ADC_ACCUM_TW_MASK BIT(3) #define BD73800_INT_ADC_POW_VAL_MASK BIT(4) #define BD73800_INT_RTC0_MASK BIT(5) #define BD73800_INT_RTC1_MASK BIT(6) #define BD73800_INT_RTC2_MASK BIT(7) #define BD73800_INT_BUCK1_DVS_DONE_MASK BIT(0) #define BD73800_INT_BUCK2_DVS_DONE_MASK BIT(1) #define BD73800_INT_BUCK3_DVS_DONE_MASK BIT(2) #define BD73800_INT_BUCK4_DVS_DONE_MASK BIT(3) #define BD73800_INT_BUCK5_DVS_DONE_MASK BIT(4) #define BD73800_INT_BUCK6_DVS_DONE_MASK BIT(5) #define BD73800_INT_BUCK7_DVS_DONE_MASK BIT(6) #define BD73800_INT_BUCK8_DVS_DONE_MASK BIT(7) #define BD73800_INT_BUCK1_OCP_MASK BIT(0) #define BD73800_INT_BUCK2_OCP_MASK BIT(1) #define BD73800_INT_BUCK3_OCP_MASK BIT(2) #define BD73800_INT_BUCK4_OCP_MASK BIT(3) #define BD73800_INT_BUCK5_OCP_MASK BIT(4) #define BD73800_INT_BUCK6_OCP_MASK BIT(5) #define BD73800_INT_BUCK7_OCP_MASK BIT(6) #define BD73800_INT_BUCK8_OCP_MASK BIT(7) #define BD73800_INT_PBTN_LONG_PRESS_MASK BIT(0) #define BD73800_INT_PBTN_MID_PRESS_MASK BIT(1) #define BD73800_INT_PBTN_SHORT_PUSH_MASK BIT(2) #define BD73800_INT_PBTN_SHORT_PRESS_MASK BIT(3) #define BD73800_INT_WDG_MASK BIT(4) #define BD73800_INT_SWRESET_MASK BIT(5) #define BD73800_INT_SEQ_DONE_MASK BIT(6) #define BD73800_INT_GPIO1_MASK BIT(0) #define BD73800_INT_GPIO2_MASK BIT(1) #define BD73800_INT_GPIO3_MASK BIT(2) #define BD73800_INT_GPIO4_MASK BIT(3) #endif /* _MFD_BD73800_H */