/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_X86_PERF_REGS_H
#define _ASM_X86_PERF_REGS_H

#include <linux/bits.h>

enum perf_event_x86_regs {
	PERF_REG_X86_AX,
	PERF_REG_X86_BX,
	PERF_REG_X86_CX,
	PERF_REG_X86_DX,
	PERF_REG_X86_SI,
	PERF_REG_X86_DI,
	PERF_REG_X86_BP,
	PERF_REG_X86_SP,
	PERF_REG_X86_IP,
	PERF_REG_X86_FLAGS,
	PERF_REG_X86_CS,
	PERF_REG_X86_SS,
	PERF_REG_X86_DS,
	PERF_REG_X86_ES,
	PERF_REG_X86_FS,
	PERF_REG_X86_GS,
	PERF_REG_X86_R8,
	PERF_REG_X86_R9,
	PERF_REG_X86_R10,
	PERF_REG_X86_R11,
	PERF_REG_X86_R12,
	PERF_REG_X86_R13,
	PERF_REG_X86_R14,
	PERF_REG_X86_R15,
	/*
	 * The eGPRs/SSP and XMM have overlaps. Only one can be used
	 * at a time. The ABI PERF_SAMPLE_REGS_ABI_SIMD is used to
	 * distinguish which one is used. If PERF_SAMPLE_REGS_ABI_SIMD
	 * is set, then eGPRs/SSP is used, otherwise, XMM is used.
	 *
	 * Extended GPRs (eGPRs)
	 */
	PERF_REG_X86_R16,
	PERF_REG_X86_R17,
	PERF_REG_X86_R18,
	PERF_REG_X86_R19,
	PERF_REG_X86_R20,
	PERF_REG_X86_R21,
	PERF_REG_X86_R22,
	PERF_REG_X86_R23,
	PERF_REG_X86_R24,
	PERF_REG_X86_R25,
	PERF_REG_X86_R26,
	PERF_REG_X86_R27,
	PERF_REG_X86_R28,
	PERF_REG_X86_R29,
	PERF_REG_X86_R30,
	PERF_REG_X86_R31,
	PERF_REG_X86_SSP,
	/* These are the limits for the GPRs. */
	PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
	PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
	PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1,

	/* These all need two bits set because they are 128bit */
	PERF_REG_X86_XMM0  = 32,
	PERF_REG_X86_XMM1  = 34,
	PERF_REG_X86_XMM2  = 36,
	PERF_REG_X86_XMM3  = 38,
	PERF_REG_X86_XMM4  = 40,
	PERF_REG_X86_XMM5  = 42,
	PERF_REG_X86_XMM6  = 44,
	PERF_REG_X86_XMM7  = 46,
	PERF_REG_X86_XMM8  = 48,
	PERF_REG_X86_XMM9  = 50,
	PERF_REG_X86_XMM10 = 52,
	PERF_REG_X86_XMM11 = 54,
	PERF_REG_X86_XMM12 = 56,
	PERF_REG_X86_XMM13 = 58,
	PERF_REG_X86_XMM14 = 60,
	PERF_REG_X86_XMM15 = 62,

	/* These include both GPRs and XMMX registers */
	PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2,
};

#define PERF_REG_EXTENDED_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
#define PERF_X86_EGPRS_MASK	__GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16)

enum {
	PERF_X86_SIMD_XMM_REGS      = 16,
	PERF_X86_SIMD_YMM_REGS      = 16,
	PERF_X86_SIMD_ZMM_REGS      = 32,
	PERF_X86_SIMD_VEC_REGS_MAX  = PERF_X86_SIMD_ZMM_REGS,

	PERF_X86_SIMD_OPMASK_REGS   = 8,
	PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS,
};

#define PERF_X86_SIMD_PRED_MASK	__GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0)
#define PERF_X86_SIMD_VEC_MASK	__GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)

#define PERF_X86_H16ZMM_BASE		16

enum {
	/* 1 qword = 8 bytes */
	PERF_X86_OPMASK_QWORDS   = 1,
	PERF_X86_XMM_QWORDS      = 2,
	PERF_X86_YMM_QWORDS      = 4,
	PERF_X86_ZMM_QWORDS      = 8,
	PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS,
};

#endif /* _ASM_X86_PERF_REGS_H */