From 4210f21c004a18aad11c55bdaf552e649a4fd286 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Fri, 2 May 2025 13:03:07 +0200 Subject: dt-bindings: clock: rk3576: add IOC gated clocks Certain clocks on the RK3576 are additionally essentially "gated" behind some bit toggles in the IOC GRF range. Downstream ungates these by adding a separate clock driver that maps over the GRF range and leaks their implementation of this into the DT. Instead, define some new clock IDs for these, so that consumers of these types of clocks can properly articulate which clock they're using, so that we can then add them to the clock driver for SoCs that need them. Acked-by: Krzysztof Kozlowski Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-1-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rockchip,rk3576-cru.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index f576e61bec70..ded5ce42e62a 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -594,4 +594,14 @@ #define SCMI_ARMCLK_B 11 #define SCMI_CLK_GPU 456 +/* IOC-controlled output clocks */ +#define CLK_SAI0_MCLKOUT_TO_IO 571 +#define CLK_SAI1_MCLKOUT_TO_IO 572 +#define CLK_SAI2_MCLKOUT_TO_IO 573 +#define CLK_SAI3_MCLKOUT_TO_IO 574 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_FSPI0_TO_IO 576 +#define CLK_FSPI1_TO_IO 577 + #endif -- cgit v1.2.3 From 8a023e86f3d999007f2687952afe78ef34a6aa91 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 6 May 2025 09:22:02 +0000 Subject: dt-bindings: clock: Add GRF clock definition for RK3528 These clocks are for SD/SDIO tuning purpose and come with registers in GRF syscon. Signed-off-by: Yao Zi Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250506092206.46143-2-ziyao@disroot.org Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rockchip,rk3528-cru.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h index 55a448f5ed6d..0245a53fc334 100644 --- a/include/dt-bindings/clock/rockchip,rk3528-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -414,6 +414,12 @@ #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 #define MCLK_SDPDIF_SRC_PRE 404 +#define SCLK_SDMMC_DRV 405 +#define SCLK_SDMMC_SAMPLE 406 +#define SCLK_SDIO0_DRV 407 +#define SCLK_SDIO0_SAMPLE 408 +#define SCLK_SDIO1_DRV 409 +#define SCLK_SDIO1_SAMPLE 410 /* scmi-clocks indices */ #define SCMI_PCLK_KEYREADER 0 -- cgit v1.2.3 From 6e06b641ca96c232e0b13f9b44b118742986bcd5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 3 May 2025 22:25:29 +0200 Subject: dt-bindings: clock: rk3036: add SCLK_USB480M clock-id Contrary to how it is implemented right now, the usb480m clock is a controllable mux that can switch between the 24MHz oscillator and the clock output of the usb2phy. Add the needed clock-id to allow setting this mux from DT. Acked-by: Conor Dooley Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250503202532.992033-2-heiko@sntech.de --- include/dt-bindings/clock/rk3036-cru.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 99cc617e1e54..5cbc0e2b08ff 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -47,6 +47,7 @@ #define SCLK_MACREF 152 #define SCLK_MACPLL 153 #define SCLK_SFC 160 +#define SCLK_USB480M 161 /* aclk gates */ #define ACLK_DMAC2 194 -- cgit v1.2.3 From 20fb4ac9cda06527cf60c5ec7dda7c463c9c81be Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 7 May 2025 15:19:20 -0500 Subject: dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset Add the required LVDS reset binding for the LCD TCON. Signed-off-by: Chris Morgan Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20250507201943.330111-2-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/reset/sun50i-h616-ccu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index 81b1eba2a7f7..ba626f7015b5 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -69,5 +69,6 @@ #define RST_BUS_GPADC 60 #define RST_BUS_TCON_LCD0 61 #define RST_BUS_TCON_LCD1 62 +#define RST_BUS_LVDS 63 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ -- cgit v1.2.3 From b887afb9b2362b15c1ee5585df1fb8cf3a3384c6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Mar 2025 09:41:02 +0100 Subject: dt-bindings: clock: add SM6350 QCOM video clock bindings Add device tree bindings for video clock controller for SM6350 SoCs. Signed-off-by: Konrad Dybcio Co-developed-by: Luca Weiss Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,videocc.yaml | 20 ++++++++++++++++ include/dt-bindings/clock/qcom,sm6350-videocc.h | 27 ++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm6350-videocc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 340c7e5cf980..5f7738d6835c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sm6350-videocc.h include/dt-bindings/clock/qcom,videocc-sc7180.h include/dt-bindings/clock/qcom,videocc-sc7280.h include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -26,6 +27,7 @@ properties: - qcom,sc7180-videocc - qcom,sc7280-videocc - qcom,sdm845-videocc + - qcom,sm6350-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc @@ -87,6 +89,24 @@ allOf: - const: bi_tcxo - const: bi_tcxo_ao + - if: + properties: + compatible: + enum: + - qcom,sm6350-videocc + then: + properties: + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Sleep Clock source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: sleep_clk + - if: properties: compatible: diff --git a/include/dt-bindings/clock/qcom,sm6350-videocc.h b/include/dt-bindings/clock/qcom,sm6350-videocc.h new file mode 100644 index 000000000000..2af7f91fa023 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6350-videocc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_PLL0_OUT_EVEN 1 +#define VIDEO_CC_IRIS_AHB_CLK 2 +#define VIDEO_CC_IRIS_CLK_SRC 3 +#define VIDEO_CC_MVS0_AXI_CLK 4 +#define VIDEO_CC_MVS0_CORE_CLK 5 +#define VIDEO_CC_MVSC_CORE_CLK 6 +#define VIDEO_CC_MVSC_CTL_AXI_CLK 7 +#define VIDEO_CC_SLEEP_CLK 8 +#define VIDEO_CC_SLEEP_CLK_SRC 9 +#define VIDEO_CC_VENUS_AHB_CLK 10 + +/* GDSCs */ +#define MVSC_GDSC 0 +#define MVS0_GDSC 1 + +#endif -- cgit v1.2.3