From a8454813854d93649dd21bc926e7c6f1d0c83e3c Mon Sep 17 00:00:00 2001 From: Uma Shankar Date: Thu, 5 Feb 2026 15:13:33 +0530 Subject: drm/i915: Remove i915_reg.h from i9xx_wm.c Move FW_BLC_SELF to common header to make i9xx_wm.c free from i915_reg.h include. Introduce a common intel_gmd_misc_regs.h to define common miscellaneous register definitions across graphics and display. v3: MISC header included as needed, drop from i915_reg (Jani) v2: Introdue a common misc header for GMD Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula Link: https://patch.msgid.link/20260205094341.1882816-13-uma.shankar@intel.com --- include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/drm/intel/intel_gmd_misc_regs.h (limited to 'include/drm/intel/intel_gmd_misc_regs.h') diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h new file mode 100644 index 000000000000..763d7711f21c --- /dev/null +++ b/include/drm/intel/intel_gmd_misc_regs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef _INTEL_GMD_MISC_REGS_H_ +#define _INTEL_GMD_MISC_REGS_H_ + +#define DISP_ARB_CTL _MMIO(0x45000) +#define DISP_FBC_MEMORY_WAKE REG_BIT(31) +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) +#define DISP_FBC_WM_DIS REG_BIT(15) + +#define INSTPM _MMIO(0x20c0) +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */ +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts + will not assert AGPBUSY# and will only + be delivered when out of C3. */ +#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ +#define INSTPM_TLB_INVALIDATE (1 << 9) +#define INSTPM_SYNC_FLUSH (1 << 5) + +#endif -- cgit v1.2.3