From b56fb8aa66fc18cf4d44a95c4edb97ffcc3d63ef Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:10 +0100 Subject: interconnect: qcom: icc-rpmh: Get parent's regmap for nested NoCs Since commit 57eb14779dfd ("interconnect: qcom: icc-rpmh: Support child NoC device probe") the icc-rpmh driver supports initializing child NoCs, but those child NoCs also need to be able to get the parent's regmap in order to enable QoS. Change the driver to support that and support programming QoS register. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-2-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpmh.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index f90c29111f48..3b445acefece 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -308,14 +308,19 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) - goto skip_qos_config; - - qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); - if (IS_ERR(qp->regmap)) { - dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap)); - goto skip_qos_config; + /* Try parent's regmap first */ + qp->regmap = dev_get_regmap(dev->parent, NULL); + if (!qp->regmap) { + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + goto skip_qos_config; + + qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); + if (IS_ERR(qp->regmap)) { + dev_info(dev, "Skipping QoS, regmap failed; %ld\n", + PTR_ERR(qp->regmap)); + goto skip_qos_config; + } } qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks); -- cgit v1.2.3 From ccd789e53a5c72bb90be85a5b2ebfbb26b9c03ea Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:11 +0100 Subject: interconnect: qcom: sm6350: Remove empty BCM arrays Clean up the code by removing empty BCM arrays to save some lines. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-3-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers') diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 99c435a5968f..246549cb761e 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1526,9 +1526,6 @@ static const struct qcom_icc_desc sm6350_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm * const dc_noc_bcms[] = { -}; - static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, @@ -1538,8 +1535,6 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { static const struct qcom_icc_desc sm6350_dc_noc = { .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), - .bcms = dc_noc_bcms, - .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; static struct qcom_icc_bcm * const gem_noc_bcms[] = { @@ -1600,9 +1595,6 @@ static const struct qcom_icc_desc sm6350_mmss_noc = { .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm * const npu_noc_bcms[] = { -}; - static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, @@ -1620,8 +1612,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { static const struct qcom_icc_desc sm6350_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), - .bcms = npu_noc_bcms, - .num_bcms = ARRAY_SIZE(npu_noc_bcms), }; static struct qcom_icc_bcm * const system_noc_bcms[] = { -- cgit v1.2.3 From ee7184813059388c86d73819d9c1c166aa3aab21 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:12 +0100 Subject: interconnect: qcom: sm6350: enable QoS configuration Enable QoS configuration for master ports with predefined values for priority and urgency forwarding. While this does require some "clocks" to be specified in devicetree to work correctly, thanks to ".qos_requires_clocks = true," this is backwards compatible with old DT as QoS programming will be skipped for aggre1_noc and aggre2_noc when clocks are not provided. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-4-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 288 +++++++++++++++++++++++++++++++++++++ 1 file changed, 288 insertions(+) (limited to 'drivers') diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 246549cb761e..d96bec1cbb26 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -150,26 +150,50 @@ static struct qcom_icc_node qhm_a1noc_cfg = { .link_nodes = { &srvc_aggre1_noc }, }; +static struct qcom_icc_qosbox qhm_qup_0_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_0_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; +static struct qcom_icc_qosbox xm_emmc_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", .channels = 1, .buswidth = 8, + .qosbox = &xm_emmc_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 4, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .channels = 1, .buswidth = 8, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, .link_nodes = { &qns_a1noc_snoc }, }; @@ -182,58 +206,113 @@ static struct qcom_icc_node qhm_a2noc_cfg = { .link_nodes = { &srvc_aggre2_noc }, }; +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qhm_qup_1_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 2, + .urg_fwd = 0, +}; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_1_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x6000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .channels = 1, .buswidth = 8, + .qosbox = &qxm_crypto_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .channels = 1, .buswidth = 8, + .qosbox = &qxm_ipa_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_qdss_etr_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc2_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .channels = 1, .buswidth = 8, + .qosbox = &xm_usb3_0_qos, .num_links = 1, .link_nodes = { &qns_a2noc_snoc }, }; @@ -278,18 +357,34 @@ static struct qcom_icc_node qup1_core_master = { .link_nodes = { &qup1_core_slave }, }; +static struct qcom_icc_qosbox qnm_npu_qos = { + .num_ports = 2, + .port_offsets = { 0xf000, 0x11000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", .channels = 2, .buswidth = 32, + .qosbox = &qnm_npu_qos, .num_links = 1, .link_nodes = { &qns_cdsp_gemnoc }, }; +static struct qcom_icc_qosbox qxm_npu_dsp_qos = { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", .channels = 1, .buswidth = 8, + .qosbox = &qxm_npu_dsp_qos, .num_links = 1, .link_nodes = { &qns_cdsp_gemnoc }, }; @@ -401,19 +496,35 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = { &qhs_gemnoc }, }; +static struct qcom_icc_qosbox acm_apps_qos = { + .num_ports = 2, + .port_offsets = { 0x2f100, 0x2f000 }, + .prio = 0, + .urg_fwd = 0, +}; + static struct qcom_icc_node acm_apps = { .name = "acm_apps", .channels = 1, .buswidth = 16, + .qosbox = &acm_apps_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox acm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 6, + .urg_fwd = 0, +}; + static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", .channels = 1, .buswidth = 8, + .qosbox = &acm_sys_tcu_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, @@ -429,53 +540,101 @@ static struct qcom_icc_node qhm_gemnoc_cfg = { &qhs_mdsp_ms_mpu_cfg }, }; +static struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .num_ports = 1, + .port_offsets = { 0x2e000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", .channels = 1, .buswidth = 32, + .qosbox = &qnm_cmpnoc_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 1, + .port_offsets = { 0x30000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, }; +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0x32000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .channels = 1, .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, .num_links = 1, .link_nodes = { &qns_llcc }, }; +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x31000 }, + .prio = 0, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .channels = 1, .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, .num_links = 1, .link_nodes = { &qns_llcc }, }; +static struct qcom_icc_qosbox qxm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x33080 }, + .prio = 0, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", .channels = 2, .buswidth = 32, + .qosbox = &qxm_gpu_qos, .num_links = 2, .link_nodes = { &qns_llcc, &qns_gem_noc_snoc }, @@ -497,50 +656,98 @@ static struct qcom_icc_node qhm_mnoc_cfg = { .link_nodes = { &srvc_mnoc }, }; +static struct qcom_icc_qosbox qnm_video0_qos = { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", .channels = 1, .buswidth = 32, + .qosbox = &qnm_video0_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qnm_video_cvp_qos = { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 5, + .urg_fwd = 1, +}; + static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_cvp_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0xa000, 0xb000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", .channels = 2, .buswidth = 32, + .qosbox = &qxm_camnoc_hf_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; +static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 5, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", .channels = 1, .buswidth = 8, + .qosbox = &qxm_camnoc_icp_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", .channels = 1, .buswidth = 32, + .qosbox = &qxm_camnoc_sf_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_sf }, }; +static struct qcom_icc_qosbox qxm_mdp0_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 3, + .urg_fwd = 1, +}; + static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", .channels = 1, .buswidth = 32, + .qosbox = &qxm_mdp0_qos, .num_links = 1, .link_nodes = { &qns_mem_noc_hf }, }; @@ -616,19 +823,35 @@ static struct qcom_icc_node qnm_gemnoc = { &xs_qdss_stm }, }; +static struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, +}; + static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", .channels = 1, .buswidth = 8, + .qosbox = &qxm_pimem_qos, .num_links = 2, .link_nodes = { &qns_gemnoc_gc, &qxs_imem }, }; +static struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, +}; + static struct qcom_icc_node xm_gic = { .name = "xm_gic", .channels = 1, .buswidth = 8, + .qosbox = &xm_gic_qos, .num_links = 1, .link_nodes = { &qns_gemnoc_gc }, }; @@ -1388,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; +static const struct regmap_config sm6350_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre1_noc = { + .config = &sm6350_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1413,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; +static const struct regmap_config sm6350_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre2_noc = { + .config = &sm6350_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1459,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, }; +static const struct regmap_config sm6350_compute_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_compute_noc = { + .config = &sm6350_compute_noc_regmap_config, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1532,7 +1784,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_LLCC_CFG] = &qhs_llcc, }; +static const struct regmap_config sm6350_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_dc_noc = { + .config = &sm6350_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), }; @@ -1561,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; +static const struct regmap_config sm6350_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3e200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_gem_noc = { + .config = &sm6350_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1588,7 +1858,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; +static const struct regmap_config sm6350_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c100, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_mmss_noc = { + .config = &sm6350_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1643,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sm6350_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_system_noc = { + .config = &sm6350_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, -- cgit v1.2.3