From f4cdbb5d54057838b14a9b537309df24f20232c2 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Tue, 31 Mar 2026 19:14:31 -0400 Subject: drm/amd/display: Fix implicit narrowing conversion warnings [Why] Multiple display source files contain implicit narrowing conversions when assigning wider integer types (int, uint32_t) to narrower fields (uint8_t, uint16_t) at hardware register, protocol, and storage boundaries. These conversions are intentional but undocumented, and accompanying runtime assertions add noise without providing compile-time safety. [How] Add explicit casts at all intentional narrowing boundaries across display source files. Use narrower loop variable types where loop bounds guarantee safe range. Remove runtime assertions paired with narrowing casts, inline single-use intermediate variables, and revert block scopes and braces introduced solely to contain those assertions. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: Chenyu Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 4 ++-- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 24 +++++++++------------- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_panel_cntl.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 14 ++++++------- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 12 +++++------ drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 23 +++++++++++---------- 8 files changed, 44 insertions(+), 47 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dce') diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index 673bb87d2c17..eee58f946fae 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -321,7 +321,7 @@ static int read_channel_reply(struct dce_aux *engine, uint32_t size, uint32_t aux_sw_data_val; REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); - buffer[i] = aux_sw_data_val; + buffer[i] = (uint8_t)aux_sw_data_val; ++i; } @@ -375,7 +375,7 @@ static enum aux_return_code_type get_channel_status( (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK)) return AUX_RET_ERROR_INVALID_REPLY; - *returned_bytes = get_reg_field_value(value, + *returned_bytes = (uint8_t)get_reg_field_value(value, AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 25c13822fede..ac9eed58c415 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -162,11 +162,9 @@ static bool calculate_fb_and_fractional_fb_divider( feedback_divider *= (uint64_t) (calc_pll_cs->fract_fb_divider_precision_factor); - *feedback_divider_param = - div_u64_rem( - feedback_divider, - calc_pll_cs->fract_fb_divider_factor, - fract_feedback_divider_param); + *feedback_divider_param = (uint32_t)div_u64_rem( + feedback_divider, calc_pll_cs->fract_fb_divider_factor, + fract_feedback_divider_param); if (*feedback_divider_param != 0) return true; @@ -240,7 +238,7 @@ static bool calc_fb_divider_checking_tolerance( pll_settings->calculated_pix_clk_100hz = actual_calculated_clock_100hz; pll_settings->vco_freq = - div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); + (uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); return true; } return false; @@ -440,8 +438,7 @@ static bool pll_adjust_pix_clk( bp_adjust_pixel_clock_params. encoder_object_id = pix_clk_params->encoder_object_id; bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; - bp_adjust_pixel_clock_params. - ss_enable = pix_clk_params->flags.ENABLE_SS; + bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0; bp_result = clk_src->bios->funcs->adjust_pixel_clock( clk_src->bios, &bp_adjust_pixel_clock_params); if (bp_result == BP_RESULT_OK) { @@ -958,7 +955,7 @@ static bool dce112_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); return true; } @@ -1059,7 +1056,7 @@ static bool dcn31_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1162,7 +1159,7 @@ static bool dcn401_program_pix_clk( dce112_program_pixel_clk_resync(clk_src, pix_clk_params->signal_type, pix_clk_params->color_depth, - pix_clk_params->flags.SUPPORT_YCBCR420); + pix_clk_params->flags.SUPPORT_YCBCR420 != 0); } return true; @@ -1211,9 +1208,8 @@ static bool get_pixel_clk_frequency_100hz( */ modulo_hz = REG_READ(MODULO[inst]); if (modulo_hz) - *pixel_clk_khz = div_u64((uint64_t)clock_hz* - dp_dto_ref_khz*10, - modulo_hz); + *pixel_clk_khz = (unsigned int)div_u64((uint64_t)clock_hz * + dp_dto_ref_khz * 10, modulo_hz); else *pixel_clk_khz = 0; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index fe239a96121e..05892ab4529f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -120,7 +120,7 @@ static void process_channel_reply( uint32_t i2c_data; REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); - *buffer++ = i2c_data; + *buffer++ = (uint8_t)i2c_data; --length; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c index de31fb1b6819..31a9181c6a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c @@ -209,7 +209,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, if (pwm_period_bitcnt == 0) bit_count = 16; else - bit_count = pwm_period_bitcnt; + bit_count = (uint8_t)pwm_period_bitcnt; /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */ masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1); @@ -224,7 +224,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl, * components shift by bitCount then mask 16 bits and add rounding bit * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0 */ - backlight_16bit = active_duty_cycle >> bit_count; + backlight_16bit = (uint32_t)(active_duty_cycle >> bit_count); backlight_16bit &= 0xFFFF; backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index c1448ae47366..d178dcc4306d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -802,7 +802,7 @@ static void program_bit_depth_reduction( ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */ - spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED; + spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0; /* Default to 12 bit truncation without rounding */ trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT; trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE; @@ -835,9 +835,9 @@ static void program_bit_depth_reduction( spatial_dither_enable, DCP_SPATIAL_DITHER_MODE_A_AA_A, DCP_SPATIAL_DITHER_DEPTH_30BPP, - bit_depth_params->flags.FRAME_RANDOM, - bit_depth_params->flags.RGB_RANDOM, - bit_depth_params->flags.HIGHPASS_RANDOM); + bit_depth_params->flags.FRAME_RANDOM != 0, + bit_depth_params->flags.RGB_RANDOM != 0, + bit_depth_params->flags.HIGHPASS_RANDOM != 0); } #if defined(CONFIG_DRM_AMD_DC_SI) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c index 806b5709c9e7..a3cd04fc44f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c @@ -176,7 +176,7 @@ void dmub_abm_init_config(struct abm *abm, cmd.abm_init_config.header.type = DMUB_CMD__ABM; cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_init_config.abm_init_config_data.bytes = bytes; + cmd.abm_init_config.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask; @@ -237,7 +237,7 @@ bool dmub_abm_save_restore( cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE; cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; - cmd.abm_save_restore.abm_init_config_data.bytes = bytes; + cmd.abm_save_restore.abm_init_config_data.bytes = (uint16_t)bytes; cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask; @@ -265,10 +265,10 @@ bool dmub_abm_set_pipe(struct abm *abm, memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; - cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; - cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; - cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; - cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; + cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; + cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst; + cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option; + cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst; cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); @@ -308,7 +308,7 @@ bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned i memset(&cmd, 0, sizeof(cmd)); cmd.abm_set_event.header.type = DMUB_CMD__ABM; cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT; - cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable; + cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = (uint8_t)scaling_enable; cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map; cmd.abm_set_event.abm_set_event_data.panel_mask = (1<mpcc_inst = pipe_ctx->plane_res.mpcc_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; if (pipe_ctx->stream_res.opp) - copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; + copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst; else copy_settings_data->opp_inst = 0; if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; // Misc copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm; - copy_settings_data->psr_level = psr_context->psr_level.u32all; + copy_settings_data->psr_level = (uint16_t)psr_context->psr_level.u32all; copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations; - copy_settings_data->frame_delay = psr_context->frame_delay; + copy_settings_data->frame_delay = (uint8_t)psr_context->frame_delay; copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; - copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; + copy_settings_data->init_sdp_deadline = (uint16_t)psr_context->sdpTransmitLineNumDeadline; copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR; copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 0af1b8e0a49e..9b50bf1d80fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -151,22 +151,23 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->digfe_inst = replay_context->digfe_inst; if (pipe_ctx->plane_res.dpp) - copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; + copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst; else copy_settings_data->dpp_inst = 0; + if (pipe_ctx->stream_res.tg) - copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; + copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; else copy_settings_data->otg_inst = 0; copy_settings_data->dpphy_inst = link->link_enc->transmitter; // Misc - copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns; - copy_settings_data->panel_inst = panel_inst; - copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags; + copy_settings_data->line_time_in_ns = (uint16_t)replay_context->line_time_in_ns; + copy_settings_data->panel_inst = (uint16_t)panel_inst; + copy_settings_data->debug.u32All = (uint16_t)link->replay_settings.config.debug_flags; copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; - copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; + copy_settings_data->max_deviation_line = (uint16_t)link->dpcd_caps.pr_info.max_deviation_line; copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode; @@ -193,13 +194,13 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode; if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { - copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns; - copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns; - copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns; + copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns; + copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns; + copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns; copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us; copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us = - dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; + (uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link); } -- cgit v1.2.3