From e3f05d3b18e6cfbddaed687b4a57c280015acc1f Mon Sep 17 00:00:00 2001 From: Chunyan Zhang Date: Thu, 7 Dec 2017 20:57:08 +0800 Subject: clk: sprd: add divider clock support This is a feature that can also be found in sprd composite clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Chunyan Zhang Signed-off-by: Stephen Boyd --- drivers/clk/sprd/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/sprd/Makefile') diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile index cee36b511109..80e603905c90 100644 --- a/drivers/clk/sprd/Makefile +++ b/drivers/clk/sprd/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o clk-sprd-y += common.o clk-sprd-y += gate.o clk-sprd-y += mux.o +clk-sprd-y += div.o -- cgit v1.2.3