From e21e74c6e251152dfc45efdf2279db2778d51223 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 29 May 2023 10:34:40 +0200 Subject: clk: qcom: mmcc-msm8974: Add OXILICX_GDSC for msm8226 On msm8226 we also have OXILICX_GDSC but we need a slighly different config, with a .cxcs defined for clock but with no parent. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-oxilicx-v2-1-f7e4ebff3d61@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/mmcc-msm8974.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 82f6bad144a9..c37524d55d8e 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -2426,6 +2426,16 @@ static struct gdsc oxilicx_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; +static struct gdsc oxili_cx_gdsc_msm8226 = { + .gdscr = 0x4034, + .cxcs = (unsigned int []){ 0x4028 }, + .cxc_count = 1, + .pd = { + .name = "oxili_cx", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *mmcc_msm8226_clocks[] = { [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, @@ -2515,6 +2525,7 @@ static struct gdsc *mmcc_msm8226_gdscs[] = { [MDSS_GDSC] = &mdss_gdsc, [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, + [OXILICX_GDSC] = &oxili_cx_gdsc_msm8226, }; static const struct regmap_config mmcc_msm8226_regmap_config = { -- cgit v1.2.3 From 745dfa078666a70be9aabc5d96e3f04e1f412d0c Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 9 Jun 2023 11:26:31 +0530 Subject: clk: qcom: gcc-ipq9574: Add USB related clocks Add the clocks needed for enabling USB in IPQ9574 Reviewed-by: Dmitry Baryshkov Acked-by: Stephen Boyd Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/d1c5aa4a8535c645fdb06df62a562918516ba0c6.1686289721.git.quic_varada@quicinc.com [bjorn: Clock defines split out to separate commit] Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq9574.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 6914f962c893..8f430367299e 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2004,6 +2004,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = { }, }; +static struct clk_branch gcc_usb0_pipe_clk = { + .halt_reg = 0x2c054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2c054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk = { + .halt_reg = 0x2c058, + .clkr = { + .enable_reg = 0x2c058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb0_sleep_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_sleep_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { F(144000, P_XO, 16, 12, 125), F(400000, P_XO, 12, 1, 5), @@ -4003,6 +4038,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, -- cgit v1.2.3 From f6f89d194e4ddcfe197ac8a05ed4161f642a5c68 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:32 +0200 Subject: clk: qcom: gpucc-sm6350: Introduce index-based clk lookup Add the nowadays-prefered and marginally faster way of looking up parent clocks in the device tree. It also allows for clock-names-independent operation, so long as the order (which is enforced by schema) is kept. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-1-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sm6350.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index ef15185a99c3..a9887d1f0ed7 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -24,6 +24,12 @@ #define CX_GMU_CBCR_WAKE_MASK 0xF #define CX_GMU_CBCR_WAKE_SHIFT 8 +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + enum { P_BI_TCXO, P_GPLL0_OUT_MAIN, @@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll0", .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, .fw_name = "bi_tcxo", }, .num_parents = 1, @@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll1", .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, .fw_name = "bi_tcxo", }, .num_parents = 1, @@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = { }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, + { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk" }, - { .fw_name = "gcc_gpu_gpll0_div_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" }, }; static const struct parent_map gpu_cc_parent_map_1[] = { @@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = { }; static const struct clk_parent_data gpu_cc_parent_data_1[] = { - { .fw_name = "bi_tcxo" }, + { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &crc_div.hw }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { -- cgit v1.2.3 From 743913b343a3ec2510fe3c0dfaff03d049659922 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:33 +0200 Subject: clk: qcom: gpucc-sm6350: Fix clock source names fw_name for GCC inputs didn't match the bindings. Fix it. Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-2-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sm6350.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index a9887d1f0ed7..0bcbba2a2943 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -132,8 +132,8 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, - { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk_src" }, }; static const struct parent_map gpu_cc_parent_map_1[] = { @@ -151,7 +151,7 @@ static const struct clk_parent_data gpu_cc_parent_data_1[] = { { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" }, + { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { -- cgit v1.2.3 From 2fd02de27054576a4a8c89302e2f77122c55e957 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 19:48:06 +0200 Subject: clk: qcom: gcc-sc8280xp: Add missing GDSC flags All of the 8280's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Signed-off-by: Konrad Dybcio Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230620-topic-sc8280_gccgdsc-v2-1-562c1428c10d@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc8280xp.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index b90c71637814..64bea886322d 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6761,7 +6761,7 @@ static struct gdsc pcie_0_tunnel_gdsc = { .name = "pcie_0_tunnel_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc pcie_1_tunnel_gdsc = { @@ -6772,7 +6772,7 @@ static struct gdsc pcie_1_tunnel_gdsc = { .name = "pcie_1_tunnel_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; /* @@ -6787,7 +6787,7 @@ static struct gdsc pcie_2a_gdsc = { .name = "pcie_2a_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, }; static struct gdsc pcie_2b_gdsc = { @@ -6798,7 +6798,7 @@ static struct gdsc pcie_2b_gdsc = { .name = "pcie_2b_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, }; static struct gdsc pcie_3a_gdsc = { @@ -6809,7 +6809,7 @@ static struct gdsc pcie_3a_gdsc = { .name = "pcie_3a_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, }; static struct gdsc pcie_3b_gdsc = { @@ -6820,7 +6820,7 @@ static struct gdsc pcie_3b_gdsc = { .name = "pcie_3b_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, }; static struct gdsc pcie_4_gdsc = { @@ -6831,7 +6831,7 @@ static struct gdsc pcie_4_gdsc = { .name = "pcie_4_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, }; static struct gdsc ufs_card_gdsc = { @@ -6840,6 +6840,7 @@ static struct gdsc ufs_card_gdsc = { .name = "ufs_card_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc ufs_phy_gdsc = { @@ -6848,6 +6849,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc usb30_mp_gdsc = { @@ -6856,6 +6858,7 @@ static struct gdsc usb30_mp_gdsc = { .name = "usb30_mp_gdsc", }, .pwrsts = PWRSTS_RET_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc usb30_prim_gdsc = { @@ -6864,6 +6867,7 @@ static struct gdsc usb30_prim_gdsc = { .name = "usb30_prim_gdsc", }, .pwrsts = PWRSTS_RET_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc usb30_sec_gdsc = { @@ -6872,6 +6876,7 @@ static struct gdsc usb30_sec_gdsc = { .name = "usb30_sec_gdsc", }, .pwrsts = PWRSTS_RET_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc emac_0_gdsc = { @@ -6880,6 +6885,7 @@ static struct gdsc emac_0_gdsc = { .name = "emac_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, }; static struct gdsc emac_1_gdsc = { @@ -6888,6 +6894,7 @@ static struct gdsc emac_1_gdsc = { .name = "emac_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, }; static struct clk_regmap *gcc_sc8280xp_clocks[] = { -- cgit v1.2.3 From 4712eb7ff85bd3dd09c6668b8de4080e02b3eea9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 19:48:08 +0200 Subject: clk: qcom: gcc-sc8280xp: Add missing GDSCs There are 10 more GDSCs that we've not been caring about, and by extension (and perhaps even more importantly), not putting to sleep. Add them. Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Signed-off-by: Konrad Dybcio Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230620-topic-sc8280_gccgdsc-v2-3-562c1428c10d@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc8280xp.c | 100 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 64bea886322d..3e1a62fa3a07 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6897,6 +6897,96 @@ static struct gdsc emac_1_gdsc = { .flags = RETAIN_FF_ENABLE, }; +static struct gdsc usb4_1_gdsc = { + .gdscr = 0xb8004, + .pd = { + .name = "usb4_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc usb4_gdsc = { + .gdscr = 0x2a004, + .pd = { + .name = "usb4_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { + .gdscr = 0x7d050, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { + .gdscr = 0x7d058, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { + .gdscr = 0x7d054, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { + .gdscr = 0x7d06c, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { + .gdscr = 0x7d05c, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { + .gdscr = 0x7d060, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu2_gdsc = { + .gdscr = 0x7d0a0, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu3_gdsc = { + .gdscr = 0x7d0a4, + .pd = { + .name = "hlos1_vote_turing_mmu_tbu3_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + static struct clk_regmap *gcc_sc8280xp_clocks[] = { [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr, [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr, @@ -7377,6 +7467,16 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = { [USB30_SEC_GDSC] = &usb30_sec_gdsc, [EMAC_0_GDSC] = &emac_0_gdsc, [EMAC_1_GDSC] = &emac_1_gdsc, + [USB4_1_GDSC] = &usb4_1_gdsc, + [USB4_GDSC] = &usb4_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU2_GDSC] = &hlos1_vote_turing_mmu_tbu2_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU3_GDSC] = &hlos1_vote_turing_mmu_tbu3_gdsc, }; static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { -- cgit v1.2.3 From ff19022b9112d6bbd7c117c83e944cb21b438e91 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 30 Jun 2023 22:19:44 +0300 Subject: clk: qcom: gcc-sm7150: Add CLK_OPS_PARENT_ENABLE to sdcc2 rcg Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: a808d58ddf29 ("clk: qcom: Add Global Clock Controller (GCC) driver for SM7150") Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230630191944.20282-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sm7150.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index 6b628178f62c..6da87f0436d0 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -739,6 +739,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_floor_ops, + .flags = CLK_OPS_PARENT_ENABLE, }, }; -- cgit v1.2.3 From db382dd55bcb8bc6319a14ad50689c19dba83b7b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 7 Jul 2023 13:29:26 +0530 Subject: clk: qcom: gcc-sc8280xp: Allow PCIe GDSCs to enter retention state With the minimal system suspend support in place for the PCIe driver that keeps the interconnect path voted, the ALWAYS_ON flag can now be dropped. Also, the pwrsts PWRSTS_RET_ON flag should be used to allow the GDSCs to enter the retention state when the parent domain get's turned off during system suspend. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230707075926.11726-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc8280xp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 3e1a62fa3a07..1fb6ffac730c 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6786,8 +6786,8 @@ static struct gdsc pcie_2a_gdsc = { .pd = { .name = "pcie_2a_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc pcie_2b_gdsc = { @@ -6797,8 +6797,8 @@ static struct gdsc pcie_2b_gdsc = { .pd = { .name = "pcie_2b_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc pcie_3a_gdsc = { @@ -6808,8 +6808,8 @@ static struct gdsc pcie_3a_gdsc = { .pd = { .name = "pcie_3a_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc pcie_3b_gdsc = { @@ -6819,8 +6819,8 @@ static struct gdsc pcie_3b_gdsc = { .pd = { .name = "pcie_3b_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc pcie_4_gdsc = { @@ -6830,8 +6830,8 @@ static struct gdsc pcie_4_gdsc = { .pd = { .name = "pcie_4_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc ufs_card_gdsc = { -- cgit v1.2.3 From e1e1267413d2e9fbe3a34c5a5f701b0f5fb0bf2c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 19 Jun 2023 15:04:29 +0200 Subject: clk: qcom: smd-rpm: Move some RPM resources to the common header In preparation for handling the bus clocks in the icc driver, carve out some defines and a struct definition to the common rpm header. Reviewed-by: Dmitry Baryshkov Acked-by: Stephen Boyd Signed-off-by: Konrad Dybcio Acked-by: Georgi Djakov Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-4-09c78c175546@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-smd-rpm.c | 13 ------------- include/linux/soc/qcom/smd-rpm.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 13 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index e4de74b68797..937cb1515968 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -18,13 +18,6 @@ #include -#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 -#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 -#define QCOM_RPM_SMD_KEY_RATE 0x007a484b -#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 -#define QCOM_RPM_SMD_KEY_STATE 0x54415453 -#define QCOM_RPM_SCALING_ENABLE_ID 0x2 - #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ type, r_id, key) \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ @@ -171,12 +164,6 @@ struct clk_smd_rpm { unsigned long rate; }; -struct clk_smd_rpm_req { - __le32 key; - __le32 nbytes; - __le32 value; -}; - struct rpm_smd_clk_desc { struct clk_smd_rpm **clks; size_t num_clks; diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 99499e4b080e..8190878645f9 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -2,6 +2,8 @@ #ifndef __QCOM_SMD_RPM_H__ #define __QCOM_SMD_RPM_H__ +#include + struct qcom_smd_rpm; #define QCOM_SMD_RPM_ACTIVE_STATE 0 @@ -45,6 +47,19 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_PKA_CLK 0x616b70 #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d +#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 +#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b +#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 +#define QCOM_RPM_SMD_KEY_STATE 0x54415453 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2 + +struct clk_smd_rpm_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, u32 resource_type, u32 resource_id, -- cgit v1.2.3 From 410da7e344a69faf65af8a1e80d9963648a9e6a3 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 19 Jun 2023 15:04:30 +0200 Subject: soc: qcom: smd-rpm: Move icc_smd_rpm registration to clk-smd-rpm icc_smd_rpm will do bus clock votes itself rather than taking the unnecessary detour through the clock subsystem. However, it can only do that after the clocks have been handed off and scaling has been enabled in the RPM in clk-smd-rpm. Move the icc_smd_rpm registration from smd-rpm.c to clk-smd-rpm.c to avoid any possible races. icc_smd_rpm gets the driver data from the smd-rpm device, so still register the platform device on the smd-rpm parent device. Signed-off-by: Stephan Gerhold [Konrad: remove unrelated cleanups] Acked-by: Stephen Boyd Signed-off-by: Konrad Dybcio Acked-by: Georgi Djakov Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-5-09c78c175546@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-smd-rpm.c | 21 +++++++++++++++++++++ drivers/soc/qcom/smd-rpm.c | 17 +---------------- 2 files changed, 22 insertions(+), 16 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 937cb1515968..6e7f0438e8b8 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1289,12 +1289,20 @@ static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); } +static void rpm_smd_unregister_icc(void *data) +{ + struct platform_device *icc_pdev = data; + + platform_device_unregister(icc_pdev); +} + static int rpm_smd_clk_probe(struct platform_device *pdev) { int ret; size_t num_clks, i; struct clk_smd_rpm **rpm_smd_clks; const struct rpm_smd_clk_desc *desc; + struct platform_device *icc_pdev; rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); if (!rpmcc_smd_rpm) { @@ -1344,6 +1352,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) if (ret) goto err; + icc_pdev = platform_device_register_data(pdev->dev.parent, + "icc_smd_rpm", -1, NULL, 0); + if (IS_ERR(icc_pdev)) { + dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n", + icc_pdev); + /* No need to unregister clocks because of this */ + } else { + ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc, + icc_pdev); + if (ret) + goto err; + } + return 0; err: dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 0c1aa809cc4e..577f1f25ab10 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -19,7 +19,6 @@ /** * struct qcom_smd_rpm - state of the rpm device driver * @rpm_channel: reference to the smd channel - * @icc: interconnect proxy device * @dev: rpm device * @ack: completion for acks * @lock: mutual exclusion around the send/complete pair @@ -27,7 +26,6 @@ */ struct qcom_smd_rpm { struct rpmsg_endpoint *rpm_channel; - struct platform_device *icc; struct device *dev; struct completion ack; @@ -197,7 +195,6 @@ static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev, static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev) { struct qcom_smd_rpm *rpm; - int ret; rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL); if (!rpm) @@ -210,23 +207,11 @@ static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev) rpm->rpm_channel = rpdev->ept; dev_set_drvdata(&rpdev->dev, rpm); - rpm->icc = platform_device_register_data(&rpdev->dev, "icc_smd_rpm", -1, - NULL, 0); - if (IS_ERR(rpm->icc)) - return PTR_ERR(rpm->icc); - - ret = of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev); - if (ret) - platform_device_unregister(rpm->icc); - - return ret; + return of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev); } static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev) { - struct qcom_smd_rpm *rpm = dev_get_drvdata(&rpdev->dev); - - platform_device_unregister(rpm->icc); of_platform_depopulate(&rpdev->dev); } -- cgit v1.2.3 From d6edc31f3a68d8d0636e0cfcd9eced7460ad32f4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 19 Jun 2023 15:04:43 +0200 Subject: clk: qcom: smd-rpm: Separate out interconnect bus clocks The interconnect bus clocks are now handled within the ICC framework. They still however need to get a kickstart *before* we call clk_smd_rpm_enable_scaling(), or RPM will assume that they should all be running at 0 kHz and the system will inevitably die. Separate them out to ensure such a kickstart can still take place. As a happy accident, the file got smaller: Total: Before=41951, After=41555, chg -0.94% Signed-off-by: Konrad Dybcio Acked-by: Stephen Boyd Acked-by: Georgi Djakov Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-18-09c78c175546@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-smd-rpm.c | 280 +++++++++++++++++------------------------ 1 file changed, 116 insertions(+), 164 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 6e7f0438e8b8..997c2b89a5d1 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -167,12 +167,20 @@ struct clk_smd_rpm { struct rpm_smd_clk_desc { struct clk_smd_rpm **clks; size_t num_clks; + + /* + * Interconnect clocks are managed by the icc framework, this driver + * only kickstarts them so that they don't get gated between + * clk_smd_rpm_enable_scaling() and interconnect driver initialization. + */ + const struct clk_smd_rpm ** const icc_clks; + size_t num_icc_clks; bool scaling_before_handover; }; static DEFINE_MUTEX(rpm_smd_clk_lock); -static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) +static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r) { int ret; struct clk_smd_rpm_req req = { @@ -498,13 +506,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); +static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, +}; + +static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, +}; + +static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_sysmmnoc_clk, +}; + +static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_ocmemgx_clk, +}; + +static const struct clk_smd_rpm *msm8996_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_branch_aggre1_noc_clk, + &clk_smd_rpm_branch_aggre2_noc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static const struct clk_smd_rpm *msm8998_icc_clks[] = { + &clk_smd_rpm_aggre1_noc_clk, + &clk_smd_rpm_aggre2_noc_clk, + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static const struct clk_smd_rpm *sdm660_icc_clks[] = { + &clk_smd_rpm_aggre2_noc_clk, + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_cnoc_clk, + &clk_smd_rpm_mmnrt_clk, + &clk_smd_rpm_mmrt_clk, + &clk_smd_rpm_qup_clk, + &clk_smd_rpm_bus_2_snoc_clk, +}; + static struct clk_smd_rpm *msm8909_clks[] = { - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, @@ -530,15 +594,11 @@ static struct clk_smd_rpm *msm8909_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { .clks = msm8909_clks, .num_clks = ARRAY_SIZE(msm8909_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -562,21 +622,15 @@ static struct clk_smd_rpm *msm8916_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { .clks = msm8916_clks, .num_clks = ARRAY_SIZE(msm8916_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8917_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -596,19 +650,13 @@ static struct clk_smd_rpm *msm8917_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { .clks = msm8917_clks, .num_clks = ARRAY_SIZE(msm8917_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8936_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -632,25 +680,17 @@ static struct clk_smd_rpm *msm8936_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { .clks = msm8936_clks, .num_clks = ARRAY_SIZE(msm8936_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8974_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, @@ -684,20 +724,14 @@ static struct clk_smd_rpm *msm8974_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .clks = msm8974_clks, .num_clks = ARRAY_SIZE(msm8974_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), .scaling_before_handover = true, }; static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -718,24 +752,15 @@ static struct clk_smd_rpm *msm8976_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { .clks = msm8976_clks, - .num_clks = ARRAY_SIZE(msm8976_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, @@ -777,23 +802,15 @@ static struct clk_smd_rpm *msm8992_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { .clks = msm8992_clks, .num_clks = ARRAY_SIZE(msm8992_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), }; static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, @@ -837,29 +854,17 @@ static struct clk_smd_rpm *msm8994_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { .clks = msm8994_clks, .num_clks = ARRAY_SIZE(msm8994_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), }; static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -891,6 +896,8 @@ static struct clk_smd_rpm *msm8996_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .clks = msm8996_clks, .num_clks = ARRAY_SIZE(msm8996_clks), + .icc_clks = msm8996_icc_clks, + .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks), }; static struct clk_smd_rpm *qcs404_clks[] = { @@ -919,19 +926,15 @@ static struct clk_smd_rpm *qcs404_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .clks = qcs404_clks, .num_clks = ARRAY_SIZE(qcs404_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, @@ -954,12 +957,6 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, - [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, @@ -979,27 +976,19 @@ static struct clk_smd_rpm *msm8998_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .clks = msm8998_clks, .num_clks = ARRAY_SIZE(msm8998_clks), + .icc_clks = msm8998_icc_clks, + .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks), }; static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, @@ -1025,15 +1014,13 @@ static struct clk_smd_rpm *sdm660_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { .clks = sdm660_clks, .num_clks = ARRAY_SIZE(sdm660_clks), + .icc_clks = sdm660_icc_clks, + .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks), }; static struct clk_smd_rpm *mdm9607_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, @@ -1047,21 +1034,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { .clks = mdm9607_clks, .num_clks = ARRAY_SIZE(mdm9607_clks), + .icc_clks = bimc_pcnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks), }; static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -1083,23 +1064,19 @@ static struct clk_smd_rpm *msm8953_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { .clks = msm8953_clks, .num_clks = ARRAY_SIZE(msm8953_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, @@ -1110,12 +1087,6 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1125,34 +1096,24 @@ static struct clk_smd_rpm *sm6125_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { .clks = sm6125_clks, .num_clks = ARRAY_SIZE(sm6125_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; /* SM6115 */ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1166,27 +1127,17 @@ static struct clk_smd_rpm *sm6115_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { .clks = sm6115_clks, .num_clks = ARRAY_SIZE(sm6115_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1203,31 +1154,21 @@ static struct clk_smd_rpm *sm6375_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { .clks = sm6375_clks, .num_clks = ARRAY_SIZE(sm6375_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1249,6 +1190,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { .clks = qcm2290_clks, .num_clks = ARRAY_SIZE(qcm2290_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static const struct of_device_id rpm_smd_clk_match_table[] = { @@ -1332,6 +1275,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) goto err; } + for (i = 0; i < desc->num_icc_clks; i++) { + if (!desc->icc_clks[i]) + continue; + + ret = clk_smd_rpm_handoff(desc->icc_clks[i]); + if (ret) + goto err; + } + if (!desc->scaling_before_handover) { ret = clk_smd_rpm_enable_scaling(); if (ret) -- cgit v1.2.3 From c948ff727e25297f3a703eb5349dd66aabf004e4 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:28:55 +0200 Subject: clk: qcom: camcc-sc7180: fix async resume during probe To make sure that the controller is runtime resumed and its power domain is enabled before accessing its registers during probe, the synchronous runtime PM interface must be used. Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Cc: stable@vger.kernel.org # 5.11 Cc: Stephen Boyd Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/camcc-sc7180.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index 8a4ba7a19ed1..6f56bdbf0204 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -1664,7 +1664,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev) return ret; } - ret = pm_runtime_get(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret) return ret; -- cgit v1.2.3 From b0f3d01bda6c3f6f811e70f76d2040ae81f64565 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:28:56 +0200 Subject: clk: qcom: dispcc-sm8450: fix runtime PM imbalance on probe errors Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Cc: stable@vger.kernel.org # 6.1 Cc: Dmitry Baryshkov Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm8450.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index adbfd30bfc96..84db4ff5485a 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1776,8 +1776,10 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) return ret; regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err_put_rpm; + } clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); @@ -1792,9 +1794,16 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); + if (ret) + goto err_put_rpm; pm_runtime_put(&pdev->dev); + return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + return ret; } -- cgit v1.2.3 From acaf1b3296a504d4a61b685f78baae771421608d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:28:57 +0200 Subject: clk: qcom: dispcc-sm8550: fix runtime PM imbalance on probe errors Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Cc: stable@vger.kernel.org # 6.3 Cc: Neil Armstrong Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm8550.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 1e5a11081860..b2fae9001ff2 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1761,8 +1761,10 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) return ret; regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err_put_rpm; + } clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); @@ -1777,9 +1779,16 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); + if (ret) + goto err_put_rpm; pm_runtime_put(&pdev->dev); + return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + return ret; } -- cgit v1.2.3 From 10192ab375c39c58d39cba028d9685cefe1ca3c2 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:28:58 +0200 Subject: clk: qcom: gcc-sc8280xp: fix runtime PM imbalance on probe errors Make sure to decrement the runtime PM usage count before returning in case RCG dynamic frequency switch initialisation fails. Fixes: 2a541abd9837 ("clk: qcom: gcc-sc8280xp: Add runtime PM") Cc: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc8280xp.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 1fb6ffac730c..ac6f8c0c1ccb 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7539,8 +7539,8 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc); if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); + ret = PTR_ERR(regmap); + goto err_put_rpm; } /* @@ -7561,11 +7561,19 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) - return ret; + goto err_put_rpm; ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap); + if (ret) + goto err_put_rpm; + pm_runtime_put(&pdev->dev); + return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + return ret; } -- cgit v1.2.3 From 66af5339d4f8e20c6d89a490570bd94d40f1a7f6 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:28:59 +0200 Subject: clk: qcom: lpasscc-sc7280: fix missing resume during probe Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: stable@vger.kernel.org # 5.16 Cc: Taniya Das Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/lpasscc-sc7280.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c index 0df2b29e95e3..e6b815aec46a 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -118,9 +118,13 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) ret = pm_clk_add(&pdev->dev, "iface"); if (ret < 0) { dev_err(&pdev->dev, "failed to acquire iface clock\n"); - goto destroy_pm_clk; + goto err_destroy_pm_clk; } + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + goto err_destroy_pm_clk; + if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) { lpass_regmap_config.name = "qdsp6ss"; lpass_regmap_config.max_register = 0x3f; @@ -128,7 +132,7 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) ret = qcom_cc_probe_by_index(pdev, 0, desc); if (ret) - goto destroy_pm_clk; + goto err_put_rpm; } lpass_regmap_config.name = "top_cc"; @@ -137,11 +141,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) ret = qcom_cc_probe_by_index(pdev, 1, desc); if (ret) - goto destroy_pm_clk; + goto err_put_rpm; + + pm_runtime_put(&pdev->dev); return 0; -destroy_pm_clk: +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); +err_destroy_pm_clk: pm_clk_destroy(&pdev->dev); return ret; -- cgit v1.2.3 From 97112c83f4671a4a722f99a53be4e91fac4091bc Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:29:00 +0200 Subject: clk: qcom: q6sstop-qcs404: fix missing resume during probe Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef2738db0 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: stable@vger.kernel.org # 5.5 Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/q6sstop-qcs404.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/q6sstop-qcs404.c b/drivers/clk/qcom/q6sstop-qcs404.c index 780074e05841..26e2d63614ac 100644 --- a/drivers/clk/qcom/q6sstop-qcs404.c +++ b/drivers/clk/qcom/q6sstop-qcs404.c @@ -174,21 +174,32 @@ static int q6sstopcc_qcs404_probe(struct platform_device *pdev) return ret; } + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + q6sstop_regmap_config.name = "q6sstop_tcsr"; desc = &tcsr_qcs404_desc; ret = qcom_cc_probe_by_index(pdev, 1, desc); if (ret) - return ret; + goto err_put_rpm; q6sstop_regmap_config.name = "q6sstop_cc"; desc = &q6sstop_qcs404_desc; ret = qcom_cc_probe_by_index(pdev, 0, desc); if (ret) - return ret; + goto err_put_rpm; + + pm_runtime_put(&pdev->dev); return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + + return ret; } static const struct dev_pm_ops q6sstopcc_pm_ops = { -- cgit v1.2.3 From e2349da0fa7ca822cda72f427345b95795358fe7 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:29:01 +0200 Subject: clk: qcom: mss-sc7180: fix missing resume during probe Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c4097 ("clk: qcom: Add modem clock controller driver for SC7180") Cc: stable@vger.kernel.org # 5.7 Cc: Taniya Das Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-8-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/mss-sc7180.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c index 5a1407440662..d106bc65470e 100644 --- a/drivers/clk/qcom/mss-sc7180.c +++ b/drivers/clk/qcom/mss-sc7180.c @@ -87,11 +87,22 @@ static int mss_sc7180_probe(struct platform_device *pdev) return ret; } + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + ret = qcom_cc_probe(pdev, &mss_sc7180_desc); if (ret < 0) - return ret; + goto err_put_rpm; + + pm_runtime_put(&pdev->dev); return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + + return ret; } static const struct dev_pm_ops mss_sc7180_pm_ops = { -- cgit v1.2.3 From a9f71a033587c9074059132d34c74eabbe95ef26 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Jul 2023 15:29:02 +0200 Subject: clk: qcom: turingcc-qcs404: fix missing resume during probe Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC") Cc: stable@vger.kernel.org # 5.2 Cc: Bjorn Andersson Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/turingcc-qcs404.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c index 43184459228f..2cd288d6c3e4 100644 --- a/drivers/clk/qcom/turingcc-qcs404.c +++ b/drivers/clk/qcom/turingcc-qcs404.c @@ -125,11 +125,22 @@ static int turingcc_probe(struct platform_device *pdev) return ret; } + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + ret = qcom_cc_probe(pdev, &turingcc_desc); if (ret < 0) - return ret; + goto err_put_rpm; + + pm_runtime_put(&pdev->dev); return 0; + +err_put_rpm: + pm_runtime_put_sync(&pdev->dev); + + return ret; } static const struct dev_pm_ops turingcc_pm_ops = { -- cgit v1.2.3 From 20e1d75bc043c5ec1fd8f5169fde17db89eb11c3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 25 Jul 2023 10:51:56 +0200 Subject: clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCs The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sc8280xp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 167470beb369..30f636b9f0ec 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3057,7 +3057,7 @@ static struct gdsc disp0_mdss_gdsc = { .name = "disp0_mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct gdsc disp1_mdss_gdsc = { @@ -3069,7 +3069,7 @@ static struct gdsc disp1_mdss_gdsc = { .name = "disp1_mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct gdsc disp0_mdss_int2_gdsc = { @@ -3081,7 +3081,7 @@ static struct gdsc disp0_mdss_int2_gdsc = { .name = "disp0_mdss_int2_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct gdsc disp1_mdss_int2_gdsc = { @@ -3093,7 +3093,7 @@ static struct gdsc disp1_mdss_int2_gdsc = { .name = "disp1_mdss_int2_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct gdsc *disp0_cc_sc8280xp_gdscs[] = { -- cgit v1.2.3 From e5e527d1ed02fec0310d1e1574557781360e4418 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 31 Jul 2023 21:21:33 +0200 Subject: clk: qcom: videocc-sm8350: Add SC8280XP support SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230703-topic-8280_videocc-v2-2-c88269806269@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8350.c | 42 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index b148877fc73d..7246f3c99492 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -41,6 +41,10 @@ static const struct pll_vco lucid_5lpe_vco[] = { { 249600000, 1750000000, 0 }, }; +static const struct pll_vco lucid_5lpe_vco_8280xp[] = { + { 249600000, 1800000000, 0 }, +}; + static const struct alpha_pll_config video_pll0_config = { .l = 0x25, .alpha = 0x8000, @@ -159,6 +163,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_8280xp[] = { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0xb94, .mnd_width = 0, @@ -181,6 +195,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_8280xp[] = { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0xbb4, .mnd_width = 0, @@ -499,6 +522,7 @@ static struct qcom_cc_desc video_cc_sm8350_desc = { static int video_cc_sm8350_probe(struct platform_device *pdev) { + u32 video_cc_xo_clk_cbcr = 0xeec; struct regmap *regmap; int ret; @@ -510,6 +534,21 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) if (ret) return ret; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8280xp-videocc")) { + video_cc_sleep_clk_src.cmd_rcgr = 0xf38; + video_cc_sleep_clk.halt_reg = 0xf58; + video_cc_sleep_clk.clkr.enable_reg = 0xf58; + video_cc_xo_clk_src.cmd_rcgr = 0xf14; + video_cc_xo_clk_cbcr = 0xf34; + + video_pll0.vco_table = video_pll1.vco_table = lucid_5lpe_vco_8280xp; + /* No change, but assign it for completeness */ + video_pll0.num_vco = video_pll1.num_vco = ARRAY_SIZE(lucid_5lpe_vco_8280xp); + + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_8280xp; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_8280xp; + } + regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc); if (IS_ERR(regmap)) { pm_runtime_put(&pdev->dev); @@ -525,7 +564,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) * video_cc_xo_clk */ regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); @@ -534,6 +573,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) } static const struct of_device_id video_cc_sm8350_match_table[] = { + { .compatible = "qcom,sc8280xp-videocc" }, { .compatible = "qcom,sm8350-videocc" }, { } }; -- cgit v1.2.3 From 9f08d334969ba3e2ced6769a13372b153256b2d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:19 +0300 Subject: dt-bindings: clock: drop qcom,lcc-mdm9615 header file The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/lcc-mdm9615.c | 2 +- include/dt-bindings/clock/qcom,lcc-mdm9615.h | 44 ---------------------------- 2 files changed, 1 insertion(+), 45 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,lcc-mdm9615.h (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c index 8d243e880d95..c17caffdc349 100644 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ b/drivers/clk/qcom/lcc-mdm9615.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include "common.h" #include "clk-regmap.h" diff --git a/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/include/dt-bindings/clock/qcom,lcc-mdm9615.h deleted file mode 100644 index 299338ee1d88..000000000000 --- a/include/dt-bindings/clock/qcom,lcc-mdm9615.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H -#define _DT_BINDINGS_CLK_LCC_MDM9615_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif -- cgit v1.2.3 From 6bab5dab6ed3c2b0eb9112f288ce05276083b492 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:21 +0300 Subject: clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-mdm9615.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 8bed02a748ab..fb5c1244fb97 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -875,7 +875,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = { .hw.init = &(struct clk_init_data){ .name = "sdc2_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", .parent_names = gcc_cxo_pll14, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, -- cgit v1.2.3 From bac4675a4d1b80cd69eef311c6c112a88e5845f5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:22 +0300 Subject: clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 15 +- drivers/clk/qcom/Makefile | 1 - drivers/clk/qcom/lcc-mdm9615.c | 572 ----------------------------------------- drivers/clk/qcom/lcc-msm8960.c | 19 +- 4 files changed, 18 insertions(+), 589 deletions(-) delete mode 100644 drivers/clk/qcom/lcc-mdm9615.c (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 263e55d75e3f..b41da59b25c0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -247,11 +247,11 @@ config MSM_GCC_8960 i2c, USB, SD/eMMC, SATA, PCIe, etc. config MSM_LCC_8960 - tristate "APQ8064/MSM8960 LPASS Clock Controller" + tristate "APQ8064/MSM8960/MDM9650 LPASS Clock Controller" depends on ARM || COMPILE_TEST - select MSM_GCC_8960 help - Support for the LPASS clock controller on apq8064/msm8960 devices. + Support for the LPASS clock controller on apq8064/msm8960/mdm9650 + devices. Say Y if you want to use audio devices such as i2s, pcm, SLIMBus, etc. @@ -271,15 +271,6 @@ config MDM_GCC_9615 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. -config MDM_LCC_9615 - tristate "MDM9615 LPASS Clock Controller" - depends on ARM || COMPILE_TEST - select MDM_GCC_9615 - help - Support for the LPASS clock controller on mdm9615 devices. - Say Y if you want to use audio devices such as i2s, pcm, - SLIMBus, etc. - config MSM_MMCC_8960 tristate "MSM8960 Multimedia Clock Controller" depends on ARM || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e6e294274c35..b5553be134f0 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o -obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c deleted file mode 100644 index c17caffdc349..000000000000 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ /dev/null @@ -1,572 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-regmap.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" - -static struct clk_pll pll4 = { - .l_reg = 0x4, - .m_reg = 0x8, - .n_reg = 0xc, - .config_reg = 0x14, - .mode_reg = 0x0, - .status_reg = 0x18, - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll4", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -enum { - P_CXO, - P_PLL4, -}; - -static const struct parent_map lcc_cxo_pll4_map[] = { - { P_CXO, 0 }, - { P_PLL4, 2 } -}; - -static const char * const lcc_cxo_pll4[] = { - "cxo", - "pll4_vote", -}; - -static struct freq_tbl clk_tbl_aif_osr_492[] = { - { 512000, P_PLL4, 4, 1, 240 }, - { 768000, P_PLL4, 4, 1, 160 }, - { 1024000, P_PLL4, 4, 1, 120 }, - { 1536000, P_PLL4, 4, 1, 80 }, - { 2048000, P_PLL4, 4, 1, 60 }, - { 3072000, P_PLL4, 4, 1, 40 }, - { 4096000, P_PLL4, 4, 1, 30 }, - { 6144000, P_PLL4, 4, 1, 20 }, - { 8192000, P_PLL4, 4, 1, 15 }, - { 12288000, P_PLL4, 4, 1, 10 }, - { 24576000, P_PLL4, 4, 1, 5 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct freq_tbl clk_tbl_aif_osr_393[] = { - { 512000, P_PLL4, 4, 1, 192 }, - { 768000, P_PLL4, 4, 1, 128 }, - { 1024000, P_PLL4, 4, 1, 96 }, - { 1536000, P_PLL4, 4, 1, 64 }, - { 2048000, P_PLL4, 4, 1, 48 }, - { 3072000, P_PLL4, 4, 1, 32 }, - { 4096000, P_PLL4, 4, 1, 24 }, - { 6144000, P_PLL4, 4, 1, 16 }, - { 8192000, P_PLL4, 4, 1, 12 }, - { 12288000, P_PLL4, 4, 1, 8 }, - { 24576000, P_PLL4, 4, 1, 4 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct clk_rcg mi2s_osr_src = { - .ns_reg = 0x48, - .md_reg = 0x4c, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 24, - .m_val_shift = 8, - .width = 8, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_aif_osr_393, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static const char * const lcc_mi2s_parents[] = { - "mi2s_osr_src", -}; - -static struct clk_branch mi2s_osr_clk = { - .halt_reg = 0x50, - .halt_bit = 1, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_clk", - .parent_names = lcc_mi2s_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_div mi2s_div_clk = { - .reg = 0x48, - .shift = 10, - .width = 4, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_div_clk", - .parent_names = lcc_mi2s_parents, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, - }, -}; - -static struct clk_branch mi2s_bit_div_clk = { - .halt_reg = 0x50, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_div_clk", - .parent_names = (const char *[]){ "mi2s_div_clk" }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_mux mi2s_bit_clk = { - .reg = 0x48, - .shift = 14, - .width = 1, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_clk", - .parent_names = (const char *[]){ - "mi2s_bit_div_clk", - "mi2s_codec_clk", - }, - .num_parents = 2, - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \ -static struct clk_rcg prefix##_osr_src = { \ - .ns_reg = _ns, \ - .md_reg = _md, \ - .mn = { \ - .mnctr_en_bit = 8, \ - .mnctr_reset_bit = 7, \ - .mnctr_mode_shift = 5, \ - .n_val_shift = 24, \ - .m_val_shift = 8, \ - .width = 8, \ - }, \ - .p = { \ - .pre_div_shift = 3, \ - .pre_div_width = 2, \ - }, \ - .s = { \ - .src_sel_shift = 0, \ - .parent_map = lcc_cxo_pll4_map, \ - }, \ - .freq_tbl = clk_tbl_aif_osr_393, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(9), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_osr_src", \ - .parent_names = lcc_cxo_pll4, \ - .num_parents = 2, \ - .ops = &clk_rcg_ops, \ - .flags = CLK_SET_RATE_GATE, \ - }, \ - }, \ -}; \ - \ -static const char * const lcc_##prefix##_parents[] = { \ - #prefix "_osr_src", \ -}; \ - \ -static struct clk_branch prefix##_osr_clk = { \ - .halt_reg = hr, \ - .halt_bit = 1, \ - .halt_check = BRANCH_HALT_ENABLE, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(21), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_osr_clk", \ - .parent_names = lcc_##prefix##_parents, \ - .num_parents = 1, \ - .ops = &clk_branch_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -}; \ - \ -static struct clk_regmap_div prefix##_div_clk = { \ - .reg = _ns, \ - .shift = 10, \ - .width = 8, \ - .clkr = { \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_div_clk", \ - .parent_names = lcc_##prefix##_parents, \ - .num_parents = 1, \ - .ops = &clk_regmap_div_ops, \ - }, \ - }, \ -}; \ - \ -static struct clk_branch prefix##_bit_div_clk = { \ - .halt_reg = hr, \ - .halt_bit = 0, \ - .halt_check = BRANCH_HALT_ENABLE, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(19), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_bit_div_clk", \ - .parent_names = (const char *[]){ \ - #prefix "_div_clk" \ - }, \ - .num_parents = 1, \ - .ops = &clk_branch_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -}; \ - \ -static struct clk_regmap_mux prefix##_bit_clk = { \ - .reg = _ns, \ - .shift = 18, \ - .width = 1, \ - .clkr = { \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_bit_clk", \ - .parent_names = (const char *[]){ \ - #prefix "_bit_div_clk", \ - #prefix "_codec_clk", \ - }, \ - .num_parents = 2, \ - .ops = &clk_regmap_mux_closest_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -} - -CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68); -CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80); -CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74); -CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c); - -static struct freq_tbl clk_tbl_pcm_492[] = { - { 256000, P_PLL4, 4, 1, 480 }, - { 512000, P_PLL4, 4, 1, 240 }, - { 768000, P_PLL4, 4, 1, 160 }, - { 1024000, P_PLL4, 4, 1, 120 }, - { 1536000, P_PLL4, 4, 1, 80 }, - { 2048000, P_PLL4, 4, 1, 60 }, - { 3072000, P_PLL4, 4, 1, 40 }, - { 4096000, P_PLL4, 4, 1, 30 }, - { 6144000, P_PLL4, 4, 1, 20 }, - { 8192000, P_PLL4, 4, 1, 15 }, - { 12288000, P_PLL4, 4, 1, 10 }, - { 24576000, P_PLL4, 4, 1, 5 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct freq_tbl clk_tbl_pcm_393[] = { - { 256000, P_PLL4, 4, 1, 384 }, - { 512000, P_PLL4, 4, 1, 192 }, - { 768000, P_PLL4, 4, 1, 128 }, - { 1024000, P_PLL4, 4, 1, 96 }, - { 1536000, P_PLL4, 4, 1, 64 }, - { 2048000, P_PLL4, 4, 1, 48 }, - { 3072000, P_PLL4, 4, 1, 32 }, - { 4096000, P_PLL4, 4, 1, 24 }, - { 6144000, P_PLL4, 4, 1, 16 }, - { 8192000, P_PLL4, 4, 1, 12 }, - { 12288000, P_PLL4, 4, 1, 8 }, - { 24576000, P_PLL4, 4, 1, 4 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct clk_rcg pcm_src = { - .ns_reg = 0x54, - .md_reg = 0x58, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 16, - .m_val_shift = 16, - .width = 16, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_pcm_393, - .clkr = { - .enable_reg = 0x54, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcm_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static struct clk_branch pcm_clk_out = { - .halt_reg = 0x5c, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x54, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk_out", - .parent_names = (const char *[]){ "pcm_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_mux pcm_clk = { - .reg = 0x54, - .shift = 10, - .width = 1, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk", - .parent_names = (const char *[]){ - "pcm_clk_out", - "pcm_codec_clk", - }, - .num_parents = 2, - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_rcg slimbus_src = { - .ns_reg = 0xcc, - .md_reg = 0xd0, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 24, - .m_val_shift = 8, - .width = 8, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_aif_osr_393, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "slimbus_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static const char * const lcc_slimbus_parents[] = { - "slimbus_src", -}; - -static struct clk_branch audio_slimbus_clk = { - .halt_reg = 0xd4, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "audio_slimbus_clk", - .parent_names = lcc_slimbus_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_branch sps_slimbus_clk = { - .halt_reg = 0xd4, - .halt_bit = 1, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "sps_slimbus_clk", - .parent_names = lcc_slimbus_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap *lcc_mdm9615_clks[] = { - [PLL4] = &pll4.clkr, - [MI2S_OSR_SRC] = &mi2s_osr_src.clkr, - [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr, - [MI2S_DIV_CLK] = &mi2s_div_clk.clkr, - [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr, - [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr, - [PCM_SRC] = &pcm_src.clkr, - [PCM_CLK_OUT] = &pcm_clk_out.clkr, - [PCM_CLK] = &pcm_clk.clkr, - [SLIMBUS_SRC] = &slimbus_src.clkr, - [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr, - [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr, - [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr, - [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr, - [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr, - [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr, - [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr, - [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr, - [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr, - [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr, - [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr, - [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr, - [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr, - [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr, - [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr, - [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr, - [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr, - [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr, - [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr, - [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr, - [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr, - [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr, -}; - -static const struct regmap_config lcc_mdm9615_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xfc, - .fast_io = true, -}; - -static const struct qcom_cc_desc lcc_mdm9615_desc = { - .config = &lcc_mdm9615_regmap_config, - .clks = lcc_mdm9615_clks, - .num_clks = ARRAY_SIZE(lcc_mdm9615_clks), -}; - -static const struct of_device_id lcc_mdm9615_match_table[] = { - { .compatible = "qcom,lcc-mdm9615" }, - { } -}; -MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table); - -static int lcc_mdm9615_probe(struct platform_device *pdev) -{ - u32 val; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Use the correct frequency plan depending on speed of PLL4 */ - regmap_read(regmap, 0x4, &val); - if (val == 0x12) { - slimbus_src.freq_tbl = clk_tbl_aif_osr_492; - mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492; - codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; - spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; - codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; - spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; - pcm_src.freq_tbl = clk_tbl_pcm_492; - } - /* Enable PLL4 source on the LPASS Primary PLL Mux */ - regmap_write(regmap, 0xc4, 0x1); - - return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap); -} - -static struct platform_driver lcc_mdm9615_driver = { - .probe = lcc_mdm9615_probe, - .driver = { - .name = "lcc-mdm9615", - .of_match_table = lcc_mdm9615_match_table, - }, -}; -module_platform_driver(lcc_mdm9615_driver); - -MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:lcc-mdm9615"); diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c index 3926184cc91b..5e2465f73722 100644 --- a/drivers/clk/qcom/lcc-msm8960.c +++ b/drivers/clk/qcom/lcc-msm8960.c @@ -23,6 +23,10 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +struct clk_parent_data pxo_parent_data = { + .fw_name = "pxo", .name = "pxo_board", +}; + static struct clk_pll pll4 = { .l_reg = 0x4, .m_reg = 0x8, @@ -33,9 +37,7 @@ static struct clk_pll pll4 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll4", - .parent_data = (const struct clk_parent_data[]){ - { .fw_name = "pxo", .name = "pxo_board" }, - }, + .parent_data = &pxo_parent_data, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -51,7 +53,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const struct clk_parent_data lcc_pxo_pll4[] = { +static struct clk_parent_data lcc_pxo_pll4[] = { { .fw_name = "pxo", .name = "pxo_board" }, { .fw_name = "pll4_vote", .name = "pll4_vote" }, }; @@ -444,6 +446,7 @@ static const struct qcom_cc_desc lcc_msm8960_desc = { static const struct of_device_id lcc_msm8960_match_table[] = { { .compatible = "qcom,lcc-msm8960" }, { .compatible = "qcom,lcc-apq8064" }, + { .compatible = "qcom,lcc-mdm9615" }, { } }; MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table); @@ -453,6 +456,14 @@ static int lcc_msm8960_probe(struct platform_device *pdev) u32 val; struct regmap *regmap; + /* patch for the cxo <-> pxo difference */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) { + pxo_parent_data.fw_name = "cxo"; + pxo_parent_data.name = "cxo_board"; + lcc_pxo_pll4[0].fw_name = "cxo"; + lcc_pxo_pll4[0].name = "cxo_board"; + } + regmap = qcom_cc_map(pdev, &lcc_msm8960_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); -- cgit v1.2.3 From 1583694bb4eaf186f17131dbc1b83d6057d2749b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:23 +0300 Subject: clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230512211727.3445575-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-mdm9615.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index fb5c1244fb97..2f921891008d 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_names = (const char *[]){ "pll0" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, -- cgit v1.2.3 From c01c9ed3aba90e509ecffd5f99987e93898af460 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:24 +0300 Subject: clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230512211727.3445575-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-mdm9615.c | 206 +++++++++++++++++++++++++---------------- 1 file changed, 124 insertions(+), 82 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 2f921891008d..458c18b639db 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -37,6 +37,25 @@ static struct clk_fixed_factor cxo = { }, }; +enum { + DT_CXO, + DT_PLL4, +}; + +enum { + P_CXO, + P_PLL8, + P_PLL14, +}; + +static const struct parent_map gcc_cxo_map[] = { + { P_CXO, 0 }, +}; + +static const struct clk_parent_data gcc_cxo[] = { + { .index = DT_CXO, .name = "cxo_board" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -47,8 +66,8 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -58,7 +77,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]) { + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -69,7 +90,9 @@ static struct clk_regmap pll4_vote = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "pll4_vote", - .parent_names = (const char *[]){ "pll4" }, + .parent_data = &(const struct clk_parent_data) { + .index = DT_PLL4, .name = "pll4", + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -85,8 +108,8 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -96,7 +119,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]) { + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -112,8 +137,8 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -123,26 +148,22 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]) { + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, }; -enum { - P_CXO, - P_PLL8, - P_PLL14, -}; - static const struct parent_map gcc_cxo_pll8_map[] = { { P_CXO, 0 }, { P_PLL8, 3 } }; -static const char * const gcc_cxo_pll8[] = { - "cxo", - "pll8_vote", +static const struct clk_parent_data gcc_cxo_pll8[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_cxo_pll14_map[] = { @@ -150,17 +171,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = { { P_PLL14, 4 } }; -static const char * const gcc_cxo_pll14[] = { - "cxo", - "pll14_vote", -}; - -static const struct parent_map gcc_cxo_map[] = { - { P_CXO, 0 }, -}; - -static const char * const gcc_cxo[] = { - "cxo", +static const struct clk_parent_data gcc_cxo_pll14[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll14_vote.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -206,7 +219,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -222,8 +235,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -257,7 +270,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -273,8 +286,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -308,7 +321,7 @@ static struct clk_rcg gsbi3_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -324,8 +337,8 @@ static struct clk_branch gsbi3_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_clk", - .parent_names = (const char *[]){ - "gsbi3_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -359,7 +372,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -375,8 +388,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -410,7 +423,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -426,8 +439,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -473,7 +486,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -489,7 +502,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -522,7 +537,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -538,7 +553,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -571,7 +588,7 @@ static struct clk_rcg gsbi3_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -587,7 +604,9 @@ static struct clk_branch gsbi3_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_clk", - .parent_names = (const char *[]){ "gsbi3_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -620,7 +639,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -636,7 +655,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -669,7 +690,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -685,7 +706,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -724,7 +747,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -740,7 +763,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -773,7 +798,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -789,7 +814,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -822,7 +849,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -838,7 +865,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -874,7 +903,7 @@ static struct clk_rcg prng_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -890,7 +919,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]) { + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -936,7 +967,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -951,7 +982,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -984,7 +1017,7 @@ static struct clk_rcg sdc2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc2_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -999,7 +1032,9 @@ static struct clk_branch sdc2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc2_clk", - .parent_names = (const char *[]){ "sdc2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1037,7 +1072,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1053,7 +1088,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_xcvr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1086,7 +1123,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1102,8 +1139,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_clk", - .parent_names = - (const char *[]){ "usb_hsic_xcvr_fs_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1141,7 +1179,7 @@ static struct clk_rcg usb_hs1_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1156,8 +1194,9 @@ static struct clk_branch usb_hs1_system_clk = { .enable_reg = 0x36a4, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hs1_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hs1_system_clk", .ops = &clk_branch_ops, @@ -1196,7 +1235,7 @@ static struct clk_rcg usb_hsic_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1211,8 +1250,9 @@ static struct clk_branch usb_hsic_system_clk = { .enable_reg = 0x2b58, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hsic_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_system_clk", .ops = &clk_branch_ops, @@ -1251,7 +1291,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", - .parent_names = gcc_cxo_pll14, + .parent_data = gcc_cxo_pll14, .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1265,7 +1305,9 @@ static struct clk_branch usb_hsic_hsic_clk = { .enable_reg = 0x2b50, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "usb_hsic_hsic_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_hsic_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_hsic_clk", .ops = &clk_branch_ops, @@ -1281,8 +1323,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = { .enable_reg = 0x2b48, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .name = "usb_hsic_hsio_cal_clk", .ops = &clk_branch_ops, }, -- cgit v1.2.3 From a47fa46187cc2621fa29c7b89ccd4b1efa07a1eb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:25 +0300 Subject: clk: qcom: gcc-mdm9615: drop the cxo clock The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230512211727.3445575-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-mdm9615.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 458c18b639db..64d4f508e43a 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -26,17 +26,6 @@ #include "clk-branch.h" #include "reset.h" -static struct clk_fixed_factor cxo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "cxo", - .parent_names = (const char *[]){ "cxo_board" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - enum { DT_CXO, DT_PLL4, @@ -1623,10 +1612,6 @@ static struct clk_branch ebi2_aon_clk = { }, }; -static struct clk_hw *gcc_mdm9615_hws[] = { - &cxo.hw, -}; - static struct clk_regmap *gcc_mdm9615_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -1736,8 +1721,6 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = { .num_clks = ARRAY_SIZE(gcc_mdm9615_clks), .resets = gcc_mdm9615_resets, .num_resets = ARRAY_SIZE(gcc_mdm9615_resets), - .clk_hws = gcc_mdm9615_hws, - .num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws), }; static const struct of_device_id gcc_mdm9615_match_table[] = { -- cgit v1.2.3 From bc48641a68dcf9998c78248ce7e79d1a492463c1 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sat, 27 May 2023 12:39:34 +0300 Subject: clk: qcom: cbf-msm8996: Add support for MSM8996 Pro The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by: Yassine Oudjana Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-cbf-8996.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c index 1e23b734abb3..53f205a3f183 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -52,7 +52,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_STATUS] = 0x28, }; -static const struct alpha_pll_config cbfpll_config = { +static struct alpha_pll_config cbfpll_config = { .l = 72, .config_ctl_val = 0x200d4828, .config_ctl_hi_val = 0x006, @@ -141,7 +141,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, { struct clk_hw *parent; - if (req->rate < (DIV_THRESHOLD / 2)) + if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) return -EINVAL; if (req->rate < DIV_THRESHOLD) @@ -312,6 +312,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) /* Switch CBF to use the primary PLL */ regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); + if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) { + cbfpll_config.post_div_val = 0x3 << 8; + cbf_pll_postdiv.div = 4; + } + for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) { ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]); if (ret) @@ -342,6 +347,7 @@ static int qcom_msm8996_cbf_remove(struct platform_device *pdev) static const struct of_device_id qcom_msm8996_cbf_match_table[] = { { .compatible = "qcom,msm8996-cbf" }, + { .compatible = "qcom,msm8996pro-cbf" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table); -- cgit v1.2.3 From fd0b5ba87ad5709f0fd3d2bc4b7870494a75f96a Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 23 Jul 2023 21:05:02 +0200 Subject: clk: qcom: gcc-sc7180: Fix up gcc_sdcc2_apps_clk_src Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: David Wronek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230723190725.1619193-2-davidwronek@gmail.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc7180.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index cef3c77564cf..49f36e1df4fa 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -651,6 +651,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .flags = CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From e39d0fa7309bebdc19218276279b9f119d4e9f2b Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 3 Aug 2023 16:21:25 +0800 Subject: clk: qcom: lcc-msm8960: change pxo_parent_data to static The pxo_parent_data inroduced in commit bac4675a4d1b ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by: Yang Yingliang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803082125.521849-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/lcc-msm8960.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c index 5e2465f73722..d96767e1fbe9 100644 --- a/drivers/clk/qcom/lcc-msm8960.c +++ b/drivers/clk/qcom/lcc-msm8960.c @@ -23,7 +23,7 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" -struct clk_parent_data pxo_parent_data = { +static struct clk_parent_data pxo_parent_data = { .fw_name = "pxo", .name = "pxo_board", }; -- cgit v1.2.3 From 783cb693828ce487cf0bc6ad16cbcf2caae6f8d9 Mon Sep 17 00:00:00 2001 From: Patrick Whewell Date: Wed, 2 Aug 2023 14:04:00 -0700 Subject: clk: qcom: gcc-sm8250: Fix gcc_sdcc2_apps_clk_src GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Patrick Whewell Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20230802210359.408-1-patrick.whewell@sightlineapplications.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sm8250.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index b6cf4bc88d4d..d3c75bb55946 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -721,6 +721,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From b6bcd1c0c27e1f210228346e6d23a2ec0c263e8c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 1 Aug 2023 12:56:32 +0200 Subject: clk: qcom: fix some Kconfig corner cases The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b106fcab ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711be384 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a37969c ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Arnd Bergmann Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230801105718.3658612-1-arnd@kernel.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b41da59b25c0..04b55ab829d9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -986,6 +986,7 @@ config SM_GPUCC_8450 config SM_GPUCC_8550 tristate "SM8550 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8550 help Support for the graphics clock controller on SM8550 devices. @@ -1022,6 +1023,7 @@ config SM_VIDEOCC_8250 config SM_VIDEOCC_8350 tristate "SM8350 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8350 select QCOM_GDSC help @@ -1031,6 +1033,7 @@ config SM_VIDEOCC_8350 config SM_VIDEOCC_8550 tristate "SM8550 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8550 select QCOM_GDSC help @@ -1079,6 +1082,7 @@ config CLK_GFM_LPASS_SM8250 config SM_VIDEOCC_8450 tristate "SM8450 Video Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8450 select QCOM_GDSC help -- cgit v1.2.3 From 181b66ee7cdd824797fc99b53bec29cf5630a04f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 28 Jul 2023 09:57:38 +0200 Subject: clk: qcom: reset: Use the correct type of sleep/delay based on length Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b6781 ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-qcom_reset-v3-1-5958facd5db2@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/reset.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 0e914ec7aeae..e45e32804d2c 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -16,7 +16,8 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev); rcdev->ops->assert(rcdev, id); - udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ + fsleep(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ + rcdev->ops->deassert(rcdev, id); return 0; } -- cgit v1.2.3 From df04d166d1f346dbf740bbea64a3bed3e7f14c8d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 4 Aug 2023 16:09:30 +0200 Subject: clk: qcom: gcc-sm6350: Fix gcc_sdcc2_apps_clk_src GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230804-sm6350-sdcc2-v1-1-3d946927d37d@fairphone.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sm6350.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c index 9b4e4bb05963..cf4a7b6e0b23 100644 --- a/drivers/clk/qcom/gcc-sm6350.c +++ b/drivers/clk/qcom/gcc-sm6350.c @@ -641,6 +641,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .flags = CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From e3fdbef1bab8e372981c8cc4d8febbaa76c490b0 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 28 Jul 2023 14:03:08 +0530 Subject: clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Add support for the global clock controller found on IPQ5018 based devices. Acked-by: Konrad Dybcio Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Co-developed-by: Gokul Sriram Palanisamy Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5018.c | 3724 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 3733 insertions(+) create mode 100644 drivers/clk/qcom/gcc-ipq5018.c (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 04b55ab829d9..bd9bfb11b328 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -145,6 +145,14 @@ config IPQ_GCC_4019 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. +config IPQ_GCC_5018 + tristate "IPQ5018 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + help + Support for global clock controller on ipq5018 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, SD/eMMC, etc. + config IPQ_GCC_5332 tristate "IPQ5332 Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b5553be134f0..4790c8cca426 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o +obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c new file mode 100644 index 000000000000..313ff2281ca7 --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -0,0 +1,3724 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include + +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "reset.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE20_PHY0_PIPE_CLK, + DT_PCIE20_PHY1_PIPE_CLK, + DT_USB3_PHY0_CC_PIPE_CLK, + DT_GEPHY_RX_CLK, + DT_GEPHY_TX_CLK, + DT_UNIPHY_RX_CLK, + DT_UNIPHY_TX_CLK, +}; + +enum { + P_XO, + P_CORE_PI_SLEEP_CLK, + P_PCIE20_PHY0_PIPE, + P_PCIE20_PHY1_PIPE, + P_USB3PHY_0_PIPE, + P_GEPHY_RX, + P_GEPHY_TX, + P_UNIPHY_RX, + P_UNIPHY_TX, + P_GPLL0, + P_GPLL0_DIV2, + P_GPLL2, + P_GPLL4, + P_UBI32_PLL, +}; + +static const struct clk_parent_data gcc_xo_data[] = { + { .index = DT_XO }, +}; + +static const struct clk_parent_data gcc_sleep_clk_data[] = { + { .index = DT_SLEEP_CLK }, +}; + +static struct clk_alpha_pll gpll0_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gpll0_main", + .parent_data = gcc_xo_data, + .num_parents = ARRAY_SIZE(gcc_xo_data), + .ops = &clk_alpha_pll_stromer_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll2_main = { + .offset = 0x4a000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data) { + .name = "gpll2_main", + .parent_data = gcc_xo_data, + .num_parents = ARRAY_SIZE(gcc_xo_data), + .ops = &clk_alpha_pll_stromer_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4_main = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data) { + .name = "gpll4_main", + .parent_data = gcc_xo_data, + .num_parents = ARRAY_SIZE(gcc_xo_data), + .ops = &clk_alpha_pll_stromer_ops, + }, + }, +}; + +static struct clk_alpha_pll ubi32_pll_main = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data) { + .name = "ubi32_pll_main", + .parent_data = gcc_xo_data, + .num_parents = ARRAY_SIZE(gcc_xo_data), + .ops = &clk_alpha_pll_stromer_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpll0", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_alpha_pll_postdiv gpll2 = { + .offset = 0x4a000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpll2", + .parent_hws = (const struct clk_hw *[]) { + &gpll2_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_alpha_pll_postdiv gpll4 = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpll4", + .parent_hws = (const struct clk_hw *[]) { + &gpll4_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_alpha_pll_postdiv ubi32_pll = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "ubi32_pll", + .parent_hws = (const struct clk_hw *[]) { + &ubi32_pll_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor gpll0_out_main_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data) { + .name = "gpll0_out_main_div2", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_DIV2, 4 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { + { .index = DT_XO }, + { .hw = &gpll0_out_main_div2.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0_DIV2, 2 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = { + { .index = DT_XO }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_ubi32_gpll0_map[] = { + { P_XO, 0 }, + { P_UBI32_PLL, 1 }, + { P_GPLL0, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL2, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL2, 2 }, + { P_GPLL4, 3 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 2 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { + { P_XO, 0 }, + { P_GPLL0, 2 }, + { P_CORE_PI_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_DIV2, 4 }, + { P_CORE_PI_SLEEP_CLK, 6 }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { + { .index = DT_XO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL2, 2 }, + { P_GPLL0_DIV2, 4 }, +}; + +static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { + { .index = DT_XO }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = { + { P_XO, 0 }, + { P_GPLL4, 1 }, + { P_GPLL0, 2 }, + { P_GPLL0_DIV2, 4 }, +}; + +static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = { + { P_XO, 0 }, + { P_GPLL4, 1 }, + { P_GPLL0, 3 }, + { P_GPLL0_DIV2, 4 }, +}; + +static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = { + { .index = DT_XO }, + { .index = DT_GEPHY_RX_CLK }, + { .index = DT_GEPHY_TX_CLK }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = { + { P_XO, 0 }, + { P_GEPHY_RX, 1 }, + { P_GEPHY_TX, 2 }, + { P_UBI32_PLL, 3 }, + { P_GPLL0, 4 }, +}; + +static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = { + { .index = DT_XO }, + { .index = DT_GEPHY_TX_CLK }, + { .index = DT_GEPHY_RX_CLK }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = { + { P_XO, 0 }, + { P_GEPHY_TX, 1 }, + { P_GEPHY_RX, 2 }, + { P_UBI32_PLL, 3 }, + { P_GPLL0, 4 }, +}; + +static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY_RX_CLK }, + { .index = DT_UNIPHY_TX_CLK }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = { + { P_XO, 0 }, + { P_UNIPHY_RX, 1 }, + { P_UNIPHY_TX, 2 }, + { P_UBI32_PLL, 3 }, + { P_GPLL0, 4 }, +}; + +static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY_TX_CLK }, + { .index = DT_UNIPHY_RX_CLK }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = { + { P_XO, 0 }, + { P_UNIPHY_TX, 1 }, + { P_UNIPHY_RX, 2 }, + { P_UBI32_PLL, 3 }, + { P_GPLL0, 4 }, +}; + +static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = { + { .index = DT_PCIE20_PHY0_PIPE_CLK }, + { .index = DT_XO }, +}; + +static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { + { P_PCIE20_PHY0_PIPE, 0 }, + { P_XO, 2 }, +}; + +static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = { + { .index = DT_PCIE20_PHY1_PIPE_CLK }, + { .index = DT_XO }, +}; + +static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { + { P_PCIE20_PHY1_PIPE, 0 }, + { P_XO, 2 }, +}; + +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { + { .index = DT_USB3_PHY0_CC_PIPE_CLK }, + { .index = DT_XO }, +}; + +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { + { P_USB3PHY_0_PIPE, 0 }, + { P_XO, 2 }, +}; + +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 adss_pwm_clk_src = { + .cmd_rcgr = 0x1f008, + .freq_tbl = ftbl_adss_pwm_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "adss_pwm_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x0200c, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x03000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x04000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 2, 5), + F(4800000, P_XO, 5, 0, 0), + F(9600000, P_XO, 2, 4, 5), + F(16000000, P_GPLL0, 10, 1, 5), + F(24000000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x02024, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x03014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x04014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { + F(3686400, P_GPLL0_DIV2, 1, 144, 15625), + F(7372800, P_GPLL0_DIV2, 1, 288, 15625), + F(14745600, P_GPLL0_DIV2, 1, 576, 15625), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0, 16, 1, 2), + F(40000000, P_GPLL0, 1, 1, 20), + F(46400000, P_GPLL0, 1, 29, 500), + F(48000000, P_GPLL0, 1, 3, 50), + F(51200000, P_GPLL0, 1, 8, 125), + F(56000000, P_GPLL0, 1, 7, 100), + F(58982400, P_GPLL0, 1, 1152, 15625), + F(60000000, P_GPLL0, 1, 3, 40), + F(64000000, P_GPLL0, 10, 4, 5), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x02044, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_uart1_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x03034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "blsp1_uart2_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_crypto_clk_src[] = { + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 crypto_clk_src = { + .cmd_rcgr = 0x16004, + .freq_tbl = ftbl_crypto_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "crypto_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = { + F(2500000, P_GEPHY_TX, 5, 0, 0), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_GEPHY_TX, 5, 0, 0), + F(125000000, P_GEPHY_TX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gmac0_rx_clk_src = { + .cmd_rcgr = 0x68020, + .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map, + .hid_width = 5, + .freq_tbl = ftbl_gmac0_tx_clk_src, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gmac0_rx_clk_src", + .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gmac0_rx_div_clk_src = { + .reg = 0x68420, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "gmac0_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg2 gmac0_tx_clk_src = { + .cmd_rcgr = 0x68028, + .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map, + .hid_width = 5, + .freq_tbl = ftbl_gmac0_tx_clk_src, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gmac0_tx_clk_src", + .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gmac0_tx_div_clk_src = { + .reg = 0x68424, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "gmac0_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = { + F(2500000, P_UNIPHY_RX, 12.5, 0, 0), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY_RX, 1, 0, 0), + F(312500000, P_UNIPHY_RX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gmac1_rx_clk_src = { + .cmd_rcgr = 0x68030, + .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map, + .hid_width = 5, + .freq_tbl = ftbl_gmac1_rx_clk_src, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gmac1_rx_clk_src", + .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gmac1_rx_div_clk_src = { + .reg = 0x68430, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "gmac1_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = { + F(2500000, P_UNIPHY_TX, 12.5, 0, 0), + F(24000000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY_TX, 1, 0, 0), + F(312500000, P_UNIPHY_TX, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gmac1_tx_clk_src = { + .cmd_rcgr = 0x68038, + .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map, + .hid_width = 5, + .freq_tbl = ftbl_gmac1_tx_clk_src, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gmac1_tx_clk_src", + .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gmac1_tx_div_clk_src = { + .reg = 0x68434, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "gmac1_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl ftbl_gmac_clk_src[] = { + F(240000000, P_GPLL4, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gmac_clk_src = { + .cmd_rcgr = 0x68080, + .parent_map = gcc_xo_gpll0_gpll4_map, + .hid_width = 5, + .freq_tbl = ftbl_gmac_clk_src, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gmac_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gp_clk_src[] = { + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x08004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gp1_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x09004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gp2_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x0a004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gp3_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { + F(133333334, P_GPLL0, 6, 0, 0), + { } +}; + +struct clk_rcg2 lpass_axim_clk_src = { + .cmd_rcgr = 0x2e028, + .freq_tbl = ftbl_lpass_axim_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "lpass_axim_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_lpass_sway_clk_src[] = { + F(66666667, P_GPLL0, 12, 0, 0), + { } +}; + +struct clk_rcg2 lpass_sway_clk_src = { + .cmd_rcgr = 0x2e040, + .freq_tbl = ftbl_lpass_sway_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "lpass_sway_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = { + F(2000000, P_XO, 12, 0, 0), +}; + +static struct clk_rcg2 pcie0_aux_clk_src = { + .cmd_rcgr = 0x75020, + .freq_tbl = ftbl_pcie0_aux_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "pcie0_aux_clk_src", + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = { + F(240000000, P_GPLL4, 5, 0, 0), + { } +}; + +static struct clk_rcg2 pcie0_axi_clk_src = { + .cmd_rcgr = 0x75050, + .freq_tbl = ftbl_pcie0_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll4_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "pcie0_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 pcie1_aux_clk_src = { + .cmd_rcgr = 0x76020, + .freq_tbl = ftbl_pcie0_aux_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "pcie1_aux_clk_src", + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 pcie1_axi_clk_src = { + .cmd_rcgr = 0x76050, + .freq_tbl = ftbl_gp_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "pcie1_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_mux pcie0_pipe_clk_src = { + .reg = 0x7501c, + .shift = 8, + .width = 2, + .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "pcie0_pipe_clk_src", + .parent_data = gcc_pcie20_phy0_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_regmap_mux pcie1_pipe_clk_src = { + .reg = 0x7601c, + .shift = 8, + .width = 2, + .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "pcie1_pipe_clk_src", + .parent_data = gcc_pcie20_phy1_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { + F(100000000, P_GPLL0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 pcnoc_bfdcd_clk_src = { + .cmd_rcgr = 0x27000, + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "pcnoc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor pcnoc_clk_src = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data) { + .name = "pcnoc_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_qdss_at_clk_src[] = { + F(240000000, P_GPLL4, 5, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_at_clk_src = { + .cmd_rcgr = 0x2900c, + .freq_tbl = ftbl_qdss_at_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, + .clkr.hw.init = &(struct clk_init_data) { + .name = "qdss_at_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_stm_clk_src = { + .cmd_rcgr = 0x2902c, + .freq_tbl = ftbl_qdss_stm_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "qdss_stm_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { + F(266666667, P_GPLL0, 3, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_traceclkin_clk_src = { + .cmd_rcgr = 0x29048, + .freq_tbl = ftbl_qdss_traceclkin_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, + .clkr.hw.init = &(struct clk_init_data) { + .name = "qdss_traceclkin_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { + F(600000000, P_GPLL4, 2, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_tsctr_clk_src = { + .cmd_rcgr = 0x29064, + .freq_tbl = ftbl_qdss_tsctr_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, + .clkr.hw.init = &(struct clk_init_data) { + .name = "qdss_tsctr_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data) { + .name = "qdss_tsctr_div2_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor qdss_dap_sync_clk_src = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data) { + .name = "qdss_dap_sync_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor eud_at_clk_src = { + .mult = 1, + .div = 6, + .hw.init = &(struct clk_init_data) { + .name = "eud_at_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), +}; + +static struct clk_rcg2 qpic_io_macro_clk_src = { + .cmd_rcgr = 0x57010, + .freq_tbl = ftbl_qpic_io_macro_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "qpic_io_macro_clk_src", + .parent_data = gcc_xo_gpll0_gpll2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(143713, P_XO, 1, 1, 167), + F(400000, P_XO, 1, 1, 60), + F(24000000, P_XO, 1, 0, 0), + F(48000000, P_GPLL2, 12, 1, 2), + F(96000000, P_GPLL2, 12, 0, 0), + F(177777778, P_GPLL0, 1, 2, 9), + F(192000000, P_GPLL2, 6, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x42004, + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "sdcc1_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { + F(266666667, P_GPLL0, 3, 0, 0), + { } +}; + +static struct clk_rcg2 system_noc_bfdcd_clk_src = { + .cmd_rcgr = 0x26004, + .freq_tbl = ftbl_system_noc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "system_noc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor system_noc_clk_src = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data) { + .name = "system_noc_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_apss_axi_clk_src[] = { + F(400000000, P_GPLL0, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ubi0_axi_clk_src = { + .cmd_rcgr = 0x68088, + .freq_tbl = ftbl_apss_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "ubi0_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct freq_tbl ftbl_ubi0_core_clk_src[] = { + F(850000000, P_UBI32_PLL, 1, 0, 0), + F(1000000000, P_UBI32_PLL, 1, 0, 0), +}; + +static struct clk_rcg2 ubi0_core_clk_src = { + .cmd_rcgr = 0x68100, + .freq_tbl = ftbl_ubi0_core_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_ubi32_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "ubi0_core_clk_src", + .parent_data = gcc_xo_ubi32_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0), + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_rcg2 usb0_aux_clk_src = { + .cmd_rcgr = 0x3e05c, + .freq_tbl = ftbl_pcie0_aux_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "usb0_aux_clk_src", + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = { + F(25000000, P_GPLL0, 16, 1, 2), + { } +}; + +static struct clk_rcg2 usb0_lfps_clk_src = { + .cmd_rcgr = 0x3e090, + .freq_tbl = ftbl_usb0_lfps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "usb0_lfps_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 usb0_master_clk_src = { + .cmd_rcgr = 0x3e00c, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "usb0_master_clk_src", + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { + F(60000000, P_GPLL4, 10, 1, 2), + { } +}; + +static struct clk_rcg2 usb0_mock_utmi_clk_src = { + .cmd_rcgr = 0x3e020, + .freq_tbl = ftbl_usb0_mock_utmi_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "usb0_mock_utmi_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_mux usb0_pipe_clk_src = { + .reg = 0x3e048, + .shift = 8, + .width = 2, + .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, + .clkr = { + .hw.init = &(struct clk_init_data) { + .name = "usb0_pipe_clk_src", + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl ftbl_q6_axi_clk_src[] = { + F(400000000, P_GPLL0, 2, 0, 0), + { } +}; + +static struct clk_rcg2 q6_axi_clk_src = { + .cmd_rcgr = 0x59120, + .freq_tbl = ftbl_q6_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_gpll4_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "q6_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { + F(133333333, P_GPLL0, 6, 0, 0), + { } +}; + +static struct clk_rcg2 wcss_ahb_clk_src = { + .cmd_rcgr = 0x59020, + .freq_tbl = ftbl_wcss_ahb_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "wcss_ahb_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_sleep_clk_src = { + .halt_reg = 0x30000, + .clkr = { + .enable_reg = 0x30000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sleep_clk_src", + .parent_data = gcc_sleep_clk_data, + .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_xo_clk_src = { + .halt_reg = 0x30018, + .clkr = { + .enable_reg = 0x30018, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data) { + .name = "gcc_xo_clk_src", + .parent_data = gcc_xo_data, + .num_parents = ARRAY_SIZE(gcc_xo_data), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_xo_clk = { + .halt_reg = 0x30030, + .clkr = { + .enable_reg = 0x30030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_xo_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk = { + .halt_reg = 0x1f020, + .clkr = { + .enable_reg = 0x1f020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_adss_pwm_clk", + .parent_hws = (const struct clk_hw *[]) { + &adss_pwm_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x02008, + .clkr = { + .enable_reg = 0x02008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x02004, + .clkr = { + .enable_reg = 0x02004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x03010, + .clkr = { + .enable_reg = 0x03010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x0300c, + .clkr = { + .enable_reg = 0x0300c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x04010, + .clkr = { + .enable_reg = 0x04010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x0400c, + .clkr = { + .enable_reg = 0x0400c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x0203c, + .clkr = { + .enable_reg = 0x0203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_uart1_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_uart1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x0302c, + .clkr = { + .enable_reg = 0x0302c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_blsp1_uart2_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &blsp1_uart2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_btss_lpo_clk = { + .halt_reg = 0x1c004, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_btss_lpo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_blk_ahb_clk = { + .halt_reg = 0x56308, + .clkr = { + .enable_reg = 0x56308, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_cmn_blk_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_blk_sys_clk = { + .halt_reg = 0x5630c, + .clkr = { + .enable_reg = 0x5630c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_cmn_blk_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data) { + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1601c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data) { + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]) { + &crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_dcc_clk = { + .halt_reg = 0x77004, + .clkr = { + .enable_reg = 0x77004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_dcc_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gephy_rx_clk = { + .halt_reg = 0x56010, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x56010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gephy_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gephy_tx_clk = { + .halt_reg = 0x56014, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x56014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gephy_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gmac0_cfg_clk = { + .halt_reg = 0x68304, + .clkr = { + .enable_reg = 0x68304, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac0_cfg_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac0_ptp_clk = { + .halt_reg = 0x68300, + .clkr = { + .enable_reg = 0x68300, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac0_ptp_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac0_rx_clk = { + .halt_reg = 0x68240, + .clkr = { + .enable_reg = 0x68240, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac0_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gmac0_sys_clk = { + .halt_reg = 0x68190, + .halt_check = BRANCH_HALT_DELAY, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x683190, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac0_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac0_tx_clk = { + .halt_reg = 0x68244, + .clkr = { + .enable_reg = 0x68244, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac0_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac0_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gmac1_cfg_clk = { + .halt_reg = 0x68324, + .clkr = { + .enable_reg = 0x68324, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac1_cfg_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac1_ptp_clk = { + .halt_reg = 0x68320, + .clkr = { + .enable_reg = 0x68320, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac1_ptp_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac1_rx_clk = { + .halt_reg = 0x68248, + .clkr = { + .enable_reg = 0x68248, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac1_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gmac1_sys_clk = { + .halt_reg = 0x68310, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac1_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gmac1_tx_clk = { + .halt_reg = 0x6824c, + .clkr = { + .enable_reg = 0x6824c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gmac1_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x08000, + .clkr = { + .enable_reg = 0x08000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw *[]) { + &gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x09000, + .clkr = { + .enable_reg = 0x09000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw *[]) { + &gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x0a000, + .clkr = { + .enable_reg = 0x0a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw *[]) { + &gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_core_axim_clk = { + .halt_reg = 0x2e048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x2e048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_lpass_core_axim_clk", + .parent_hws = (const struct clk_hw *[]) { + &lpass_axim_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_sway_clk = { + .halt_reg = 0x2e04c, + .clkr = { + .enable_reg = 0x2e04c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_lpass_sway_clk", + .parent_hws = (const struct clk_hw *[]) { + &lpass_sway_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio0_ahb_clk = { + .halt_reg = 0x58004, + .clkr = { + .enable_reg = 0x58004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_mdioi0_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio1_ahb_clk = { + .halt_reg = 0x58014, + .clkr = { + .enable_reg = 0x58014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_mdio1_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk = { + .halt_reg = 0x75010, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk = { + .halt_reg = 0x75014, + .clkr = { + .enable_reg = 0x75014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_aux_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk = { + .halt_reg = 0x75008, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_axi_m_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { + .halt_reg = 0x75048, + .clkr = { + .enable_reg = 0x75048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_axi_s_bridge_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk = { + .halt_reg = 0x7500c, + .clkr = { + .enable_reg = 0x7500c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_axi_s_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x75018, + .halt_check = BRANCH_HALT_DELAY, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x75018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_ahb_clk = { + .halt_reg = 0x76010, + .clkr = { + .enable_reg = 0x76010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_aux_clk = { + .halt_reg = 0x76014, + .clkr = { + .enable_reg = 0x76014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_aux_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_m_clk = { + .halt_reg = 0x76008, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_axi_m_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { + .halt_reg = 0x76048, + .clkr = { + .enable_reg = 0x76048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_axi_s_bridge_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_axi_s_clk = { + .halt_reg = 0x7600c, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_axi_s_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 8, + .halt_check = BRANCH_HALT_DELAY, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x76018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x13004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data) { + .name = "gcc_prng_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_ahb_clk = { + .halt_reg = 0x59138, + .clkr = { + .enable_reg = 0x59138, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_ahb_s_clk = { + .halt_reg = 0x5914c, + .clkr = { + .enable_reg = 0x5914c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_ahb_s_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_axim_clk = { + .halt_reg = 0x5913c, + .clkr = { + .enable_reg = 0x5913c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_axim_clk", + .parent_hws = (const struct clk_hw *[]) { + &q6_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_axim2_clk = { + .halt_reg = 0x59150, + .clkr = { + .enable_reg = 0x59150, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_axim2_clk", + .parent_hws = (const struct clk_hw *[]) { + &q6_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_axis_clk = { + .halt_reg = 0x59154, + .clkr = { + .enable_reg = 0x59154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_axis_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_tsctr_1to2_clk = { + .halt_reg = 0x59148, + .clkr = { + .enable_reg = 0x59148, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6_tsctr_1to2_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_div2_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6ss_atbm_clk = { + .halt_reg = 0x59144, + .clkr = { + .enable_reg = 0x59144, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6ss_atbm_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6ss_pclkdbg_clk = { + .halt_reg = 0x59140, + .clkr = { + .enable_reg = 0x59140, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6ss_pclkdbg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6ss_trig_clk = { + .halt_reg = 0x59128, + .clkr = { + .enable_reg = 0x59128, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_q6ss_trig_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_at_clk = { + .halt_reg = 0x29024, + .clkr = { + .enable_reg = 0x29024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_at_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk = { + .halt_reg = 0x29084, + .clkr = { + .enable_reg = 0x29084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_dap_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_cfg_ahb_clk = { + .halt_reg = 0x29008, + .clkr = { + .enable_reg = 0x29008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_ahb_clk = { + .halt_reg = 0x29004, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_dap_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_etr_usb_clk = { + .halt_reg = 0x29028, + .clkr = { + .enable_reg = 0x29028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_etr_usb_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_eud_at_clk = { + .halt_reg = 0x29020, + .clkr = { + .enable_reg = 0x29020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_eud_at_clk", + .parent_hws = (const struct clk_hw *[]) { + &eud_at_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_stm_clk = { + .halt_reg = 0x29044, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_stm_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_stm_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_traceclkin_clk = { + .halt_reg = 0x29060, + .clkr = { + .enable_reg = 0x29060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_traceclkin_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_traceclkin_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_tsctr_div8_clk = { + .halt_reg = 0x2908c, + .clkr = { + .enable_reg = 0x2908c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qdss_tsctr_div8_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk = { + .halt_reg = 0x57024, + .clkr = { + .enable_reg = 0x57024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qpic_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk = { + .halt_reg = 0x57020, + .clkr = { + .enable_reg = 0x57020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qpic_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_io_macro_clk = { + .halt_reg = 0x5701c, + .clkr = { + .enable_reg = 0x5701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_qpic_io_macro_clk", + .parent_hws = (const struct clk_hw *[]) { + &qpic_io_macro_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x4201c, + .clkr = { + .enable_reg = 0x4201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sdcc1_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x42018, + .clkr = { + .enable_reg = 0x42018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw *[]) { + &sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_gmac0_ahb_clk = { + .halt_reg = 0x260a0, + .clkr = { + .enable_reg = 0x260a0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_gmac0_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_gmac0_axi_clk = { + .halt_reg = 0x26084, + .clkr = { + .enable_reg = 0x26084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_gmac0_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_gmac1_ahb_clk = { + .halt_reg = 0x260a4, + .clkr = { + .enable_reg = 0x260a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_gmac1_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_gmac1_axi_clk = { + .halt_reg = 0x26088, + .clkr = { + .enable_reg = 0x26088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_gmac1_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_lpass_axim_clk = { + .halt_reg = 0x26074, + .clkr = { + .enable_reg = 0x26074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_lpass_axim_clk", + .parent_hws = (const struct clk_hw *[]) { + &lpass_axim_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_lpass_sway_clk = { + .halt_reg = 0x26078, + .clkr = { + .enable_reg = 0x26078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_lpass_sway_clk", + .parent_hws = (const struct clk_hw *[]) { + &lpass_sway_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_ubi0_axi_clk = { + .halt_reg = 0x26094, + .clkr = { + .enable_reg = 0x26094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_snoc_ubi0_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &ubi0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_pcie0_axi_clk = { + .halt_reg = 0x26048, + .clkr = { + .enable_reg = 0x26048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sys_noc_pcie0_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_pcie1_axi_clk = { + .halt_reg = 0x2604c, + .clkr = { + .enable_reg = 0x2604c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sys_noc_pcie1_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { + .halt_reg = 0x26024, + .clkr = { + .enable_reg = 0x26024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sys_noc_qdss_stm_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_stm_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb0_axi_clk = { + .halt_reg = 0x26040, + .clkr = { + .enable_reg = 0x26040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sys_noc_usb0_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { + .halt_reg = 0x26034, + .clkr = { + .enable_reg = 0x26034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_sys_noc_wcss_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_axi_clk = { + .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68200, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &ubi0_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_cfg_clk = { + .halt_reg = 0x68160, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68160, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_cfg_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_dbg_clk = { + .halt_reg = 0x68214, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68214, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_dbg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_core_clk = { + .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68210, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_core_clk", + .parent_hws = (const struct clk_hw *[]) { + &ubi0_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_nc_axi_clk = { + .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_nc_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_utcm_clk = { + .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68208, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_ubi0_utcm_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy_ahb_clk = { + .halt_reg = 0x56108, + .clkr = { + .enable_reg = 0x56108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_uniphy_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy_rx_clk = { + .halt_reg = 0x56110, + .clkr = { + .enable_reg = 0x56110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_uniphy_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_uniphy_tx_clk = { + .halt_reg = 0x56114, + .clkr = { + .enable_reg = 0x56114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_uniphy_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &gmac1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_uniphy_sys_clk = { + .halt_reg = 0x5610c, + .clkr = { + .enable_reg = 0x5610c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_uniphy_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk = { + .halt_reg = 0x3e044, + .clkr = { + .enable_reg = 0x3e044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_aux_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_eud_at_clk = { + .halt_reg = 0x3e04c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x3e04c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_eud_at_clk", + .parent_hws = (const struct clk_hw *[]) { + &eud_at_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_lfps_clk = { + .halt_reg = 0x3e050, + .clkr = { + .enable_reg = 0x3e050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_lfps_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_lfps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk = { + .halt_reg = 0x3e000, + .clkr = { + .enable_reg = 0x3e000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_master_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk = { + .halt_reg = 0x3e008, + .clkr = { + .enable_reg = 0x3e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_mock_utmi_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { + .halt_reg = 0x3e080, + .clkr = { + .enable_reg = 0x3e080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk = { + .halt_reg = 0x3e004, + .clkr = { + .enable_reg = 0x3e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_sleep_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk = { + .halt_reg = 0x3e040, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x3e040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_usb0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_pipe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_acmt_clk = { + .halt_reg = 0x59064, + .clkr = { + .enable_reg = 0x59064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_acmt_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_ahb_s_clk = { + .halt_reg = 0x59034, + .clkr = { + .enable_reg = 0x59034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_ahb_s_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_axi_m_clk = { + .halt_reg = 0x5903c, + .clkr = { + .enable_reg = 0x5903c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_axi_m_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_axi_s_clk = { + .halt_reg = 0x59068, + .clkr = { + .enable_reg = 0x59068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wi_s_clk", + .parent_hws = (const struct clk_hw *[]) { + &system_noc_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { + .halt_reg = 0x59050, + .clkr = { + .enable_reg = 0x59050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { + .halt_reg = 0x59040, + .clkr = { + .enable_reg = 0x59040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_apb_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { + .halt_reg = 0x59054, + .clkr = { + .enable_reg = 0x59054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { + .halt_reg = 0x59044, + .clkr = { + .enable_reg = 0x59044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_atb_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { + .halt_reg = 0x59060, + .clkr = { + .enable_reg = 0x59060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { + .halt_reg = 0x5905c, + .clkr = { + .enable_reg = 0x5905c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_dapbus_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { + .halt_reg = 0x59058, + .clkr = { + .enable_reg = 0x59058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_div2_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { + .halt_reg = 0x59048, + .clkr = { + .enable_reg = 0x59048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_dbg_ifc_nts_clk", + .parent_hws = (const struct clk_hw *[]) { + &qdss_tsctr_div2_clk_src.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_ecahb_clk = { + .halt_reg = 0x59038, + .clkr = { + .enable_reg = 0x59038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_wcss_ecahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_hw *gcc_ipq5018_hws[] = { + &gpll0_out_main_div2.hw, + &pcnoc_clk_src.hw, + &system_noc_clk_src.hw, + &qdss_dap_sync_clk_src.hw, + &qdss_tsctr_div2_clk_src.hw, + &eud_at_clk_src.hw, +}; + +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x29, + .alpha = 0xaaaaaaaa, + .alpha_hi = 0xaa, + .config_ctl_val = 0x4001075b, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .alpha_en_mask = BIT(24), + .vco_val = 0x1, + .vco_mask = GENMASK(21, 20), + .test_ctl_val = 0x0, + .test_ctl_hi_val = 0x0, +}; + +static struct clk_regmap *gcc_ipq5018_clks[] = { + [GPLL0_MAIN] = &gpll0_main.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL2_MAIN] = &gpll2_main.clkr, + [GPLL2] = &gpll2.clkr, + [GPLL4_MAIN] = &gpll4_main.clkr, + [GPLL4] = &gpll4.clkr, + [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr, + [UBI32_PLL] = &ubi32_pll.clkr, + [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, + [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr, + [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr, + [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, + [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr, + [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr, + [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr, + [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr, + [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr, + [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr, + [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr, + [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr, + [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr, + [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr, + [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr, + [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, + [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr, + [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr, + [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, + [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, + [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, + [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, + [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, + [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, + [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, + [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, + [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, + [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, + [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, + [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, + [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, + [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, + [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, + [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, + [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, + [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, + [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, + [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, + [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, + [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, + [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, + [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, + [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, + [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, + [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, + [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr, + [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr, + [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr, + [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr, + [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr, + [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr, + [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr, + [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, + [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr, + [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, + [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr, + [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, + [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr, + [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr, + [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr, + [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr, + [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr, + [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr, + [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr, + [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr, + [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr, + [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr, + [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, + [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, + [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr, + [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, + [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, + [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, + [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, + [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, + [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, + [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr, + [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, + [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, + [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, + [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, + [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, + [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, + [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, + [GCC_XO_CLK] = &gcc_xo_clk.clkr, + [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, + [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, + [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr, + [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr, + [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr, + [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr, + [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr, + [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr, + [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr, + [GMAC_CLK_SRC] = &gmac_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, + [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, + [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr, + [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr, + [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr, + [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr, + [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, + [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, + [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, + [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, + [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, + [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, + [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, + [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr, + [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr, + [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, + [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr, + [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, + [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, + [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, + [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, + [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, +}; + +static const struct qcom_reset_map gcc_ipq5018_resets[] = { + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 }, + [GCC_BLSP1_BCR] = { 0x01000, 0 }, + [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, + [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 }, + [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 }, + [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 }, + [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, + [GCC_BOOT_ROM_BCR] = { 0x13008, 0 }, + [GCC_BTSS_BCR] = { 0x1c000, 0 }, + [GCC_CMN_BLK_BCR] = { 0x56300, 0 }, + [GCC_CMN_LDO_BCR] = { 0x33000, 0 }, + [GCC_CE_BCR] = { 0x33014, 0 }, + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, + [GCC_DCC_BCR] = { 0x77000, 0 }, + [GCC_DCD_BCR] = { 0x2a000, 0 }, + [GCC_DDRSS_BCR] = { 0x1e000, 0 }, + [GCC_EDPD_BCR] = { 0x3a000, 0 }, + [GCC_GEPHY_BCR] = { 0x56000, 0 }, + [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 }, + [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 }, + [GCC_GEPHY_RX_ARES] = { 0x56004, 2 }, + [GCC_GEPHY_TX_ARES] = { 0x56004, 3 }, + [GCC_GMAC0_BCR] = { 0x19000, 0 }, + [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 }, + [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 }, + [GCC_GMAC1_BCR] = { 0x19100, 0 }, + [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 }, + [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 }, + [GCC_IMEM_BCR] = { 0x0e000, 0 }, + [GCC_LPASS_BCR] = { 0x2e000, 0 }, + [GCC_MDIO0_BCR] = { 0x58000, 0 }, + [GCC_MDIO1_BCR] = { 0x58010, 0 }, + [GCC_MPM_BCR] = { 0x2c000, 0 }, + [GCC_PCIE0_BCR] = { 0x75004, 0 }, + [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 }, + [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 }, + [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 }, + [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 }, + [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 }, + [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 }, + [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 }, + [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 }, + [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, + [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, + [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, + [GCC_PCIE1_BCR] = { 0x76004, 0 }, + [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 }, + [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 }, + [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 }, + [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 }, + [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 }, + [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 }, + [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 }, + [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, + [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 }, + [GCC_PCNOC_BCR] = { 0x27018, 0 }, + [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 }, + [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 }, + [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 }, + [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 }, + [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 }, + [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 }, + [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 }, + [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 }, + [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 }, + [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 }, + [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 }, + [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 }, + [GCC_PRNG_BCR] = { 0x13000, 0 }, + [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 }, + [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 }, + [GCC_Q6_AHB_ARES] = { 0x59110, 2 }, + [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 }, + [GCC_Q6_AXIM_ARES] = { 0x59110, 4 }, + [GCC_Q6_AXIS_ARES] = { 0x59158, 0 }, + [GCC_QDSS_BCR] = { 0x29000, 0 }, + [GCC_QPIC_BCR] = { 0x57018, 0 }, + [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 }, + [GCC_SDCC1_BCR] = { 0x42000, 0 }, + [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, + [GCC_SPDM_BCR] = { 0x2f000, 0 }, + [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, + [GCC_TCSR_BCR] = { 0x28000, 0 }, + [GCC_TLMM_BCR] = { 0x34000, 0 }, + [GCC_UBI0_AXI_ARES] = { 0x680}, + [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, + [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, + [GCC_UBI0_DBG_ARES] = { 0x68010, 3 }, + [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 }, + [GCC_UBI0_CORE_ARES] = { 0x68010, 7 }, + [GCC_UBI32_BCR] = { 0x19064, 0 }, + [GCC_UNIPHY_BCR] = { 0x56100, 0 }, + [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 }, + [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 }, + [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 }, + [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 }, + [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 }, + [GCC_USB0_BCR] = { 0x3e070, 0 }, + [GCC_USB0_PHY_BCR] = { 0x3e034, 0 }, + [GCC_WCSS_BCR] = { 0x18000, 0 }, + [GCC_WCSS_DBG_ARES] = { 0x59008, 0 }, + [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 }, + [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 }, + [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 }, + [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 }, + [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 }, + [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, + [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, + [GCC_WCSSAON_RESET] = { 0x59010, 0}, + [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, +}; + +static const struct of_device_id gcc_ipq5018_match_table[] = { + { .compatible = "qcom,gcc-ipq5018" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table); + +static const struct regmap_config gcc_ipq5018_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7fffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_ipq5018_desc = { + .config = &gcc_ipq5018_regmap_config, + .clks = gcc_ipq5018_clks, + .num_clks = ARRAY_SIZE(gcc_ipq5018_clks), + .resets = gcc_ipq5018_resets, + .num_resets = ARRAY_SIZE(gcc_ipq5018_resets), + .clk_hws = gcc_ipq5018_hws, + .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws), +}; + +static int gcc_ipq5018_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc; + + regmap = qcom_cc_map(pdev, &ipq5018_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + + return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap); +} + +static struct platform_driver gcc_ipq5018_driver = { + .probe = gcc_ipq5018_probe, + .driver = { + .name = "qcom,gcc-ipq5018", + .of_match_table = gcc_ipq5018_match_table, + }, +}; + +static int __init gcc_ipq5018_init(void) +{ + return platform_driver_register(&gcc_ipq5018_driver); +} +core_initcall(gcc_ipq5018_init); + +static void __exit gcc_ipq5018_exit(void) +{ + platform_driver_unregister(&gcc_ipq5018_driver); +} +module_exit(gcc_ipq5018_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 9c76c5cf4b3177a22978893c2312d73bcc911739 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:07 +0200 Subject: clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properly Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by: Jeffrey Hugo Tested-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-3-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8998.c | 58 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index be024f8093c5..cccb19cae481 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -25,6 +25,9 @@ #include "reset.h" #include "gdsc.h" +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + static struct pll_vco fabia_vco[] = { { 250000000, 2000000000, 0 }, { 125000000, 1000000000, 1 }, @@ -1367,6 +1370,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { }, }; +static struct clk_branch gcc_mmss_gpll0_div_clk = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_out_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_mmss_gpll0_clk = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -1395,6 +1414,38 @@ static struct clk_branch gcc_mss_gpll0_div_clk_src = { }, }; +static struct clk_branch gcc_gpu_gpll0_div_clk = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_out_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_out_main.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_blsp1_ahb_clk = { .halt_reg = 0x17004, .halt_check = BRANCH_HALT_VOTED, @@ -3080,6 +3131,9 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, [SSC_XO] = &ssc_xo_clk.clkr, [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { @@ -3235,6 +3289,10 @@ static int gcc_msm8998_probe(struct platform_device *pdev) if (ret) return ret; + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ + regmap_write(regmap, GCC_MMSS_MISC, 0x10003); + regmap_write(regmap, GCC_GPU_MISC, 0x10003); + return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); } -- cgit v1.2.3 From 932d8c56884ad847844c7e25ec73f712893a2b57 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:08 +0200 Subject: clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputs Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: Jeffrey Hugo Tested-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/mmcc-msm8998.c | 35 ++++++++--------------------------- 1 file changed, 8 insertions(+), 27 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c index 4490594bde69..040c495e91e4 100644 --- a/drivers/clk/qcom/mmcc-msm8998.c +++ b/drivers/clk/qcom/mmcc-msm8998.c @@ -46,19 +46,6 @@ enum { P_DPLINK, }; -static struct clk_fixed_factor gpll0_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "mmss_gpll0_div", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "gpll0" - }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - static const struct clk_div_table post_div_table_fabia_even[] = { { 0x0, 1 }, { 0x1, 2 }, @@ -354,7 +341,7 @@ static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { { .fw_name = "xo" }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { @@ -368,7 +355,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { { .fw_name = "xo" }, { .hw = &mmpll0_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { @@ -384,7 +371,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { { .hw = &mmpll0_out_even.clkr.hw }, { .hw = &mmpll1_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { @@ -400,7 +387,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { { .hw = &mmpll0_out_even.clkr.hw }, { .hw = &mmpll5_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = { @@ -418,7 +405,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div { .hw = &mmpll3_out_even.clkr.hw }, { .hw = &mmpll6_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { @@ -436,7 +423,7 @@ static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_di { .hw = &mmpll7_out_even.clkr.hw }, { .hw = &mmpll10_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { @@ -454,7 +441,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_di { .hw = &mmpll7_out_even.clkr.hw }, { .hw = &mmpll10_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { @@ -474,7 +461,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_g { .hw = &mmpll7_out_even.clkr.hw }, { .hw = &mmpll10_out_even.clkr.hw }, { .fw_name = "gpll0" }, - { .hw = &gpll0_div.hw }, + { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, }; static struct clk_rcg2 byte0_clk_src = { @@ -2544,10 +2531,6 @@ static struct clk_branch vmem_ahb_clk = { }, }; -static struct clk_hw *mmcc_msm8998_hws[] = { - &gpll0_div.hw, -}; - static struct gdsc video_top_gdsc = { .gdscr = 0x1024, .pd = { @@ -2855,8 +2838,6 @@ static const struct qcom_cc_desc mmcc_msm8998_desc = { .num_resets = ARRAY_SIZE(mmcc_msm8998_resets), .gdscs = mmcc_msm8998_gdscs, .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs), - .clk_hws = mmcc_msm8998_hws, - .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws), }; static const struct of_device_id mmcc_msm8998_match_table[] = { -- cgit v1.2.3 From 03f1b83d89851abdd5c490f873124a1ba2a6ae33 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:09 +0200 Subject: clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. Add .name lookup to make sure older DTs consume the correct clock. Reviewed-by: Jeffrey Hugo Tested-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-5-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-msm8998.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index f929e0f2333f..cc0b43354787 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -98,7 +98,7 @@ static const struct parent_map gpu_xo_gpll0_map[] = { static const struct clk_parent_data gpu_xo_gpll0[] = { { .hw = &gpucc_cxo_clk.clkr.hw }, - { .fw_name = "gpll0" }, + { .fw_name = "gpll0", .name = "gcc_gpu_gpll0_clk" }, }; static const struct parent_map gpu_xo_gpupll0_map[] = { -- cgit v1.2.3 From a6f1e8623836bb6ce64c347d110ecb6259ae73c4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:10 +0200 Subject: clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-6-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8998.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index cccb19cae481..ef410f52f09f 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2112,7 +2112,7 @@ static struct clk_branch gcc_gp3_clk = { static struct clk_branch gcc_bimc_gfx_clk = { .halt_reg = 0x46040, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x46040, .enable_mask = BIT(0), @@ -2125,7 +2125,7 @@ static struct clk_branch gcc_bimc_gfx_clk = { static struct clk_branch gcc_gpu_bimc_gfx_clk = { .halt_reg = 0x71010, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x71010, .enable_mask = BIT(0), @@ -2151,7 +2151,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { static struct clk_branch gcc_gpu_cfg_ahb_clk = { .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x71004, .enable_mask = BIT(0), -- cgit v1.2.3 From 1784d031ef1f329bd362343a8fe1c083116160af Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 10 Jul 2023 15:58:06 +0530 Subject: clk: qcom: ipq5332: drop the mem noc clocks Due to the recent design changes, all the mem noc clocks will be configured by the bootloaders and it will be access protected by the TZ firmware. So drop these clocks from the GCC driver. Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/20230710102807.1189942-2-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq5332.c | 95 ------------------------------------------ 1 file changed, 95 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index a75ab88ed14c..939925baa9eb 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -1635,42 +1635,6 @@ static struct clk_branch gcc_mdio_slave_ahb_clk = { }, }; -static struct clk_branch gcc_mem_noc_q6_axi_clk = { - .halt_reg = 0x19010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19010, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_q6_axi_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_q6_axim_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mem_noc_ts_clk = { - .halt_reg = 0x19028, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x19028, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_ts_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_tsctr_div8_clk_src.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nss_ts_clk = { .halt_reg = 0x17018, .halt_check = BRANCH_HALT_VOTED, @@ -3339,42 +3303,6 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { }, }; -static struct clk_branch gcc_mem_noc_ahb_clk = { - .halt_reg = 0x1900c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1900c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_pcnoc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mem_noc_apss_axi_clk = { - .halt_reg = 0x1901c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(6), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_apss_axi_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_apss_axi_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = { .reg = 0x2e010, .shift = 0, @@ -3390,24 +3318,6 @@ static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = { }, }; -static struct clk_branch gcc_mem_noc_qosgen_extref_clk = { - .halt_reg = 0x19024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_qosgen_extref_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_snoc_qosgen_extref_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap *gcc_ipq5332_clocks[] = { [GPLL0_MAIN] = &gpll0_main.clkr, [GPLL0] = &gpll0.clkr, @@ -3451,8 +3361,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr, - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, - [GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr, [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, @@ -3573,10 +3481,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr, [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, - [GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr, - [GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr, [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr, - [GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr, [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr, [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, -- cgit v1.2.3 From 90d5c043dda7901065e9da4b23967903640fd2ea Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 10 Jul 2023 15:58:07 +0530 Subject: clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock With the removal of the mem noc clocks in the commit e224dc703521 ("clk: qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the gcc_apss_axi_clk_src clock as well, since there are no clocks uses this clock as a parent. Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq5332.c | 111 +++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 72 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 939925baa9eb..40d8e8d5956f 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -224,38 +224,20 @@ static const struct clk_parent_data gcc_parent_data_4[] = { }; static const struct parent_map gcc_parent_map_5[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL2_OUT_AUX, 2 }, - { P_GPLL4_OUT_AUX, 3 }, - { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, - { P_GPLL0_OUT_AUX, 5 }, -}; - -static const struct clk_parent_data gcc_parent_data_5[] = { - { .index = DT_XO }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll2.clkr.hw }, - { .hw = &gpll4.clkr.hw }, - { .hw = &gpll0_div2.hw }, - { .hw = &gpll0.clkr.hw }, -}; - -static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_AUX, 2 }, { P_SLEEP_CLK, 6 }, }; -static const struct clk_parent_data gcc_parent_data_6[] = { +static const struct clk_parent_data gcc_parent_data_5[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll0.clkr.hw }, { .index = DT_SLEEP_CLK }, }; -static const struct parent_map gcc_parent_map_7[] = { +static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL2_OUT_AUX, 2 }, @@ -263,7 +245,7 @@ static const struct parent_map gcc_parent_map_7[] = { { P_SLEEP_CLK, 6 }, }; -static const struct clk_parent_data gcc_parent_data_7[] = { +static const struct clk_parent_data gcc_parent_data_6[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, @@ -271,74 +253,74 @@ static const struct clk_parent_data gcc_parent_data_7[] = { { .index = DT_SLEEP_CLK }, }; -static const struct parent_map gcc_parent_map_8[] = { +static const struct parent_map gcc_parent_map_7[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL2_OUT_AUX, 2 }, }; -static const struct clk_parent_data gcc_parent_data_8[] = { +static const struct clk_parent_data gcc_parent_data_7[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, }; -static const struct parent_map gcc_parent_map_9[] = { +static const struct parent_map gcc_parent_map_8[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL2_OUT_MAIN, 2 }, { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, }; -static const struct clk_parent_data gcc_parent_data_9[] = { +static const struct clk_parent_data gcc_parent_data_8[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll2.clkr.hw }, { .hw = &gpll0_div2.hw }, }; -static const struct parent_map gcc_parent_map_10[] = { +static const struct parent_map gcc_parent_map_9[] = { { P_SLEEP_CLK, 6 }, }; -static const struct clk_parent_data gcc_parent_data_10[] = { +static const struct clk_parent_data gcc_parent_data_9[] = { { .index = DT_SLEEP_CLK }, }; -static const struct parent_map gcc_parent_map_11[] = { +static const struct parent_map gcc_parent_map_10[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 2 }, { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 }, }; -static const struct clk_parent_data gcc_parent_data_11[] = { +static const struct clk_parent_data gcc_parent_data_10[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &gpll0_div2.hw }, }; -static const struct parent_map gcc_parent_map_12[] = { +static const struct parent_map gcc_parent_map_11[] = { { P_XO, 0 }, { P_GPLL0_OUT_AUX, 2 }, { P_SLEEP_CLK, 6 }, }; -static const struct clk_parent_data gcc_parent_data_12[] = { +static const struct clk_parent_data gcc_parent_data_11[] = { { .index = DT_XO }, { .hw = &gpll0.clkr.hw }, { .index = DT_SLEEP_CLK }, }; -static const struct parent_map gcc_parent_map_13[] = { +static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_GPLL4_OUT_AUX, 1 }, { P_GPLL0_OUT_MAIN, 3 }, { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, }; -static const struct clk_parent_data gcc_parent_data_13[] = { +static const struct clk_parent_data gcc_parent_data_12[] = { { .index = DT_XO }, { .hw = &gpll4.clkr.hw }, { .hw = &gpll0.clkr.hw }, @@ -371,20 +353,6 @@ static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = { { } }; -static struct clk_rcg2 gcc_apss_axi_clk_src = { - .cmd_rcgr = 0x24004, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_apss_axi_clk_src, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "gcc_apss_axi_clk_src", - .parent_data = gcc_parent_data_5, - .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { F(960000, P_XO, 1, 1, 25), F(4800000, P_XO, 5, 0, 0), @@ -733,12 +701,12 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = { .cmd_rcgr = 0x28004, .mnd_width = 16, .hid_width = 5, - .parent_map = gcc_parent_map_6, + .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_pcie_aux_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_aux_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; @@ -810,12 +778,12 @@ static struct clk_rcg2 gcc_q6_axim_clk_src = { .cmd_rcgr = 0x25004, .mnd_width = 0, .hid_width = 5, - .parent_map = gcc_parent_map_7, + .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_apss_axi_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_q6_axim_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; @@ -931,12 +899,12 @@ static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { .cmd_rcgr = 0x32004, .mnd_width = 0, .hid_width = 5, - .parent_map = gcc_parent_map_8, + .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_qpic_io_macro_clk_src", - .parent_data = gcc_parent_data_8, - .num_parents = ARRAY_SIZE(gcc_parent_data_8), + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_rcg2_ops, }, }; @@ -957,12 +925,12 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .cmd_rcgr = 0x33004, .mnd_width = 8, .hid_width = 5, - .parent_map = gcc_parent_map_9, + .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk_src", - .parent_data = gcc_parent_data_9, - .num_parents = ARRAY_SIZE(gcc_parent_data_9), + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_rcg2_floor_ops, }, }; @@ -976,12 +944,12 @@ static struct clk_rcg2 gcc_sleep_clk_src = { .cmd_rcgr = 0x3400c, .mnd_width = 0, .hid_width = 5, - .parent_map = gcc_parent_map_10, + .parent_map = gcc_parent_map_9, .freq_tbl = ftbl_gcc_sleep_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sleep_clk_src", - .parent_data = gcc_parent_data_10, - .num_parents = ARRAY_SIZE(gcc_parent_data_10), + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), .ops = &clk_rcg2_ops, }, }; @@ -998,12 +966,12 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { .cmd_rcgr = 0x2e004, .mnd_width = 0, .hid_width = 5, - .parent_map = gcc_parent_map_11, + .parent_map = gcc_parent_map_10, .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_system_noc_bfdcd_clk_src", - .parent_data = gcc_parent_data_11, - .num_parents = ARRAY_SIZE(gcc_parent_data_11), + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), .ops = &clk_rcg2_ops, }, }; @@ -1039,12 +1007,12 @@ static struct clk_rcg2 gcc_usb0_aux_clk_src = { .cmd_rcgr = 0x2c018, .mnd_width = 16, .hid_width = 5, - .parent_map = gcc_parent_map_12, + .parent_map = gcc_parent_map_11, .freq_tbl = ftbl_gcc_pcie_aux_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_aux_clk_src", - .parent_data = gcc_parent_data_12, - .num_parents = ARRAY_SIZE(gcc_parent_data_12), + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), .ops = &clk_rcg2_ops, }, }; @@ -1091,12 +1059,12 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { .cmd_rcgr = 0x2c02c, .mnd_width = 8, .hid_width = 5, - .parent_map = gcc_parent_map_13, + .parent_map = gcc_parent_map_12, .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_mock_utmi_clk_src", - .parent_data = gcc_parent_data_13, - .num_parents = ARRAY_SIZE(gcc_parent_data_13), + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), .ops = &clk_rcg2_ops, }, }; @@ -3328,7 +3296,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, [GCC_AHB_CLK] = &gcc_ahb_clk.clkr, - [GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr, [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, -- cgit v1.2.3 From a27ac3806b0a0e6954fb5967223b8635242e5b8f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 19:35:53 +0200 Subject: clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Signed-off-by: Konrad Dybcio Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sm8450.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 75635d40a12d..9f4f72553ecf 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -935,7 +935,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -958,7 +958,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From b311f5d3c4749259043a9a458a8db07915210142 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:35 +0530 Subject: clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5051769ad90c..c00d26a3e6df 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .index = DT_TCXO_IDX }, }; -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .index = DT_PCIE_0_PIPE_CLK_IDX }, - { .index = DT_TCXO_IDX }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_0_PIPE_CLK_IDX, + }, + .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, }, }, -- cgit v1.2.3 From 2524dae5cd453ca39e8ba1b95c2755a8a2d94059 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:36 +0530 Subject: clk: qcom: gcc-qdu1000: Fix clkref clocks handling Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index c00d26a3e6df..8df7b7983968 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1447,14 +1447,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { static struct clk_branch gcc_pcie_0_clkref_en = { .halt_reg = 0x9c004, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c004, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; @@ -2274,14 +2273,13 @@ static struct clk_branch gcc_tsc_etu_clk = { static struct clk_branch gcc_usb2_clkref_en = { .halt_reg = 0x9c008, - .halt_bit = 31, - .halt_check = BRANCH_HALT_ENABLE, + .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9c008, .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_usb2_clkref_en", - .ops = &clk_branch_ops, + .ops = &clk_branch2_ops, }, }, }; -- cgit v1.2.3 From 06d71fa10f2e507444c6759328a6c19d38eab788 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:37 +0530 Subject: clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 8df7b7983968..626c5afed780 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -2521,6 +2521,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr, [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, + [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { -- cgit v1.2.3 From 089aad8c769ca0710a66a2adc3e11d94b027b5f7 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:38 +0530 Subject: clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware version of QDU1000 and QRU100 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-6-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 626c5afed780..991fb2bc97e9 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1131,6 +1131,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = { }, }; +static struct clk_branch gcc_ddrss_ecpri_gsi_clk = { + .halt_reg = 0x54298, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x54298, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x54298, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_ddrss_ecpri_gsi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_ecpri_ahb_clk = { .halt_reg = 0x3a008, .halt_check = BRANCH_HALT_VOTED, @@ -2522,6 +2542,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr, + [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; static const struct qcom_reset_map gcc_qdu1000_resets[] = { -- cgit v1.2.3 From 76346cf7089abd488fb3ad9753901b99baa3cafc Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:39 +0530 Subject: clk: qcom: gcc-qdu1000: Add support for GDSCs Add the GDSCs support for QDU1000 and QRU1000 SoCs. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-7-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 991fb2bc97e9..718c34dca6e8 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -17,6 +17,7 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "clk-regmap-phy-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2409,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x9d004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_phy_gdsc = { + .gdscr = 0x7c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, + .pd = { + .name = "gcc_pcie_0_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0x49004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "gcc_usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, @@ -2545,6 +2579,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, }; +static struct gdsc *gcc_qdu1000_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, +}; + static const struct qcom_reset_map gcc_qdu1000_resets[] = { [GCC_ECPRI_CC_BCR] = { 0x3e000 }, [GCC_ECPRI_SS_BCR] = { 0x3a000 }, @@ -2606,6 +2646,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = { .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), .resets = gcc_qdu1000_resets, .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), + .gdscs = gcc_qdu1000_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), }; static const struct of_device_id gcc_qdu1000_match_table[] = { -- cgit v1.2.3 From baa316580013ca100c23c8e92ac713f69f19fb08 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:40 +0530 Subject: clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-8-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 718c34dca6e8..540577ae58e4 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = { .name = "gcc_sdcc5_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = { .name = "gcc_sdcc5_ice_core_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From 1c16a7b794e15a2e843a1fbfd3ffaea46672f6e7 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:41 +0530 Subject: clk: qcom: gcc-qdu1000: Update the RCGs ops The clock RCGs are required to be parked at safe clock source(XO) during disable as per the hardware expectation and clk_rcg2_shared_ops are the closest implementation for the same. Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803105741.2292309-9-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qdu1000.c | 58 +++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 540577ae58e4..de35cdc93732 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -475,7 +475,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = { .name = "gcc_aggre_noc_ecpri_dma_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = { .name = "gcc_aggre_noc_ecpri_gsi_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -514,7 +514,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -542,7 +542,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -561,7 +561,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .name = "gcc_pcie_0_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -622,7 +622,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { @@ -638,7 +638,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { @@ -654,7 +654,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { @@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { @@ -686,7 +686,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { @@ -707,7 +707,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { @@ -723,7 +723,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { @@ -739,7 +739,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { @@ -755,7 +755,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { @@ -771,7 +771,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { @@ -787,7 +787,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { @@ -803,7 +803,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { @@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { @@ -851,7 +851,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { .name = "gcc_qupv3_wrap1_s6_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { @@ -867,7 +867,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { .name = "gcc_qupv3_wrap1_s7_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = { .name = "gcc_sm_bus_xo_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = { .name = "gcc_tsc_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -975,7 +975,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -989,7 +989,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1003,7 +1003,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; -- cgit v1.2.3 From d863492886930a1a6f7c0d9dda8f728077b540f0 Mon Sep 17 00:00:00 2001 From: Otto Pflüger Date: Wed, 2 Aug 2023 19:03:18 +0200 Subject: clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the parent clock of gpll0_early, so it needs to be enabled for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC by adding its existing definition to the clock list. This clock also doesn't work with clk_alpha_pll_ops, use clk_branch_simple_ops instead to make it enable and disable correctly. Signed-off-by: Otto Pflüger Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-msm8917.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index a4c33a2ce61c..b2cbdb351fcf 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -64,7 +64,7 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .index = DT_XO, }, .num_parents = 1, - .ops = &clk_alpha_pll_ops, + .ops = &clk_branch_simple_ops, }, }, }; @@ -3042,6 +3042,7 @@ static struct gdsc cpp_gdsc = { static struct clk_regmap *gcc_msm8917_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_EARLY] = &gpll0_early.clkr, + [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, [GPLL3] = &gpll3.clkr, [GPLL3_EARLY] = &gpll3_early.clkr, [GPLL4] = &gpll4.clkr, -- cgit v1.2.3 From 9bc66f973988dc4adc29d36824423448f8da8feb Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 14 Aug 2023 12:40:24 +0200 Subject: clk: qcom: gcc-ipq4019: add missing networking resets IPQ4019 has more networking related resets that will be required for future wired networking support, so lets add them. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c index 5657e29464ad..b1a8af01ef7d 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c @@ -1686,6 +1686,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = { [GCC_TCSR_BCR] = {0x22000, 0}, [GCC_MPM_BCR] = {0x24000, 0}, [GCC_SPDM_BCR] = {0x25000, 0}, + [ESS_MAC1_ARES] = {0x1200C, 0}, + [ESS_MAC2_ARES] = {0x1200C, 1}, + [ESS_MAC3_ARES] = {0x1200C, 2}, + [ESS_MAC4_ARES] = {0x1200C, 3}, + [ESS_MAC5_ARES] = {0x1200C, 4}, + [ESS_PSGMII_ARES] = {0x1200C, 5}, }; static const struct regmap_config gcc_ipq4019_regmap_config = { -- cgit v1.2.3 From a7bea084fb0a30991951ec55c890a936fb41a044 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 16 Aug 2023 16:01:13 +0800 Subject: clk: qcom: gcc-ipq5018: change some variable static lpass_axim_clk_src and lpass_sway_clk_src are only used in gcc-ipq5018.c now, change them to static. Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Yang Yingliang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230816080113.1222352-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq5018.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 313ff2281ca7..19dc2b71cacf 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -826,7 +826,7 @@ static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { { } }; -struct clk_rcg2 lpass_axim_clk_src = { +static struct clk_rcg2 lpass_axim_clk_src = { .cmd_rcgr = 0x2e028, .freq_tbl = ftbl_lpass_axim_clk_src, .hid_width = 5, @@ -844,7 +844,7 @@ static const struct freq_tbl ftbl_lpass_sway_clk_src[] = { { } }; -struct clk_rcg2 lpass_sway_clk_src = { +static struct clk_rcg2 lpass_sway_clk_src = { .cmd_rcgr = 0x2e040, .freq_tbl = ftbl_lpass_sway_clk_src, .hid_width = 5, -- cgit v1.2.3 From 2db8dc7bf49cc0b04a99d9525d5d54312f431ce5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 31 Jul 2023 14:20:12 +0200 Subject: clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags Some clocks, at least PCNoC (a.k.a CNoC_PERIPH) need to be always on, at least on the ACTIVE side, regardless of whether they're used for bus scaling or not. Introduce a new macro to preset non-INT_MAX rates and clk flags to make it easy and work implicitly through the CCF. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-1-452dd36d11d7@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-smd-rpm.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 997c2b89a5d1..f38eb8055759 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -19,7 +19,7 @@ #include #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ - type, r_id, key) \ + type, r_id, key, ao_rate, ao_flags) \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ .rpm_res_type = (type), \ @@ -43,7 +43,7 @@ .active_only = true, \ .rpm_key = (key), \ .peer = &clk_smd_rpm_##_prefix##_name, \ - .rate = INT_MAX, \ + .rate = (ao_rate), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ @@ -52,12 +52,14 @@ .name = "xo_board", \ }, \ .num_parents = 1, \ + .flags = (ao_flags), \ }, \ } -#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \ +#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\ + ao_rate, ao_flags) \ __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ - type, r_id, key) + type, r_id, key, ao_rate, ao_flags) #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ type, r_id, r, key, ao_flags) \ @@ -105,17 +107,22 @@ #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ - type, r_id, QCOM_RPM_SMD_KEY_RATE) + type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ - QCOM_RPM_SMD_KEY_RATE) + QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) + +#define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \ + __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ + _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ + QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags) #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ __DEFINE_CLK_SMD_RPM( \ _name##_clk_src, _name##_a_clk_src, \ - type, r_id, QCOM_RPM_SMD_KEY_RATE) + type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ @@ -129,7 +136,7 @@ #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ - type, r_id, QCOM_RPM_SMD_KEY_STATE) + type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ -- cgit v1.2.3 From e1cd74b6dccb98ca09e4612ff29c7658db7a487b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 31 Jul 2023 14:20:13 +0200 Subject: clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must be always-on as long as the APSS is online and only has to run at 19.2 MHz. Define it to be as such in the ACTIVE domain. Some SoCs use that clock for bus scaling, while others just need it for reaching the hardware. This commit will hurt neither. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-2-452dd36d11d7@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-smd-rpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index f38eb8055759..c8d59e0f25f2 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -456,7 +456,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); DEFINE_CLK_SMD_RPM_BUS(snoc, 1); DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); -- cgit v1.2.3 From 75d1d3a433f0a0748a89eb074830e9b635a19fd2 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 29 Aug 2023 07:08:47 -0700 Subject: clk: qcom: Fix SM_GPUCC_8450 dependencies CONFIG_SM_GCC_8450 depends on ARM64 but it is selected by CONFIG_SM_GPUCC_8450, which can be selected on ARM, resulting in a Kconfig warning. WARNING: unmet direct dependencies detected for SM_GCC_8450 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_GPUCC_8450 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Add the same dependencies to CONFIG_SM_GPUCC_8450 to resolve the warning. Fixes: 728692d49edc ("clk: qcom: Add support for SM8450 GPUCC") Signed-off-by: Nathan Chancellor Link: https://lore.kernel.org/r/20230829-fix-sm_gpucc_8550-deps-v1-1-d751f6cd35b2@kernel.org Reviewed-by: Konrad Dybcio Signed-off-by: Stephen Boyd --- drivers/clk/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bd9bfb11b328..865db5202e4c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -986,6 +986,7 @@ config SM_GPUCC_8350 config SM_GPUCC_8450 tristate "SM8450 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help Support for the graphics clock controller on SM8450 devices. -- cgit v1.2.3