From bed18bbbf9d9af55ccc01a6e2a8ec90d7e35cb11 Mon Sep 17 00:00:00 2001 From: Calvin Owens Date: Mon, 25 May 2026 20:22:53 -0700 Subject: x86/cfi: Add __init_or_module annotations for fineibt I'm seeing some benign section mismatch warnings with fineibt when building kernels with CONFIG_MODULES=n: WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x1db (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x473 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x57c (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x6d9 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xb57 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xb81 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xd00 (section: .text) -> poison_endbr (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xdd3 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xe58 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xe85 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: apply_fineibt+0x8 (section: .text.unlikely.) -> __apply_fineibt (section: .init.text) Add the missing __init_or_module section annotations to fix the warnings, and also free up a tiny bit of memory after boot. Signed-off-by: Calvin Owens Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Kees Cook Reviewed-by: Juergen Gross Link: https://patch.msgid.link/1f50aecf23311dc5ffb965c5ccfb8b49208dbb3f.1779763849.git.calvin@wbinvd.org --- arch/x86/kernel/alternative.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/x86/kernel') diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 62936a3bde19..400baffcd609 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -1775,8 +1775,8 @@ static int cfi_rewrite_callers(s32 *start, s32 *end) #define FINEIBT_WARN(_f, _v) \ WARN_ONCE((_f) != (_v), "FineIBT: " #_f " %ld != %d\n", _f, _v) -static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi, bool builtin) +static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi, bool builtin) { int ret; @@ -2088,8 +2088,8 @@ bool decode_fineibt_insn(struct pt_regs *regs, unsigned long *target, u32 *type) #else /* !CONFIG_FINEIBT: */ -static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi, bool builtin) +static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi, bool builtin) { if (IS_ENABLED(CONFIG_CFI) && builtin) pr_info("CFI: Using standard kCFI\n"); @@ -2101,8 +2101,8 @@ static void poison_cfi(void *addr) { } #endif /* !CONFIG_FINEIBT */ -void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi) +void __init_or_module apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi) { return __apply_fineibt(start_retpoline, end_retpoline, start_cfi, end_cfi, -- cgit v1.2.3 From b47748678c6cd831aba376f6b2d90b7718c7c661 Mon Sep 17 00:00:00 2001 From: Chao Gao Date: Thu, 19 Jun 2025 22:21:50 -0700 Subject: x86/fpu: Fix kernel-doc formatting above fpu_enable_guest_xfd_features() Adjust the indentation and use tabs between function parameters and their descriptions to align with the convention used in FPU code. Signed-off-by: Chao Gao Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20250620052152.490414-1-chao.gao@intel.com --- arch/x86/kernel/fpu/core.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/x86/kernel') diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 584fb9913be4..2ed26134c0d1 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -294,15 +294,15 @@ void fpu_free_guest_fpstate(struct fpu_guest *gfpu) } EXPORT_SYMBOL_FOR_KVM(fpu_free_guest_fpstate); -/* - * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable - * @guest_fpu: Pointer to the guest FPU container - * @xfeatures: Features requested by guest CPUID - * - * Enable all dynamic xfeatures according to guest perm and requested CPUID. - * - * Return: 0 on success, error code otherwise - */ +/** + * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable + * @guest_fpu: Pointer to the guest FPU container + * @xfeatures: Features requested by guest CPUID + * + * Enable all dynamic xfeatures according to guest perm and requested CPUID. + * + * Return: 0 on success, error code otherwise + */ int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures) { lockdep_assert_preemption_enabled(); -- cgit v1.2.3 From 77d34d39509341d76ab10f63ef67648545c90da1 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Wed, 13 May 2026 22:07:13 +0200 Subject: x86/cpu: Move intel_get_platform_id() to cpu/intel.c It is not only used in the microcode loader anymore and the platform ID is cached in the cpuinfo_x86 structure so move the getter to Intel CPU-specific code. No functional changes. Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Binbin Wu Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/all/20260430020953.1405535-1-binbin.wu@linux.intel.com --- arch/x86/include/asm/microcode.h | 2 -- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/intel.c | 35 ++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/microcode/intel.c | 36 ----------------------------------- 4 files changed, 36 insertions(+), 38 deletions(-) (limited to 'arch/x86/kernel') diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 9cd136d4515c..645e65ac1586 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -62,8 +62,6 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; } -extern u32 intel_get_platform_id(void); - static inline u32 intel_get_microcode_revision(void) { u32 rev, dummy; diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 87b1d4c0727e..8d8f890c4bc0 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -238,6 +238,7 @@ extern void early_cpu_init(void); extern void identify_secondary_cpu(unsigned int cpu); extern void print_cpu_info(struct cpuinfo_x86 *); void print_cpu_msr(struct cpuinfo_x86 *); +extern u32 intel_get_platform_id(void); /* * Friendlier CR3 helpers. diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index abb3984336eb..03073b90d2ec 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -199,6 +199,41 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) c->cpuid_level = cpuid_eax(0); } +/* + * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 + * structures are populated. + */ +static u32 intel_cpuid_vfm(void) +{ + u32 eax = cpuid_eax(1); + u32 fam = x86_family(eax); + u32 model = x86_model(eax); + + return IFM(fam, model); +} + +u32 intel_get_platform_id(void) +{ + unsigned int val[2]; + + if (x86_hypervisor_present) + return 0; + + /* + * This can be called early. Use CPUID directly instead of + * relying on cpuinfo_x86 which may not be fully initialized. + * The PII does not have MSR_IA32_PLATFORM_ID. Everything + * before _it_ has no microcode (for Linux at least). + */ + if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) + return 0; + + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + + return (val[1] >> 18) & 7; +} + static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f4a444e6114d..1142183c950c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -121,42 +121,6 @@ static inline unsigned int exttable_size(struct extended_sigtable *et) return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } - -/* - * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 - * structures are populated. - */ -static u32 intel_cpuid_vfm(void) -{ - u32 eax = cpuid_eax(1); - u32 fam = x86_family(eax); - u32 model = x86_model(eax); - - return IFM(fam, model); -} - -u32 intel_get_platform_id(void) -{ - unsigned int val[2]; - - if (x86_hypervisor_present) - return 0; - - /* - * This can be called early. Use CPUID directly instead of - * relying on cpuinfo_x86 which may not be fully initialized. - * The PII does not have MSR_IA32_PLATFORM_ID. Everything - * before _it_ has no microcode (for Linux at least). - */ - if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) - return 0; - - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - - return (val[1] >> 18) & 7; -} - void intel_collect_cpu_info(struct cpu_signature *sig) { sig->sig = cpuid_eax(1); -- cgit v1.2.3 From cdb4d57c3e497fe99a9ffa54f085b75130b12b5a Mon Sep 17 00:00:00 2001 From: Melody Wang Date: Wed, 8 Jul 2026 01:21:17 +0000 Subject: x86/apic: Ensure ICR register write value is handled as 32 bits The low 32-bit ICR data is prepared by __prepare_ICR(), which returns a 32-bit value. However, when this value is assigned to a new variable, it's easy to mistakenly declare that variable with a different width. To avoid this class of mistakes, use __prepare_ICR() directly as the function argument instead of storing its result in an intermediate variable. This also shaves off a bunch of lines in the code. There should be no functionality change resulting from this. Signed-off-by: Melody Wang Signed-off-by: Borislav Petkov (AMD) Acked-by: Thomas Gleixner Link: https://patch.msgid.link/20260708012117.177959-1-huibo.wang@amd.com --- arch/x86/kernel/apic/local.h | 4 +--- arch/x86/kernel/apic/x2apic_phys.c | 4 +--- arch/x86/kernel/apic/x2apic_savic.c | 5 +---- 3 files changed, 3 insertions(+), 10 deletions(-) (limited to 'arch/x86/kernel') diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 998efd442063..090dd71837aa 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,9 +44,7 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, #ifdef CONFIG_X86_X2APIC static inline void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) { - unsigned long cfg = __prepare_ICR(0, vector, dest); - - native_x2apic_icr_write(cfg, apicid); + native_x2apic_icr_write(__prepare_ICR(0, vector, dest), apicid); } #endif diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 10f79026e8e3..090647cc5a78 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -85,11 +85,9 @@ static void static void __x2apic_send_IPI_shorthand(int vector, u32 which) { - unsigned long cfg = __prepare_ICR(which, vector, 0); - /* x2apic MSRs are special and need a special fence: */ weak_wrmsr_fence(); - native_x2apic_icr_write(cfg, 0); + native_x2apic_icr_write(__prepare_ICR(which, vector, 0), 0); } void x2apic_send_IPI_allbutself(int vector) diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c index dbc5678bc3b6..4bc6d7e018a5 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -243,10 +243,7 @@ static void savic_write(u32 reg, u32 data) static void send_ipi(u32 dest, unsigned int vector, unsigned int dsh) { - unsigned int icr_low; - - icr_low = __prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL); - savic_icr_write(icr_low, dest); + savic_icr_write(__prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL), dest); } static void savic_send_ipi(int cpu, int vector) -- cgit v1.2.3 From b096d79bc1eed9eda57c12ccd76d6797cdba4cf2 Mon Sep 17 00:00:00 2001 From: Tim Wiederhake Date: Mon, 29 Jun 2026 19:37:59 +0200 Subject: x86/msr: Document the I/O-like write semantics in the msr driver Explain why msr_write() does not advance the index. [ bp: Massage commit message. ] Signed-off-by: Tim Wiederhake Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260629173759.1770596-1-twiederh@redhat.com --- arch/x86/kernel/msr.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/x86/kernel') diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 34bdb752f892..eb988df22521 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -13,6 +13,9 @@ * and then read/write in chunks of 8 bytes. A larger size means multiple * reads or writes of the same register. * + * Writing the same register multiple times can be useful for MSRs with + * I/O-like semantics, e.g. a virtual MSR that accepts logging information. + * * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on * an SMP box will direct the access to CPU %d. */ -- cgit v1.2.3 From 10b45e63a5b010be59ecbd2e437744adb12f838a Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 30 Jun 2026 10:30:30 +0200 Subject: x86/cpu: Remove unnecessary __maybe_unused annotations Remove __maybe_unused from variables and functions that are referenced unconditionally. Signed-off-by: Thorsten Blum Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260630083031.683508-2-thorsten.blum@linux.dev --- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 3 +-- arch/x86/kernel/cpu/topology_common.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/x86/kernel') diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a3df21d26460..63cab0554bc6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1651,7 +1651,7 @@ static inline bool parse_set_clear_cpuid(char *arg, bool set) int taint = 0; while (arg) { - bool found __maybe_unused = false; + bool found = false; unsigned int bit; opt = strsep(&arg, ","); diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 531dfb771c8b..6cdc410e7547 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -136,8 +136,7 @@ struct cont_desc { * Microcode patch container file is prepended to the initrd in cpio * format. See Documentation/arch/x86/microcode.rst */ -static const char -ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin"; +static const char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin"; /* * This is CPUID(1).EAX on the BSP. It is used in two ways: diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index cf7513416b70..f0b0a91fcf0f 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -62,7 +62,7 @@ const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) } } -static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) +static unsigned int parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { u32 cache_type : 5, -- cgit v1.2.3