From 7d970b893eff75c40226a641b43e95c3b2c341b4 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 22 Sep 2025 12:57:58 -0500 Subject: dt-bindings: arm: aspeed: add IBM Balcones board Document a new AST2600 BMC board for IBM P11 server. Signed-off-by: Eddie James Reviewed-by: Rob Herring (Arm) Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..b2fcfcc4a3b9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -93,6 +93,7 @@ properties: - facebook,minerva-cmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc + - ibm,balcones-bmc - ibm,blueridge-bmc - ibm,everest-bmc - ibm,fuji-bmc -- cgit v1.2.3 From fa2d3aa180c888ba63a6c1d3fd273c8e4494b79f Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 22 Sep 2025 12:57:59 -0500 Subject: dt-bindings: arm: aspeed: add IBM Bonnell board Document the existing AST2600 BMC board for IBM P10 server. Signed-off-by: Eddie James Reviewed-by: Rob Herring (Arm) Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index b2fcfcc4a3b9..9730df98b945 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -95,6 +95,7 @@ properties: - facebook,yosemite4-bmc - ibm,balcones-bmc - ibm,blueridge-bmc + - ibm,bonnell-bmc - ibm,everest-bmc - ibm,fuji-bmc - ibm,rainier-bmc -- cgit v1.2.3 From 3d37117ab43ff57577b922c53ef12260956a9330 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Thu, 18 Sep 2025 20:17:47 +0800 Subject: dt-bindings: arm64: mediatek: add mt8395-evk-ufs board Add a compatible string for the MediaTek mt8395-evk-ufs board. This board is the origin Genio 1200 EVK already mounted two main storages, one is eMMC, and the other is UFS. The system automatically prioritizes between eMMC and UFS via BROM detection, so user could not use both storage types simultaneously. As a result, mt8395-evk-ufs must be treated as a separate board. Signed-off-by: Macpaul Lin Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index f04277873694..2c5c92b87b3a 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -445,6 +445,7 @@ properties: - enum: - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk + - mediatek,mt8395-evk-ufs - radxa,nio-12l - const: mediatek,mt8395 - const: mediatek,mt8195 -- cgit v1.2.3 From 10dee355bdc1a8409babc71e5aa36c7d7f995910 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Sat, 20 Sep 2025 20:23:34 +0200 Subject: dt-bindings: arm: mediatek: Add MT6582 yarisxl Add an entry for Alcatel Pop C7 (OT-7041D) smartphone board, named yarisxl, based on MT6582 SoC. Signed-off-by: Cristian Cozzolino Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index f04277873694..5dce019cc998 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -38,6 +38,7 @@ properties: - const: mediatek,mt6580 - items: - enum: + - alcatel,yarisxl - prestigio,pmt5008-3g - const: mediatek,mt6582 - items: -- cgit v1.2.3 From 75e700fa357876bc4f501f585c2cc335acc8c237 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 27 Sep 2025 17:23:09 +0800 Subject: dt-bindings: arm: rockchip: Add FriendlyElec NanoPi R76S The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway device with two 2.5G, designed and developed by FriendlyElec. Add devicetree binding documentation for the FriendlyElec NanoPi R76S board. Acked-by: Rob Herring (Arm) Signed-off-by: Tianling Shen Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6aceaa8acbb2..e8185344c6f0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -330,6 +330,11 @@ properties: - friendlyarm,nanopi-r6s - const: rockchip,rk3588s + - description: FriendlyElec NanoPi R76S + items: + - const: friendlyarm,nanopi-r76s + - const: rockchip,rk3576 + - description: FriendlyElec NanoPi Zero2 items: - const: friendlyarm,nanopi-zero2 -- cgit v1.2.3 From 8b811220eb294ae30634af6597e1d992f5ff9193 Mon Sep 17 00:00:00 2001 From: Kevin Tung Date: Wed, 1 Oct 2025 16:47:50 +0800 Subject: dt-bindings: arm: aspeed: add Meta Yosemite5 board Document the new compatibles used on Meta Yosemite5. Signed-off-by: Kevin Tung Acked-by: Conor Dooley Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9730df98b945..9298c1a75dd1 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -93,6 +93,7 @@ properties: - facebook,minerva-cmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc + - facebook,yosemite5-bmc - ibm,balcones-bmc - ibm,blueridge-bmc - ibm,bonnell-bmc -- cgit v1.2.3 From e4c4f5a1ae18a7828c2bfaf9dfe2473632b92d1b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 3 Oct 2025 20:14:38 +0200 Subject: dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets Some of the USB4 muxes, RCGs and resets were not initially described. Add indices for them to allow extending the driver. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,x1e80100-gcc.yaml | 62 ++++++++++++++++++++-- include/dt-bindings/clock/qcom,x1e80100-gcc.h | 61 +++++++++++++++++++++ 2 files changed, 119 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 68dde0720c71..1b15b5070954 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -32,9 +32,36 @@ properties: - description: PCIe 5 pipe clock - description: PCIe 6a pipe clock - description: PCIe 6b pipe clock - - description: USB QMP Phy 0 clock source - - description: USB QMP Phy 1 clock source - - description: USB QMP Phy 2 clock source + - description: USB4_0 QMPPHY clock source + - description: USB4_1 QMPPHY clock source + - description: USB4_2 QMPPHY clock source + - description: USB4_0 PHY DP0 GMUX clock source + - description: USB4_0 PHY DP1 GMUX clock source + - description: USB4_0 PHY PCIE PIPEGMUX clock source + - description: USB4_0 PHY PIPEGMUX clock source + - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_1 PHY DP0 GMUX 2 clock source + - description: USB4_1 PHY DP1 GMUX 2 clock source + - description: USB4_1 PHY PCIE PIPEGMUX clock source + - description: USB4_1 PHY PIPEGMUX clock source + - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_2 PHY DP0 GMUX 2 clock source + - description: USB4_2 PHY DP1 GMUX 2 clock source + - description: USB4_2 PHY PCIE PIPEGMUX clock source + - description: USB4_2 PHY PIPEGMUX clock source + - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_0 PHY RX 0 clock source + - description: USB4_0 PHY RX 1 clock source + - description: USB4_1 PHY RX 0 clock source + - description: USB4_1 PHY RX 1 clock source + - description: USB4_2 PHY RX 0 clock source + - description: USB4_2 PHY RX 1 clock source + - description: USB4_0 PHY PCIE PIPE clock source + - description: USB4_0 PHY max PIPE clock source + - description: USB4_1 PHY PCIE PIPE clock source + - description: USB4_1 PHY max PIPE clock source + - description: USB4_2 PHY PCIE PIPE clock source + - description: USB4_2 PHY max PIPE clock source power-domains: description: @@ -67,7 +94,34 @@ examples: <&pcie6b_phy>, <&usb_1_ss0_qmpphy 0>, <&usb_1_ss1_qmpphy 1>, - <&usb_1_ss2_qmpphy 2>; + <&usb_1_ss2_qmpphy 2>, + <&usb4_0_phy_dp0_gmux_clk>, + <&usb4_0_phy_dp1_gmux_clk>, + <&usb4_0_phy_pcie_pipegmux_clk>, + <&usb4_0_phy_pipegmux_clk>, + <&usb4_0_phy_sys_pcie_pipegmux_clk>, + <&usb4_1_phy_dp0_gmux_2_clk>, + <&usb4_1_phy_dp1_gmux_2_clk>, + <&usb4_1_phy_pcie_pipegmux_clk>, + <&usb4_1_phy_pipegmux_clk>, + <&usb4_1_phy_sys_pcie_pipegmux_clk>, + <&usb4_2_phy_dp0_gmux_2_clk>, + <&usb4_2_phy_dp1_gmux_2_clk>, + <&usb4_2_phy_pcie_pipegmux_clk>, + <&usb4_2_phy_pipegmux_clk>, + <&usb4_2_phy_sys_pcie_pipegmux_clk>, + <&usb4_0_phy_rx_0_clk>, + <&usb4_0_phy_rx_1_clk>, + <&usb4_1_phy_rx_0_clk>, + <&usb4_1_phy_rx_1_clk>, + <&usb4_2_phy_rx_0_clk>, + <&usb4_2_phy_rx_1_clk>, + <&usb4_0_phy_pcie_pipe_clk>, + <&usb4_0_phy_max_pipe_clk>, + <&usb4_1_phy_pcie_pipe_clk>, + <&usb4_1_phy_max_pipe_clk>, + <&usb4_2_phy_pcie_pipe_clk>, + <&usb4_2_phy_max_pipe_clk>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 710c340f24a5..62aa12425592 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -363,6 +363,30 @@ #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357 +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358 +#define GCC_USB4_0_PHY_DP0_CLK_SRC 359 +#define GCC_USB4_0_PHY_DP1_CLK_SRC 360 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362 +#define GCC_USB4_0_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_0_PHY_RX1_CLK_SRC 364 +#define GCC_USB4_0_PHY_SYS_CLK_SRC 365 +#define GCC_USB4_1_PHY_DP0_CLK_SRC 366 +#define GCC_USB4_1_PHY_DP1_CLK_SRC 367 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 370 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 371 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 372 +#define GCC_USB4_2_PHY_DP0_CLK_SRC 373 +#define GCC_USB4_2_PHY_DP1_CLK_SRC 374 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375 +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376 +#define GCC_USB4_2_PHY_RX0_CLK_SRC 377 +#define GCC_USB4_2_PHY_RX1_CLK_SRC 378 +#define GCC_USB4_2_PHY_SYS_CLK_SRC 379 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 @@ -484,4 +508,41 @@ #define GCC_VIDEO_BCR 87 #define GCC_VIDEO_AXI0_CLK_ARES 88 #define GCC_VIDEO_AXI1_CLK_ARES 89 +#define GCC_USB4_0_MISC_USB4_SYS_BCR 90 +#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91 +#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92 +#define GCC_USB4_0_MISC_USB_PIPE_BCR 93 +#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94 +#define GCC_USB4_0_MISC_TMU_BCR 95 +#define GCC_USB4_0_MISC_SB_IF_BCR 96 +#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97 +#define GCC_USB4_0_MISC_AHB_BCR 98 +#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99 +#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100 +#define GCC_USB4_1_MISC_USB4_SYS_BCR 101 +#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102 +#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103 +#define GCC_USB4_1_MISC_USB_PIPE_BCR 104 +#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105 +#define GCC_USB4_1_MISC_TMU_BCR 106 +#define GCC_USB4_1_MISC_SB_IF_BCR 107 +#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108 +#define GCC_USB4_1_MISC_AHB_BCR 109 +#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110 +#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111 +#define GCC_USB4_2_MISC_USB4_SYS_BCR 112 +#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113 +#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114 +#define GCC_USB4_2_MISC_USB_PIPE_BCR 115 +#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116 +#define GCC_USB4_2_MISC_TMU_BCR 117 +#define GCC_USB4_2_MISC_SB_IF_BCR 118 +#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119 +#define GCC_USB4_2_MISC_AHB_BCR 120 +#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121 +#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122 +#define GCC_USB4PHY_PHY_PRIM_BCR 123 +#define GCC_USB4PHY_PHY_SEC_BCR 124 +#define GCC_USB4PHY_PHY_TERT_BCR 125 + #endif -- cgit v1.2.3 From 83c4e3c39b2b55afe56ed0d14b93b5f219350c81 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 10 Oct 2025 12:46:31 +0000 Subject: dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks The firmware exposes clocks that can be controlled via the Alive Clock and Power Manager (ACPM) interface. Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring (Arm) Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole Link: https://patch.msgid.link/20251010-acpm-clk-v6-1-321ee8826fd4@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 11 +++++++++ include/dt-bindings/clock/google,gs101-acpm.h | 26 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 include/dt-bindings/clock/google,gs101-acpm.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml index 9785aac3b5f3..d3bca6088d12 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -24,6 +24,15 @@ properties: compatible: const: google,gs101-acpm-ipc + "#clock-cells": + const: 1 + description: + Clocks that are variable and index based. These clocks don't provide + an entire range of values between the limits but only discrete points + within the range. The firmware also manages the voltage scaling + appropriately with the clock scaling. The argument is the ID of the + clock contained by the firmware messages. + mboxes: maxItems: 1 @@ -45,6 +54,7 @@ properties: required: - compatible + - "#clock-cells" - mboxes - shmem @@ -56,6 +66,7 @@ examples: power-management { compatible = "google,gs101-acpm-ipc"; + #clock-cells = <1>; mboxes = <&ap2apm_mailbox>; shmem = <&apm_sram>; diff --git a/include/dt-bindings/clock/google,gs101-acpm.h b/include/dt-bindings/clock/google,gs101-acpm.h new file mode 100644 index 000000000000..e2ba89e09fa6 --- /dev/null +++ b/include/dt-bindings/clock/google,gs101-acpm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 Linaro Ltd. + * + * Device Tree binding constants for Google gs101 ACPM clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H + +#define GS101_CLK_ACPM_DVFS_MIF 0 +#define GS101_CLK_ACPM_DVFS_INT 1 +#define GS101_CLK_ACPM_DVFS_CPUCL0 2 +#define GS101_CLK_ACPM_DVFS_CPUCL1 3 +#define GS101_CLK_ACPM_DVFS_CPUCL2 4 +#define GS101_CLK_ACPM_DVFS_G3D 5 +#define GS101_CLK_ACPM_DVFS_G3DL2 6 +#define GS101_CLK_ACPM_DVFS_TPU 7 +#define GS101_CLK_ACPM_DVFS_INTCAM 8 +#define GS101_CLK_ACPM_DVFS_TNR 9 +#define GS101_CLK_ACPM_DVFS_CAM 10 +#define GS101_CLK_ACPM_DVFS_MFC 11 +#define GS101_CLK_ACPM_DVFS_DISP 12 +#define GS101_CLK_ACPM_DVFS_BO 13 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */ -- cgit v1.2.3 From cf3c07f4da9db1a4ade6f2af814b9bf5b6a3a687 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Mon, 22 Sep 2025 13:10:55 +0200 Subject: dt-bindings: arm: fsl: add compatible for Skov i.MX8MP variant In preparation for adding a new device tree variant with a different panel, describe the DT compatible in the binding. Signed-off-by: Steffen Trumtrar Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 00cdf490b062..c5d81e3f8bd1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1111,6 +1111,7 @@ properties: - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate + - skov,imx8mp-skov-revc-jutouch-jt101tm023 # SKOV i.MX8MP climate control with 10" JuTouch panel - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board -- cgit v1.2.3 From f679e54e6755c5602c0a31951370858bdc21c39a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 10 Sep 2025 20:34:02 -0300 Subject: dt-bindings: soc: imx-iomuxc-gpr: Document the CSI mux On i.MX6Q/6DL the following subnodes exist to describe the CSI port muxing: - ipu1_csi0_mux - ipu1_csi1_mux - ipu2_csi0_mux - ipu2_csi1_mux As they were not documented, dt-schema emits warnings like: 'ipu1_csi0_mux', 'ipu1_csi1_mux' do not match any of the regexes: '^pinctrl-[0-9]+$' Add a top-level patternProperties entry for these CSI mux subnodes and restrict it to i.MX6Q. Signed-off-by: Fabio Estevam Acked-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index b77ce8c6a935..721a67e84c13 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -51,6 +51,22 @@ properties: type: object $ref: /schemas/mux/reg-mux.yaml +patternProperties: + "^ipu[12]_csi[01]_mux$": + type: object + $ref: /schemas/media/video-mux.yaml + +allOf: + - if: + properties: + compatible: + not: + contains: + const: fsl,imx6q-iomuxc-gpr + then: + patternProperties: + '^ipu[12]_csi[01]_mux$': false + additionalProperties: false required: -- cgit v1.2.3 From 9e38dc1abce6fb776d4b6731ccc64ad25e525d39 Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Tue, 14 Oct 2025 13:12:24 +0800 Subject: dt-bindings: vendor-prefixes: Document LinkEase LinkEase is a company focusing on the research and development of network equipment and related software and hardware from Shenzhen. Add vendor prefix for it. Acked-by: Conor Dooley Signed-off-by: Liangbin Lian Link: https://patch.msgid.link/20251014051226.64255-2-jjm2473@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..003cc91fb02f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -907,6 +907,8 @@ patternProperties: description: Lincoln Technology Solutions "^lineartechnology,.*": description: Linear Technology + "^linkease,.*": + description: Shenzhen LinkEase Network Technology Co., Ltd. "^linksprite,.*": description: LinkSprite Technologies, Inc. "^linksys,.*": -- cgit v1.2.3 From fc3cd4021eeecb9adbe030b8cf32587126775d8e Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Tue, 14 Oct 2025 13:12:25 +0800 Subject: dt-bindings: arm: rockchip: Add LinkEase EasePi R1 LinkEase EasePi R1 is a high-performance mini router based on RK3568. Acked-by: Conor Dooley Signed-off-by: Liangbin Lian Link: https://patch.msgid.link/20251014051226.64255-3-jjm2473@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e8185344c6f0..f7072b968fa7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -753,6 +753,11 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 + - description: LinkEase EasePi R1 + items: + - const: linkease,easepi-r1 + - const: rockchip,rk3568 + - description: Luckfox Core3576 Module based boards items: - enum: -- cgit v1.2.3 From ff29a83cda0f6eebb57d14f0a6456e3d1e5dc7c3 Mon Sep 17 00:00:00 2001 From: Hsun Lai Date: Tue, 14 Oct 2025 10:16:13 +0800 Subject: dt-bindings: arm: rockchip: Add 100ASK DShanPi A1 This documents 100ASK DShanPi A1 which is a SBC based on RK3576 SoC. Link: https://wiki.dshanpi.org/en/docs/DshanPi-A1/intro/ Signed-off-by: Hsun Lai Acked-by: Conor Dooley Link: https://patch.msgid.link/0601AB836AE5F348+20251014021623.286121-2-i@chainsx.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index f7072b968fa7..ba61ea743613 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -15,6 +15,11 @@ properties: compatible: oneOf: + - description: 100ASK DshanPi A1 board + items: + - const: 100ask,dshanpi-a1 + - const: rockchip,rk3576 + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) items: - const: vamrs,ficus -- cgit v1.2.3 From 4430d52cd7249fb53756d26ab409caac55ac1537 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 15 Oct 2025 08:13:37 +0800 Subject: dt-bindings: mtd: cdns,hp-nfc: Add iommu property Agilex5 integrates an ARM SMMU (System Memory Management Unit) with Translation Buffer Units (TBUs) assigned to various peripherals, including the NAND controller. The Cadence HP NAND controller ("cdns,hp-nfc") on Agilex5 is behind a TBU connected to the system's SMMUv3. To support this, the controller requires an `iommus` property in the device tree to properly configure address translation through the IOMMU framework. Adding the `iommus` property to the binding schema allows the OS to associate the NAND controller with its corresponding SMMU stream ID. This enables: - DMA address translation between the controller and system memory - Memory protection for NAND operations - Proper functioning of the IOMMU framework in secure or virtualized environments This change documents the IOMMU integration for the NAND controller on platforms like Agilex5 where such hardware is present. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Khairul Anuar Romli Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml index e1f4d7c35a88..73dc69cee4d8 100644 --- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml +++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml @@ -40,6 +40,9 @@ properties: dmas: maxItems: 1 + iommus: + maxItems: 1 + cdns,board-delay-ps: description: | Estimated Board delay. The value includes the total round trip -- cgit v1.2.3 From 2c83769b2f29d6c6b93d1e0f0c23bbd0ce84b241 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 15 Oct 2025 08:13:38 +0800 Subject: dt-bindings: dma: snps,dw-axi-dmac: Add iommu property Agilex5 integrates an ARM SMMU v3 (System Memory Management Unit) with dedicated Translation Buffer Units (TBUs) assigned to various peripherals, including the Synopsys DesignWare AXI DMA controller. Each TBU handles address translation for its associated device by mapping stream IDs to memory access permissions and virtual-to-physical address mappings via the SMMU core. The DesignWare AXI DMAC instances on Agilex5 are connected to their respective TBUs. These TBUs forward DMA transactions from the controller through the SMMU, enabling IOMMU-based features such as: - Address translation for DMA operations - Isolation and protection of memory regions accessed by the DMA controller - Support for secure and virtualized environments through enforced access control To support this configuration, the `iommus` property must be added to the binding schema for `snps,dw-axi-dmac`. This allows the device tree to associate each DMA controller with the correct SMMU stream ID, enabling the Linux IOMMU framework to configure translation contexts at runtime. This change documents the IOMMU support for the DMA controller on Agilex5 and allows proper integration with the SMMUv3 hardware. Signed-off-by: Adrian Ng Ho Yin Signed-off-by: Khairul Anuar Romli Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 935735a59afd..a393a33c8908 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -42,6 +42,9 @@ properties: minItems: 1 maxItems: 8 + iommus: + maxItems: 1 + clocks: items: - description: Bus Clock -- cgit v1.2.3 From 72459d90793a54223b97d2d3d5ff2325c5ec3e15 Mon Sep 17 00:00:00 2001 From: Lothar Rubusch Date: Sat, 18 Oct 2025 12:11:48 +0000 Subject: dt-bindings: altera: add Enclustra Mercury SA1 Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 30c44a0e6407..30ef03c53d73 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -52,6 +52,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: -- cgit v1.2.3 From 729ef2397223e850fe1e8b7f2b0198c549ff5a6c Mon Sep 17 00:00:00 2001 From: Lothar Rubusch Date: Sat, 18 Oct 2025 12:11:50 +0000 Subject: dt-bindings: altera: add binding for Mercury+ SA2 Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 30ef03c53d73..72cf04b22a08 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -62,6 +62,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: -- cgit v1.2.3 From a31736de523a325946d74d27ac04881ff9bf5c71 Mon Sep 17 00:00:00 2001 From: Lothar Rubusch Date: Sat, 18 Oct 2025 12:11:52 +0000 Subject: dt-bindings: altera: add Mercury AA1 variants Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 72cf04b22a08..227665d0016f 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,6 +31,9 @@ properties: - description: Mercury+ AA1 boards items: - enum: + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 -- cgit v1.2.3 From 558417387bc76fc4baec5c540bc734eacb684800 Mon Sep 17 00:00:00 2001 From: Lothar Rubusch Date: Sat, 18 Oct 2025 12:11:54 +0000 Subject: dt-bindings: altera: removal of generic PE1 dts Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 227665d0016f..db61537b7115 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -34,7 +34,6 @@ properties: - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 - - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 -- cgit v1.2.3 From e260e8114eff40a7d0e2be4070007979a5336435 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Thu, 18 Sep 2025 16:14:40 +1000 Subject: dt-bindings: embedded-controller: add Traverse Ten64 board controller Add device tree binding for the board (micro)controller on Ten64 family boards[1]. The schema is simple and is (presently) only consumed by U-Boot, but it is possible nvmem, watchdog and other features could be described in the future, as well as extension to future Traverse boards. [1] https://ten64doc.traverse.com.au/hardware/microcontroller/ Signed-off-by: Mathew McBride Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- .../traverse,ten64-controller.yaml | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/embedded-controller/traverse,ten64-controller.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/embedded-controller/traverse,ten64-controller.yaml b/Documentation/devicetree/bindings/embedded-controller/traverse,ten64-controller.yaml new file mode 100644 index 000000000000..08d02c4df873 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/traverse,ten64-controller.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/traverse,ten64-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Traverse Ten64 board microcontroller + +maintainers: + - Mathew McBride + +description: | + The board microcontroller on the Ten64 board family is responsible for + management of power sources on the board, as well as signalling the SoC + to power on and reset. + +properties: + compatible: + const: traverse,ten64-controller + + reg: + const: 0x7e + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; + }; -- cgit v1.2.3 From fbfbc68852edc17c825796419936ea1aed521c95 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:27 +0800 Subject: dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 example The Networking Subsystem (NSS) clock controller acts as both a clock provider and an interconnect provider. The #interconnect-cells property is needed in the Device Tree Source (DTS) to ensure that client drivers such as the PPE driver can correctly acquire ICC clocks from the NSS ICC provider. Add the #interconnect-cells property to the IPQ9574 Device Tree binding example to complete it. Fixes: 28300ecedce4 ("dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions") Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 17252b6ea3be..5d35925e60d0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -94,5 +94,6 @@ examples: "bus"; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; ... -- cgit v1.2.3 From 06ac2566e73d9d9fa2be62315e182945f7934882 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:32 +0800 Subject: dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC NSS clock controller provides the clocks and resets to the networking blocks such as PPE (Packet Process Engine) and UNIPHY (PCS) on IPQ5424 devices. Add support for the compatible string "qcom,ipq5424-nsscc" based on the existing IPQ9574 NSS clock controller Device Tree binding. Additionally, update the clock names for PPE and NSS for newer SoC additions like IPQ5424 to use generic and reusable identifiers "nss" and "ppe" without the clock rate suffix. Also add master/slave ids for IPQ5424 networking interfaces, which is used by nss-ipq5424 driver for providing interconnect services using icc-clk framework. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-7-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq9574-nsscc.yaml | 62 ++++++++++++++++++--- include/dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 ++++++++++++++++++++++ include/dt-bindings/interconnect/qcom,ipq5424.h | 13 +++++ include/dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +++++++++++++++ 4 files changed, 178 insertions(+), 8 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,ipq5424-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq5424-nsscc.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 5d35925e60d0..7ff4ff3587ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 maintainers: - Bjorn Andersson @@ -12,21 +12,29 @@ maintainers: description: | Qualcomm networking sub system clock control module provides the clocks, - resets on IPQ9574 + resets on IPQ9574 and IPQ5424 - See also:: + See also: + include/dt-bindings/clock/qcom,ipq5424-nsscc.h include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq5424-nsscc.h include/dt-bindings/reset/qcom,ipq9574-nsscc.h properties: compatible: - const: qcom,ipq9574-nsscc + enum: + - qcom,ipq5424-nsscc + - qcom,ipq9574-nsscc clocks: items: - description: Board XO source - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate + can vary for different IPQ SoCs. For example, it is 1200 MHz on the + IPQ9574 and 300 MHz on the IPQ5424. + - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock + rate can vary for different IPQ SoCs. For example, it is 353 MHz + on the IPQ9574 and 375 MHz on the IPQ5424. - description: GCC GPLL0 OUT AUX clock source - description: Uniphy0 NSS Rx clock source - description: Uniphy0 NSS Tx clock source @@ -42,8 +50,12 @@ properties: clock-names: items: - const: xo - - const: nss_1200 - - const: ppe_353 + - enum: + - nss_1200 + - nss + - enum: + - ppe_353 + - ppe - const: gpll0_out - const: uniphy0_rx - const: uniphy0_tx @@ -60,6 +72,40 @@ required: allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + const: qcom,ipq9574-nsscc + then: + properties: + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + else: + properties: + clock-names: + items: + - const: xo + - const: nss + - const: ppe + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus unevaluatedProperties: false diff --git a/include/dt-bindings/clock/qcom,ipq5424-nsscc.h b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..eeae0dc38042 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PORT3_MAC_CLK 28 +#define NSS_CC_PORT3_RX_CLK 29 +#define NSS_CC_PORT3_RX_CLK_SRC 30 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 +#define NSS_CC_PORT3_TX_CLK 32 +#define NSS_CC_PORT3_TX_CLK_SRC 33 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_CC_PPE_CLK_SRC 35 +#define NSS_CC_PPE_EDMA_CFG_CLK 36 +#define NSS_CC_PPE_EDMA_CLK 37 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 38 +#define NSS_CC_PPE_SWITCH_CFG_CLK 39 +#define NSS_CC_PPE_SWITCH_CLK 40 +#define NSS_CC_PPE_SWITCH_IPE_CLK 41 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 42 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 43 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 44 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 45 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 46 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 47 +#define NSS_CC_XGMAC0_PTP_REF_CLK 48 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 +#define NSS_CC_XGMAC1_PTP_REF_CLK 50 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 +#define NSS_CC_XGMAC2_PTP_REF_CLK 52 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index c5e0dec0b300..07b786bee7d6 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -44,4 +44,17 @@ #define MASTER_CPU 0 #define SLAVE_L3 1 +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_AXI 6 +#define SLAVE_NSSNOC_CE_AXI 7 +#define MASTER_NSSNOC_CE_APB 8 +#define SLAVE_NSSNOC_CE_APB 9 +#define MASTER_NSSNOC_EIP 10 +#define SLAVE_NSSNOC_EIP 11 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ diff --git a/include/dt-bindings/reset/qcom,ipq5424-nsscc.h b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..9627e3b0ad30 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PORT3_MAC_CLK_ARES 17 +#define NSS_CC_PORT3_RX_CLK_ARES 18 +#define NSS_CC_PORT3_TX_CLK_ARES 19 +#define NSS_CC_PPE_BCR 20 +#define NSS_CC_PPE_EDMA_CLK_ARES 21 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23 +#define NSS_CC_PPE_SWITCH_CLK_ARES 24 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30 +#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31 +#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34 +#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35 + +#endif -- cgit v1.2.3 From 5a0236736e0904902770933769600af68b648e44 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Sep 2025 22:51:54 +0200 Subject: dt-bindings: arm: imx: document i.MX 95 Verdin Evaluation Kit (EVK) Document support for i.MX 95 Verdin Evaluation Kit (EVK), which used to be the Titan EVK. Note that the SoM used in this EVK is a derivative SoM from Verdin line of SoMs, an actual i.MX95 Verdin SoM is under development. [1] https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95-evaluation-kit Acked-by: Rob Herring (Arm) Reviewed-by: Daniel Baluta Reviewed-by: Francesco Dolcini Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c5d81e3f8bd1..abc4e5d6a854 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1431,6 +1431,7 @@ properties: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 - description: PHYTEC i.MX 95 FPSC based Boards -- cgit v1.2.3 From e2525826241872ac0141371b1ea8e11e2f11a689 Mon Sep 17 00:00:00 2001 From: Jonas Rebmann Date: Tue, 14 Oct 2025 15:09:31 +0200 Subject: dt-bindings: arm: fsl: Add Protonic PRT8ML Add DT compatible string for Protonic PRT8ML board. Acked-by: Rob Herring (Arm) Signed-off-by: Jonas Rebmann Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index abc4e5d6a854..21b7168d61f5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1106,6 +1106,7 @@ properties: - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board - gocontroll,moduline-display # GOcontroll Moduline Display controller + - prt,prt8ml # Protonic PRT8ML - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel -- cgit v1.2.3 From b8ac5ceef28acbf6e0b00bdac055d3462580bef5 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 14 Oct 2025 18:53:51 +0300 Subject: dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA Extend the list of supported compatible strings with fsl,lx2160ardb-fpga. Since the register map exposed by the LX2160ARDB's FPGA also contains two GPIO controllers, accept the necessary GPIO pattern property. At the same time, add the #address-cells and #size-cells properties as valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are addressable. This is necessary because when defining child devices such as the GPIO controller described in the added example, the child device needs a the reg property to properly identify its register location in the parent I2C device address space. Impose this restriction for the new compatible through an if-statement. The feature set exposed by these QIXIS FPGA devices is highly dependent on the board type, meaning that even though the FPGA found on the LX2160AQDS board (fsl,lx2160aqds-fpga) works in the same way in terms of access over I2C as the one found on the LX2160ARDB (fsl,lx2160ardb-fpga added here), the register map inside the device space is different since there are different on-board devices to be controlled. Signed-off-by: Ioana Ciornei Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- .../bindings/board/fsl,fpga-qixis-i2c.yaml | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml index 28b37772fb65..e889dac052e7 100644 --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml @@ -22,6 +22,13 @@ properties: - fsl,lx2160aqds-fpga - const: fsl,fpga-qixis-i2c - const: simple-mfd + - const: fsl,lx2160ardb-fpga + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 interrupts: maxItems: 1 @@ -32,10 +39,37 @@ properties: mux-controller: $ref: /schemas/mux/reg-mux.yaml +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + enum: + - fsl,lx2160ardb-fpga-gpio-sfp + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,lx2160ardb-fpga + then: + required: + - "#address-cells" + - "#size-cells" + else: + properties: + "#address-cells": false + "#size-cells": false + additionalProperties: false examples: @@ -68,3 +102,27 @@ examples: }; }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + board-control@66 { + compatible = "fsl,lx2160ardb-fpga"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@19 { + compatible = "fsl,lx2160ardb-fpga-gpio-sfp"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP2_TX_EN", "", + "", "", + "SFP2_RX_LOS", "SFP2_TX_FAULT", + "", "SFP2_MOD_ABS"; + }; + }; + }; -- cgit v1.2.3 From 2346a408b4f2b8f9ea3778deb40a91c774e463b6 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 14 Oct 2025 18:53:52 +0300 Subject: dt-bindings: fsl,fpga-qixis: describe the gpio child node found on LS1046AQDS Extend the list of accepted child nodes with the QIXIS FPGA based GPIO controller and explicitly list its compatible string fsl,ls1046aqds-fpga-gpio-stat-pres2 as the only one accepted. Signed-off-by: Ioana Ciornei Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml index 5a3cd431ef6e..2eacb581b9fd 100644 --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml @@ -57,6 +57,16 @@ patternProperties: '^mdio-mux@[a-f0-9,]+$': $ref: /schemas/net/mdio-mux-mmioreg.yaml + '^gpio@[0-9a-f]+$': + type: object + additionalProperties: true + + properties: + compatible: + contains: + enum: + - fsl,ls1046aqds-fpga-gpio-stat-pres2 + required: - compatible - reg -- cgit v1.2.3 From 1ade4b89d84656744acd60d5c826923451f5c23b Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 27 Sep 2025 15:21:35 +0200 Subject: dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED variants X1/X1 Plus variant of the said device comes in either FHD+ OLED or FHD+ LCD panel, and shares the same model number UX3407QA. It appears LCD panel's brightness adjustment is PWM backlight controlled, so a dedicated device-tree is required. Introduce dedicated compatibles with fallback to 'asus,zenbook-a14-ux3407qa' as they are otherwise the same. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250927-zenbook-improvements-v3-1-d46c7368dc70@vinarskis.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 18b5ed044f9f..abdc39c025aa 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1083,7 +1083,13 @@ properties: - items: - enum: - - asus,zenbook-a14-ux3407qa + - asus,zenbook-a14-ux3407qa-lcd + - asus,zenbook-a14-ux3407qa-oled + - const: asus,zenbook-a14-ux3407qa + - const: qcom,x1p42100 + + - items: + - enum: - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd -- cgit v1.2.3 From 8388ebac980201382941600d4d9a2dc0bc1c9db4 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Mon, 29 Sep 2025 14:46:41 +0800 Subject: dt-bindings: arm: qcom: Add Radxa Dragon Q6A Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Document the top-level compatible for this board. Acked-by: Krzysztof Kozlowski Signed-off-by: Xilin Wu Link: https://lore.kernel.org/r/20250929-radxa-dragon-q6a-v5-1-aa96ffc352f8@radxa.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index abdc39c025aa..850bd9180bab 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -340,6 +340,7 @@ properties: - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - radxa,dragon-q6a - shift,otter - const: qcom,qcm6490 -- cgit v1.2.3 From bfc5cabaa4979f6645c851759b4242f9efe4f106 Mon Sep 17 00:00:00 2001 From: Jingzhou Zhu Date: Wed, 8 Oct 2025 21:00:51 +0800 Subject: dt-bindings: arm: qcom: Document Huawei MateBook E 2019 Add compatible for the sdm850-based tablet Huawei MateBook E 2019 using its codename "planck". Acked-by: Krzysztof Kozlowski Signed-off-by: Jingzhou Zhu Link: https://lore.kernel.org/r/20251008130052.11427-2-newwheatzjz@zohomail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 850bd9180bab..ae2fab820c79 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -894,6 +894,7 @@ properties: - items: - enum: + - huawei,planck - lenovo,yoga-c630 - lg,judyln - lg,judyp -- cgit v1.2.3 From bc42d98593535ccca739f67d9b9cb859f4e13304 Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Wed, 8 Oct 2025 21:20:19 +0300 Subject: dt-bindings: arm: qcom: Add Asus ZenFone 2 Laser/Selfie Add a compatible for Asus ZenFone 2 Laser/Selfie (1080p) Signed-off-by: Erikas Bitovtas Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251008182106.217340-2-xerikasxx@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae2fab820c79..df3dd0798a7d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -88,6 +88,7 @@ properties: - items: - enum: + - asus,z00t - huawei,kiwi - longcheer,l9100 - samsung,a7 -- cgit v1.2.3 From 1a614267281fa477b7d1eeb7b225f106161eb739 Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Tue, 14 Oct 2025 16:04:25 +0200 Subject: dt-bindings: arm: qcom: Add Xiaomi Redmi 3S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document Xiaomi Redmi 3S (land). Add qcom,msm8937 for msm-id, board-id allow-list. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20251014-msm8937-v10-2-b3e8da82e968@mainlining.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index df3dd0798a7d..d84bd3bca201 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -192,6 +192,11 @@ properties: - xiaomi,riva - const: qcom,msm8917 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - flipkart,rimob @@ -1176,6 +1181,7 @@ allOf: - qcom,apq8094 - qcom,apq8096 - qcom,msm8917 + - qcom,msm8937 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 -- cgit v1.2.3 From 697fbb43aba6dae48cbe5e1fa0d3023a0b12ab73 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Oct 2025 20:56:42 +0800 Subject: dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatibles for A523 There are two DMA controllers on the A523, one in the main system area and the other for the MCU. These are the same as the one found on the A100. The only difference is the DMA endpoint (DRQ) layout. Since the number of channels and endpoints are described with additional generic properties, just add new A523-specific compatible strings and fallback to the A100 one. Acked-by: Conor Dooley Link: https://patch.msgid.link/20251027125655.793277-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index 0f2501f72cca..c3e14eb6cfff 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -29,7 +29,10 @@ properties: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma - items: - - const: allwinner,sun50i-h616-dma + - enum: + - allwinner,sun50i-h616-dma + - allwinner,sun55i-a523-dma + - allwinner,sun55i-a523-mcu-dma - const: allwinner,sun50i-a100-dma reg: -- cgit v1.2.3 From 22e1d0d8cda783bee95de578cbda3ad0da8a3eb4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 17 Oct 2025 15:50:44 +0200 Subject: dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Add devicetree bindings for the AM67 based Kontron SMARC-sAM67 module. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251017135116.548236-2-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 0105dcda6e04..2e15029dbc67 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -194,6 +194,7 @@ properties: items: - enum: - beagle,am67a-beagley-ai + - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s -- cgit v1.2.3 From ccec1069246ad121c1cbb6494d75140d512a9b5b Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Wed, 11 Jun 2025 13:53:37 -0500 Subject: dt-bindings: arm: tegra: Document Jetson Nano Devkits Add compatibles for the Tegra210 Jetson Nano Developer Kits Signed-off-by: Aaron Kling Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 6139407c2cbf..50a31dba7bec 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -189,6 +189,11 @@ properties: - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2894-0050-a08 + - nvidia,p3450-0000 + - const: nvidia,tegra210 + - items: + - const: nvidia,p3541-0000 + - const: nvidia,p3450-0000 - const: nvidia,tegra210 - description: Jetson TX2 Developer Kit items: -- cgit v1.2.3 From 58676e819bf0ccf161e8684a7b8f641f0348ab57 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Fri, 31 Oct 2025 21:17:38 +0800 Subject: dt-bindings: intel: Add Agilex5 SoCFPGA 013b board Add compatible for Agilex5 SoCFPGA 013b board. Signed-off-by: Niravkumar L Rabara Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index c75cd7d29f1a..cf7a91dfec8a 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 -- cgit v1.2.3 From 6cf18454d7caf5a56776f6011ab9c6bca823c7e7 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 26 Aug 2025 16:08:47 +0200 Subject: dt-bindings: omap: add AM335x-based TQMa335x SOM and MBa335x board TQMa335x[L] is a SOM family using TI AM335x CPU family. MBa335x is an evaluation mainboard for this SOM. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250826140853.2570528-2-alexander.stein@ew.tq-group.com Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/ti/omap.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documentation/devicetree/bindings/arm/ti/omap.yaml index aa5df4692e37..14f1b9d8f59d 100644 --- a/Documentation/devicetree/bindings/arm/ti/omap.yaml +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -129,6 +129,13 @@ properties: - const: phytec,am335x-phycore-som - const: ti,am33xx + - description: TQ-Systems TQMa335x[L] SoM + items: + - enum: + - tq,tqma3359-mba335x # MBa335x carrier board + - const: tq,tqma3359 + - const: ti,am33xx + - description: TI OMAP4430 SoC based platforms items: - enum: -- cgit v1.2.3 From 333fa35fbd1f20b0d8a4af3b236fd9f52f3431b2 Mon Sep 17 00:00:00 2001 From: Charan Pedumuru Date: Fri, 24 Oct 2025 07:57:10 +0000 Subject: dt-bindings: mmc: ti,omap2430-sdhci: convert to DT schema Convert TI OMAP SDHCI Controller binding to YAML format. Changes during Conversion: - Define new properties like "clocks", "clock-names", "pbias-supply" and "power-domains" to resolve dtb_check errors. - Remove "pinctrl-names" and "pinctrl-" from required as they are not necessary for all DTS files. - Remove "ti,hwmods" property entirely from the YAML as the DTS doesn't contain this property for the given compatibles and the text binding is misleading. - Add "clocks", "clock-names" and "max-frequency" to the required properties based on the compatible and the text binding doesn't mention these properties as required. - Add missing strings like "default-rev11", "sdr12-rev11", "sdr25-rev11", "hs-rev11", "sdr25-rev11" and "sleep" to pinctrl-names string array to resolve errors detected by dtb_check. Signed-off-by: Charan Pedumuru Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251024-ti-sdhci-omap-v5-3-df5f6f033a38@gmail.com Signed-off-by: Kevin Hilman --- .../devicetree/bindings/mmc/sdhci-omap.txt | 43 ------ .../devicetree/bindings/mmc/ti,omap2430-sdhci.yaml | 169 +++++++++++++++++++++ 2 files changed, 169 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-omap.txt create mode 100644 Documentation/devicetree/bindings/mmc/ti,omap2430-sdhci.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt deleted file mode 100644 index f91e341e6b36..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt +++ /dev/null @@ -1,43 +0,0 @@ -* TI OMAP SDHCI Controller - -Refer to mmc.txt for standard MMC bindings. - -For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning. - -Required properties: -- compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers - Should be "ti,omap3-sdhci" for omap3 controllers - Should be "ti,omap4-sdhci" for omap4 and ti81 controllers - Should be "ti,omap5-sdhci" for omap5 controllers - Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers - Should be "ti,k2g-sdhci" for K2G - Should be "ti,am335-sdhci" for am335x controllers - Should be "ti,am437-sdhci" for am437x controllers -- ti,hwmods: Must be "mmc", is controller instance starting 1 - (Not required for K2G). -- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50", - "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104", - "ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11", - "hs200_1_8v", -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format as described - in the generic DMA client binding. A tx and rx specifier is required. -- dma-names: List of DMA request names. These strings correspond 1:1 with the - DMA specifiers listed in dmas. The string naming is to be "tx" - and "rx" for TX and RX DMA requests, respectively. - -Deprecated properties: -- ti,non-removable: Compatible with the generic non-removable property - -Example: - mmc1: mmc@4809c000 { - compatible = "ti,dra7-sdhci"; - reg = <0x4809c000 0x400>; - ti,hwmods = "mmc1"; - bus-width = <4>; - vmmc-supply = <&vmmc>; /* phandle to regulator node */ - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/mmc/ti,omap2430-sdhci.yaml b/Documentation/devicetree/bindings/mmc/ti,omap2430-sdhci.yaml new file mode 100644 index 000000000000..34e288f3ef13 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/ti,omap2430-sdhci.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/ti,omap2430-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP SDHCI Controller + +maintainers: + - Kishon Vijay Abraham I + +description: + For UHS devices which require tuning, the device tree should have a + cpu_thermal node which maps to the appropriate thermal zone. This + is used to get the temperature of the zone during tuning. + +properties: + compatible: + enum: + - ti,omap2430-sdhci + - ti,omap3-sdhci + - ti,omap4-sdhci + - ti,omap5-sdhci + - ti,dra7-sdhci + - ti,k2g-sdhci + - ti,am335-sdhci + - ti,am437-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: fck + - const: mmchsdb_fck + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + pinctrl-names: + minItems: 1 + maxItems: 14 + items: + enum: + - default + - default-rev11 + - hs + - sdr12 + - sdr12-rev11 + - sdr25 + - sdr25-rev11 + - sdr50 + - ddr50-rev11 + - sdr104-rev11 + - ddr50 + - sdr104 + - ddr_1_8v-rev11 + - ddr_1_8v + - ddr_3_3v + - hs-rev11 + - hs200_1_8v-rev11 + - hs200_1_8v + - sleep + + pinctrl-0: + maxItems: 1 + + pinctrl-1: + maxItems: 1 + + pinctrl-2: + maxItems: 1 + + pinctrl-3: + maxItems: 1 + + pinctrl-4: + maxItems: 1 + + pinctrl-5: + maxItems: 1 + + pinctrl-6: + maxItems: 1 + + pinctrl-7: + maxItems: 1 + + pinctrl-8: + maxItems: 1 + + power-domains: + maxItems: 1 + + pbias-supply: + description: + It is used to specify the voltage regulator that provides the bias + voltage for certain analog or I/O pads. + + ti,non-removable: + description: + It indicates that a component is not meant to be easily removed or + replaced by the user, such as an embedded battery or a non-removable + storage slot like eMMC. + type: boolean + deprecated: true + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + It represents the speed at which a clock signal associated with a device + or bus operates, measured in Hertz (Hz). This value is crucial for configuring + hardware components that require a specific clock speed. + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: sdhci-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,dra7-sdhci + - ti,k2g-sdhci + then: + required: + - max-frequency + - if: + properties: + compatible: + contains: + const: ti,k2g-sdhci + then: + required: + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + mmc@4809c000 { + compatible = "ti,dra7-sdhci"; + reg = <0x4809c000 0x400>; + interrupts = ; + max-frequency = <192000000>; + sdhci-caps-mask = <0x0 0x400000>; + bus-width = <4>; + vmmc-supply = <&vmmc>; /* phandle to regulator node */ + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + }; +... -- cgit v1.2.3 From b88827cb0bd1a192855db40494970bbdd7aad939 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Mon, 27 Oct 2025 14:28:12 +0100 Subject: dt-bindings: arm: mediatek: add BPI-R4 Pro board Add compatibles for Bananapi R4 Pro boards. Signed-off-by: Frank Wunderlich Reviewed-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 2c5c92b87b3a..391b385c91dc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -113,6 +113,12 @@ properties: - const: bananapi,bpi-r4-2g5 - const: bananapi,bpi-r4 - const: mediatek,mt7988a + - items: + - enum: + - bananapi,bpi-r4-pro-4e + - bananapi,bpi-r4-pro-8x + - const: bananapi,bpi-r4-pro + - const: mediatek,mt7988a - items: - enum: - mediatek,mt8127-moose -- cgit v1.2.3 From 2cc22890635ded33856e2761b780688f54a49393 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 23 Oct 2025 15:28:29 +0800 Subject: dt-bindings: riscv: spacemit: add MusePi Pro board Document the compatible string for the MusePi Pro [1]. It is a 1.8-inch single board computer based on the SpacemiT K1/M1 RISC-V SoC [2]. Here's a refined list of its core features: - SoC: SpacemiT M1/K1, 8-core 64-bit RISC-V. - Memory: LPDDR4X @ 2400MT/s, available in 8GB & 16GB options. - Storage: Onboard eMMC 5.1 (64GB/128GB options), M.2 M-Key for NVMe SSD (2230 size), and a microSD slot (UHS-II) for expansion. - Display: HDMI 1.4 (1080P@60Hz) and 2-lane MIPI DSI FPC (1080P@60Hz). - Connectivity: Onboard Wi-Fi 6 & Bluetooth 5.2, single Gigabit Ethernet port (RJ45). - USB: 4x USB 3.0 Type-A (host) and 1x USB 2.0 Type-C (device/OTG). - Expansion: Full-size miniPCIe slot and a second M.2 M-Key (2230). - GPIO: Standard 40-pin GPIO interface. - MIPI: 1x 4-lane MIPI CSI FPC and 2x MIPI DSI FPC interfaces. - Clock: Onboard RTC with battery support. Link: https://developer.spacemit.com/documentation?token=YJtdwnvvViPVcmkoPDpcvwfVnrh&type=pdf [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Acked-by: Conor Dooley Signed-off-by: Troy Mitchell Link: https://lore.kernel.org/r/20251023-k1-musepi-pro-dts-v4-1-01836303e10f@linux.spacemit.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index c56b62a6299a..52fe39296031 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -22,6 +22,7 @@ properties: - enum: - bananapi,bpi-f3 - milkv,jupiter + - spacemit,musepi-pro - xunlong,orangepi-rv2 - const: spacemit,k1 -- cgit v1.2.3 From 25802f8d16374bcfc1e32d26fdee0d89ec82f865 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Tue, 4 Nov 2025 01:17:00 +0800 Subject: dt-bindings: vendor-prefixes: Add 9Tripod Add 9Tripod to the vendor prefixes. Signed-off-by: Coia Prant Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251103171702.1518730-2-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 003cc91fb02f..7fd091e87007 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -30,6 +30,8 @@ patternProperties: description: 70mai Co., Ltd. "^8dev,.*": description: 8devices, UAB + "^9tripod,.*": + description: Shenzhen 9Tripod Innovation and Development CO., LTD. "^abb,.*": description: ABB "^abilis,.*": -- cgit v1.2.3 From a12838aab0cea1e4427d8d620906ce6a1a83a344 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Tue, 4 Nov 2025 01:17:01 +0800 Subject: dt-bindings: arm: rockchip: Add 9Tripod X3568 series This documents 9Tripod X3568 v4 which is a SBC based on RK3568 SoC. Link: http://www.9tripod.com/showpro.php?id=117 Link: https://appletsapi.52solution.com/media/X3568V4%E5%BC%80%E5%8F%91%E6%9D%BF%E7%A1%AC%E4%BB%B6%E6%89%8B%E5%86%8C.pdf Signed-off-by: Coia Prant Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251103171702.1518730-3-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ba61ea743613..9f68ec6a7a37 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -30,6 +30,12 @@ properties: - const: vamrs,rock960 - const: rockchip,rk3399 + - description: 9Tripod X3568 series board + items: + - enum: + - 9tripod,x3568-v4 + - const: rockchip,rk3568 + - description: Amarula Vyasa RK3288 items: - const: amarula,vyasa-rk3288 -- cgit v1.2.3 From dd94481408ba0e3b68c42d3ee986d83215a9fac9 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Fri, 7 Nov 2025 07:35:25 +0800 Subject: dt-bindings: firmware: svc: Add IOMMU support for Agilex5 In Agilex5, the TBU (Translation Buffer Unit) can now operate in non-secure mode, enabling Linux to utilize it through the IOMMU framework. This allows improved memory management capabilities in non-secure environments. With Agilex5 lifting this restriction, we are now extending the device tree bindings to support IOMMU for the Agilex5 SVC. Signed-off-by: Khairul Anuar Romli Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml index fac1e955852e..b42cfa78b28b 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -34,6 +34,7 @@ properties: enum: - intel,stratix10-svc - intel,agilex-svc + - intel,agilex5-svc method: description: | @@ -54,6 +55,9 @@ properties: reserved memory region for the service layer driver to communicate with the secure device manager. + iommus: + maxItems: 1 + fpga-mgr: $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml description: Optional child node for fpga manager to perform fabric configuration. @@ -63,6 +67,17 @@ required: - method - memory-region +allOf: + - if: + properties: + compatible: + contains: + enum: + - intel,agilex5-svc + then: + required: + - iommus + additionalProperties: false examples: -- cgit v1.2.3 From 323256d11e01d5ee2a0a2e7b682890498b90b212 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 12 Nov 2025 04:44:40 +0000 Subject: dt-bindings: riscv: spacemit: Add OrangePi R2S board Document the compatible string for the OrangePi R2S board [1], which is marketed as using the Ky X1 SoC but is in fact identical in die and package to the SpacemiT K1 SoC [2]. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-R2S.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Signed-off-by: Michael Opdenacker Acked-by: Krzysztof Kozlowski Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20251112044426.2351999-2-michael.opdenacker@rootcommit.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 52fe39296031..9c49482002f7 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -23,6 +23,7 @@ properties: - bananapi,bpi-f3 - milkv,jupiter - spacemit,musepi-pro + - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 -- cgit v1.2.3 From 2f6ef830a756f58312b3f3bbe3c1edb739e84ec5 Mon Sep 17 00:00:00 2001 From: João Paulo Gonçalves Date: Tue, 11 Nov 2025 18:54:57 +0100 Subject: dt-bindings: arm: ti: add Toradex Aquila AM69 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DT compatible strings for the Toradex Aquila AM69 SoM and its supported carrier boards: the Aquila Development Board and the Clover carrier board. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Link: https://www.toradex.com/products/carrier-board/clover Signed-off-by: João Paulo Gonçalves Signed-off-by: Francesco Dolcini Acked-by: Conor Dooley Link: https://patch.msgid.link/20251111175502.8847-2-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 2e15029dbc67..c6eb72462bef 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -158,6 +158,14 @@ properties: - ti,am654-evm - const: ti,am654 + - description: K3 AM69 SoC Toradex Aquila Modules and Carrier Boards + items: + - enum: + - toradex,aquila-am69-clover # Aquila AM69 Module on Clover Board + - toradex,aquila-am69-dev # Aquila AM69 Module on Aquila Development Board + - const: toradex,aquila-am69 # Aquila AM69 Module + - const: ti,j784s4 + - description: K3 J7200 SoC oneOf: - const: ti,j7200 -- cgit v1.2.3 From b70d9d7dac873a3a101a1063db2bc97fa2dc29fa Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Nov 2025 09:46:42 -0600 Subject: dt-bindings: arm: ti: Add binding for AM62L SoCs Add the binding for TI's AM62L family of devices. Reviewed-by: Dhruva Gole Acked-by: Krzysztof Kozlowski Signed-off-by: Bryan Brattlof Link: https://patch.msgid.link/20251105-am62lx-v8-1-496f353e8237@ti.com Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index c6eb72462bef..85deda6d4292 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -37,6 +37,12 @@ properties: - const: phytec,am62a-phycore-som - const: ti,am62a7 + - description: K3 AM62L3 SoC and Boards + items: + - enum: + - ti,am62l3-evm + - const: ti,am62l3 + - description: K3 AM62P5 SoC and Boards items: - enum: -- cgit v1.2.3 From 425c16c37da25b6a7e8b9dd8bb1bce21562ff83f Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Fri, 14 Nov 2025 08:59:52 +0800 Subject: dt-bindings: intel: Add Agilex3 SoCFPGA board Add compatible string for Agilex3 SoCFPGA board, which shares the same architecture as Agilex5 but with two fewer CPU cores. Signed-off-by: Niravkumar L Rabara Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index cf7a91dfec8a..c918837bd41c 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -21,6 +21,12 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 - description: Agilex5 boards items: - enum: -- cgit v1.2.3 From a0c70244e5a877be917fc6aaf1e58a4debd99c4d Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 16 Oct 2025 10:41:49 +0300 Subject: dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+ The current EPP, ISP and MPE schemas are largely compatible with Tegra114+, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra114-tsec.yaml | 68 ++++++++++++++++++++++ .../bindings/display/tegra/nvidia,tegra20-epp.yaml | 14 +++-- .../bindings/display/tegra/nvidia,tegra20-isp.yaml | 15 +++-- .../bindings/display/tegra/nvidia,tegra20-mpe.yaml | 18 ++++-- 4 files changed, 102 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml new file mode 100644 index 000000000000..2c4d519a1bb7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel + - Thierry Reding + +description: Tegra Security co-processor, an embedded security processor used + mainly to manage the HDCP encryption and keys on the HDMI link. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra114-tsec + - nvidia,tegra124-tsec + - nvidia,tegra210-tsec + + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +examples: + - | + #include + #include + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml index 3c095a5491fe..334f5531b243 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -15,10 +15,16 @@ properties: pattern: "^epp@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + - nvidia,tegra124-epp + + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml index 3bc3b22e98e1..ee25b5e6f1a2 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -12,10 +12,17 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra114-isp + - nvidia,tegra124-isp + - nvidia,tegra210-isp + + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml index 2cd3e60cd0a8..36b76fa8f525 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -12,13 +12,21 @@ maintainers: properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-msenc + - nvidia,tegra124-msenc + + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc reg: maxItems: 1 -- cgit v1.2.3 From e7dc9c3a6fc46e2530119b7c1d174fa9af2b6acb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:49:28 +0300 Subject: dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI Document CSI HW block found in Tegra20 and Tegra30 SoC. The #nvidia,mipi-calibrate-cells is not an introduction of property, such property already exists in nvidia,tegra114-mipi.yaml and is used in multiple device trees. In case of Tegra30 and Tegra20 CSI block combines mipi calibration function and CSI function, in Tegra114+ mipi calibration got a dedicated hardware block which is already supported. This property here is used to align with mipi-calibration logic used by Tegra114+. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-csi.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml new file mode 100644 index 000000000000..a1aea9590769 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 CSI controller + +maintainers: + - Svyatoslav Ryhel + +properties: + compatible: + enum: + - nvidia,tegra20-csi + - nvidia,tegra30-csi + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia-pad + - const: csib-pad + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: + The number of cells in a MIPI calibration specifier. Should be 1. + The single cell specifies an id of the pad that need to be + calibrated for a given device. Valid pad ids for receiver would be + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: channel 0 represents CSI-A and 1 represents CSI-B + additionalProperties: false + + properties: + reg: + maximum: 1 + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pad is used by this CSI channel and needs to be calibrated. + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: port receiving the video stream from the sensor + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: port sending the video stream to the VI + + required: + - reg + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-csi + then: + properties: + clocks: + maxItems: 1 + + clock-names: false + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-csi + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - power-domains + - "#address-cells" + - "#size-cells" + +# see nvidia,tegra20-vi.yaml for an example -- cgit v1.2.3 From 22c788aec2efc80d6c8f4e8fa00c5a4fb10f8956 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 21 Oct 2025 22:09:26 -0500 Subject: dt-bindings: devfreq: tegra30-actmon: Add Tegra124 fallback for Tegra210 The Tegra210 actmon is compatible with the existing Tegra124 driver. Describe the compatibles as such. Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- .../devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml index e3379d106728..ea1dc86bc31f 100644 --- a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml +++ b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml @@ -19,11 +19,14 @@ description: | properties: compatible: - enum: - - nvidia,tegra30-actmon - - nvidia,tegra114-actmon - - nvidia,tegra124-actmon - - nvidia,tegra210-actmon + oneOf: + - enum: + - nvidia,tegra30-actmon + - nvidia,tegra114-actmon + - nvidia,tegra124-actmon + - items: + - const: nvidia,tegra210-actmon + - const: nvidia,tegra124-actmon reg: maxItems: 1 -- cgit v1.2.3 From 905f0dcc38f8078f0641c5cf855f420d78f10ea7 Mon Sep 17 00:00:00 2001 From: Haotien Hsu Date: Mon, 11 Aug 2025 15:45:55 +0800 Subject: dt-bindings: usb: Add wake-up support for Tegra234 XUSB host controller Populate USB wake events for Tegra234 XUSB host controller. These wake-up events are optional to maintain backward compatibility and because the USB controller does not require them for normal operation. Signed-off-by: Haotien Hsu Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../bindings/usb/nvidia,tegra234-xusb.yaml | 31 ++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml index db761dcbf72a..ec0993497fbb 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml @@ -32,9 +32,35 @@ properties: - const: bar2 interrupts: + minItems: 2 items: - description: xHCI host interrupt - description: mailbox interrupt + - description: USB wake event 0 + - description: USB wake event 1 + - description: USB wake event 2 + - description: USB wake event 3 + - description: USB wake event 4 + - description: USB wake event 5 + - description: USB wake event 6 + description: | + The first two interrupts are required for the USB host controller. The + remaining USB wake event interrupts are optional. Each USB wake event is + independent; it is not necessary to use all of these events on a + platform. The USB host controller can function even if no wake-up events + are defined. The USB wake event interrupts are handled by the Tegra PMC; + hence, the interrupt controller for these is the PMC and the interrupt + IDs correspond to the PMC wake event IDs. A complete list of wake event + IDs is provided below, and this information is also present in the Tegra + TRM document. + + PMC wake-up 76 for USB3 port 0 wakeup + PMC wake-up 77 for USB3 port 1 wakeup + PMC wake-up 78 for USB3 port 2 and port 3 wakeup + PMC wake-up 79 for USB2 port 0 wakeup + PMC wake-up 80 for USB2 port 1 wakeup + PMC wake-up 81 for USB2 port 2 wakeup + PMC wake-up 82 for USB2 port 3 wakeup clocks: items: @@ -127,8 +153,9 @@ examples: <0x03650000 0x10000>; reg-names = "hcd", "fpci", "bar2"; - interrupts = , - ; + interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>, -- cgit v1.2.3 From 21906e6f52b25340dc4c5de48a878c9ea7c13b72 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 28 Oct 2025 05:32:43 +0100 Subject: dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Add device-tree bindings for PHYTEC phyBOARD-Segin-i.MX91 board based on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module). Signed-off-by: Primoz Fiser Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 21b7168d61f5..29f586d18504 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1495,6 +1495,13 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX91 SoM based boards + items: + - enum: + - phytec,imx91-phyboard-segin # phyBOARD-Segin with i.MX91 + - const: phytec,imx91-phycore-som # phyCORE-i.MX91 SoM + - const: fsl,imx91 + - description: PHYTEC phyCORE-i.MX93 SoM based boards items: - enum: -- cgit v1.2.3 From 88f717c042bba8189dc0a11e5ac1ea7215bc69ce Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Fri, 7 Nov 2025 15:49:51 +0100 Subject: dt-bindings: arm: fsl: add Skov Rev.C HDMI support From software perspective, Rev.C HDMI and Rev.B HDMI don't differ since the panel is connected via HDMI and the touchscreen is connected via USB. However, the bootloader firmware expects to find a dts with the correct revc-hdmi compatible. Signed-off-by: Marco Felsch Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 29f586d18504..34ae86d370f6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1111,6 +1111,7 @@ properties: - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel + - skov,imx8mp-skov-revc-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate - skov,imx8mp-skov-revc-jutouch-jt101tm023 # SKOV i.MX8MP climate control with 10" JuTouch panel - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel -- cgit v1.2.3 From 565c450124c105a0b4f4ff3265e19502d44bf23b Mon Sep 17 00:00:00 2001 From: Longbin Li Date: Sat, 1 Nov 2025 09:43:21 +0800 Subject: dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC The Sophgo CV18XX/SG200X SoC top misc system controller provides register access to configure related modules. It includes a usb2 phy and a dma multiplexer. Co-developed-by: Inochi Amaoto Signed-off-by: Longbin Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20251101014329.18439-2-looong.bin@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../soc/sophgo/sophgo,cv1800b-top-syscon.yaml | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml new file mode 100644 index 000000000000..b2e8e0cb4ea6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,cv1800b-top-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV18XX/SG200X SoC top system controller + +maintainers: + - Inochi Amaoto + +description: + The Sophgo CV18XX/SG200X SoC top misc system controller provides + register access to configure related modules. + +properties: + compatible: + oneOf: + - items: + - const: sophgo,cv1800b-top-syscon + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + dma-router@154: + $ref: /schemas/dma/sophgo,cv1800b-dmamux.yaml# + unevaluatedProperties: false + + phy@48: + $ref: /schemas/phy/sophgo,cv1800b-usb2-phy.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + syscon@3000000 { + compatible = "sophgo,cv1800b-top-syscon", "syscon", "simple-mfd"; + reg = <0x03000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + phy@48 { + compatible = "sophgo,cv1800b-usb2-phy"; + reg = <0x48 0x4>; + #phy-cells = <0>; + clocks = <&clk CLK_USB_125M>, + <&clk CLK_USB_33K>, + <&clk CLK_USB_12M>; + clock-names = "app", "stb", "lpm"; + resets = <&rst 58>; + }; + + dma-router@154 { + compatible = "sophgo,cv1800b-dmamux"; + reg = <0x154 0x8>, <0x298 0x4>; + #dma-cells = <2>; + dma-masters = <&dmac>; + }; + }; + +... -- cgit v1.2.3 From 5ffac985b5f4272c8fccb0ef58369724bd10cd8d Mon Sep 17 00:00:00 2001 From: João Paulo Gonçalves Date: Tue, 11 Nov 2025 16:16:13 +0100 Subject: dt-bindings: arm: fsl: add Toradex SMARC iMX95 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DT compatible strings for Toradex SMARC iMX95 SoM and Toradex SMARC Development carrier board. Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit Signed-off-by: João Paulo Gonçalves Signed-off-by: Francesco Dolcini Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 34ae86d370f6..68a2d5fecc43 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1443,6 +1443,12 @@ properties: - const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC - const: fsl,imx95 + - description: Toradex Boards with SMARC iMX95 Modules + items: + - const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board + - const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: -- cgit v1.2.3 From a576b51e13870ba957e13e6cc265431260a32a77 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 12 Nov 2025 22:42:05 +0100 Subject: dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices QNAP builds a number of variants of the RK3568-based NAS design. Add the 2-bay TS233 variant. Acked-by: Conor Dooley Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20251112214206.423244-5-heiko@sntech.de --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 9f68ec6a7a37..04171fdae799 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -889,9 +889,11 @@ properties: - const: prt,mecsbc - const: rockchip,rk3568 - - description: QNAP TS-433-4G 4-Bay NAS + - description: QNAP TS-x33 NAS devices items: - - const: qnap,ts433 + - enum: + - qnap,ts233 + - qnap,ts433 - const: rockchip,rk3568 - description: Radxa Compute Module 3 (CM3) -- cgit v1.2.3 From 605945281a65ca68af00f3d7592a191b20b21ad4 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 19 Nov 2025 09:22:38 +0000 Subject: dt-bindings: arm: rockchip: merge Asus Tinker and Tinker S Merge sections for Asus Tinker Board and Asus Tinker Board S. Asus Tinker Board S (Storage) is just a variant of Tinker Board with an added eMMC chip. Signed-off-by: Michael Opdenacker Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251119-merge-tinker-bindings-v1-1-4072b55750c1@rootcommit.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 04171fdae799..660b89e2fc11 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -89,12 +89,9 @@ properties: - description: Asus Tinker board items: - - const: asus,rk3288-tinker - - const: rockchip,rk3288 - - - description: Asus Tinker board S - items: - - const: asus,rk3288-tinker-s + - enum: + - asus,rk3288-tinker + - asus,rk3288-tinker-s - const: rockchip,rk3288 - description: Beelink A1 -- cgit v1.2.3 From f4e81d0b95f3257a2fcfdbfaa2d8ed41015c621b Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Tue, 18 Nov 2025 15:56:42 +0000 Subject: dt-bindings: arm: rockchip: Add Asus Tinker Board 3/3S Document the compatible strings for Asus Tinker Board 3 [1] and 3S [2], which are SBCs based on the Rockchip 3566 SoC. The "3S" version ("S" for "storage") just adds a 16 GB eMMC and a "mask ROM" DIP switch to the "3" version. [1] https://tinker-board.asus.com/series/tinker-board-3.html [2] https://tinker-board.asus.com/series/tinker-board-3s.html Signed-off-by: Michael Opdenacker Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251118-tinker3-v3-1-2903693f2ebb@rootcommit.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 660b89e2fc11..d496421dbd87 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -94,6 +94,13 @@ properties: - asus,rk3288-tinker-s - const: rockchip,rk3288 + - description: Asus Tinker Board 3/3S + items: + - enum: + - asus,rk3566-tinker-board-3 + - asus,rk3566-tinker-board-3s + - const: rockchip,rk3566 + - description: Beelink A1 items: - const: azw,beelink-a1 -- cgit v1.2.3 From 7a1e15b248d69a5399c41e65731573d63b12f345 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Tue, 25 Nov 2025 15:56:00 +0800 Subject: dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Add device tree bindings for the StarFive JH7110S SoC and the VisionFive 2 Lite board equipped with it. JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade and up to 1.25GHz. Its CPU cores and peripherals are the same as those of the JH7110 SoC. VisionFive 2 Lite boards have MicroSD card version (default) and eMMC version, which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC" respectively. Acked-by: Rob Herring (Arm) Tested-by: Matthias Brugger Reviewed-by: Heinrich Schuchardt Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 04510341a71e..797d9956b949 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -35,6 +35,12 @@ properties: - starfive,visionfive-2-v1.3b - const: starfive,jh7110 + - items: + - enum: + - starfive,visionfive-2-lite + - starfive,visionfive-2-lite-emmc + - const: starfive,jh7110s + additionalProperties: true ... -- cgit v1.2.3 From d94ebab404b0ce6498770888e25102e32b2b13da Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 23 Nov 2025 14:50:44 -0800 Subject: dt-bindings: riscv: starfive: add xunlong,orangepi-rv Add "xunlong,orangepi-rv" as a StarFive JH7110 SoC-based board. Signed-off-by: Icenowy Zheng Signed-off-by: E Shattow Acked-by: Conor Dooley Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 797d9956b949..9253aab21518 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -33,6 +33,7 @@ properties: - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b + - xunlong,orangepi-rv - const: starfive,jh7110 - items: -- cgit v1.2.3 From ea1156e840324d80fac8829af72d78e2eeb8b020 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 27 Sep 2025 12:50:05 +0000 Subject: dt-bindings: arm: amlogic: add support for Tanix TX9 Pro The Oranth Tanix TX9 Pro is an Android STB using the Amlogic S912 chip Signed-off-by: Christian Hewitt Reviewed-by: Martin Blumenstingl Acked-by: Conor Dooley Link: https://patch.msgid.link/20250927125006.824293-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 2a096e060ed3..08d9963fe925 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -134,6 +134,7 @@ properties: - libretech,aml-s912-pc - minix,neo-u9h - nexbox,a1 + - oranth,tx9-pro - tronsmart,vega-s96 - ugoos,am3 - videostrong,gxm-kiii-pro -- cgit v1.2.3