From 85220be437fa0cf8515a172848ca71fc298dfde7 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Mon, 22 Jun 2026 06:54:09 +0000 Subject: dt-bindings: iommu: Fix interrupt type in example The CMDQV interrupt on Tegra264 is edge-triggered per the hardware interrupt documentation, but the binding example describes it as level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so that it does not propagate the wrong trigger type. Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support") Reported-by: Nicolin Chen Signed-off-by: Ashish Mhetre Acked-by: Jon Hunter Acked-by: Nicolin Chen Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = ; + interrupts = ; }; -- cgit v1.2.3 From d28b49f11f8cbb7d76382998c84c18f465b347a4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 1 Jul 2026 18:06:55 +0200 Subject: dt-bindings: gpu: host1x: Fix email address These bindings had mixed up local and domain parts, the combination of which doesn't exist. Fix them up. Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml | 2 +- Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml | 2 +- Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml | 2 +- Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml index ba4c6473ff92..84a84275432a 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml index c23dae713eb8..8916a868dafb 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml index 99a33a5eac3f..582eb44eb157 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -12,7 +12,7 @@ description: | through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml index 0b7561c8b9bb..4eb325cfd296 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: -- cgit v1.2.3