From ebb37bd06460fff8d6f54f7731f593b7b52143ca Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 15 Aug 2019 13:06:12 +0300 Subject: dt-bindings: interconnect: Add Qualcomm MSM8916 DT bindings The Qualcomm MSM8916 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Reviewed-by: Rob Herring Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,msm8916.yaml | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml new file mode 100644 index 000000000000..4107e60cab12 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8916 Network-On-Chip interconnect + +maintainers: + - Georgi Djakov + +description: | + The Qualcomm MSM8916 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,msm8916-bimc + - qcom,msm8916-pcnoc + - qcom,msm8916-snoc + + reg: + maxItems: 1 + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + +required: + - compatible + - reg + - '#interconnect-cells' + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include + + bimc: interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8916-pcnoc"; + reg = <0x00500000 0x11000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + reg = <0x00580000 0x14000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; -- cgit v1.2.3 From bbd8e6672f05af28032312a1a2ed260040c17fbf Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 13 Jan 2020 13:21:52 +0000 Subject: dt-bindings: soundwire: add bindings for Qcom controller This patch adds bindings for Qualcomm soundwire controller. Qualcomm SoundWire Master controller is present in most Qualcomm SoCs either integrated as part of WCD audio codecs via slimbus or as part of SOC I/O. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200113132153.27239-2-srinivas.kandagatla@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/soundwire/qcom,sdw.txt | 167 +++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/soundwire/qcom,sdw.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt new file mode 100644 index 000000000000..436547f3b155 --- /dev/null +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -0,0 +1,167 @@ +Qualcomm SoundWire Controller Bindings + + +This binding describes the Qualcomm SoundWire Controller along with its +board specific bus parameters. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,soundwire-v..", + Example: + "qcom,soundwire-v1.3.0" + "qcom,soundwire-v1.5.0" + "qcom,soundwire-v1.6.0" +- reg: + Usage: required + Value type: + Definition: the base address and size of SoundWire controller + address space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the SoundWire Controller IRQ + +- clock-names: + Usage: required + Value type: + Definition: should be "iface" for SoundWire Controller interface clock + +- clocks: + Usage: required + Value type: + Definition: should specify the SoundWire Controller interface clock + +- #sound-dai-cells: + Usage: required + Value type: + Definition: must be 1 for digital audio interfaces on the controller. + +- qcom,dout-ports: + Usage: required + Value type: + Definition: must be count of data out ports + +- qcom,din-ports: + Usage: required + Value type: + Definition: must be count of data in ports + +- qcom,ports-offset1: + Usage: required + Value type: + Definition: should specify payload transport window offset1 of each + data port. Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-offset2: + Usage: required + Value type: + Definition: should specify payload transport window offset2 of each + data port. Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-sinterval-low: + Usage: required + Value type: + Definition: should be sample interval low of each data port. + Out ports followed by In ports. Used for Sample Interval + calculation. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-word-length: + Usage: optional + Value type: + Definition: should be size of payload channel sample. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-block-pack-mode: + Usage: optional + Value type: + Definition: should be 0 or 1 to indicate the block packing mode. + 0 to indicate Blocks are per Channel + 1 to indicate Blocks are per Port. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-block-group-count: + Usage: optional + Value type: + Definition: should be in range 1 to 4 to indicate how many sample + intervals are combined into a payload. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-lane-control: + Usage: optional + Value type: + Definition: should be in range 0 to 7 to identify which data lane + the data port uses. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-hstart: + Usage: optional + Value type: + Definition: should be number identifying lowerst numbered coloum in + SoundWire Frame, i.e. left edge of the Transport sub-frame + for each port. Values between 0 and 15 are valid. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,ports-hstop: + Usage: optional + Value type: + Definition: should be number identifying highest numbered coloum in + SoundWire Frame, i.e. the right edge of the Transport + sub-frame for each port. Values between 0 and 15 are valid. + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +- qcom,dports-type: + Usage: optional + Value type: + Definition: should be one of the following types + 0 for reduced port + 1 for simple ports + 2 for full port + Out ports followed by In ports. + More info in MIPI Alliance SoundWire 1.0 Specifications. + +Note: + More Information on detail of encoding of these fields can be +found in MIPI Alliance SoundWire 1.0 Specifications. + += SoundWire devices +Each subnode of the bus represents SoundWire device attached to it. +The properties of these nodes are defined by the individual bindings. + += EXAMPLE +The following example represents a SoundWire controller on DB845c board +which has controller integrated inside WCD934x codec on SDM845 SoC. + +soundwire: soundwire@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x20>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + clocks = <&wcc>; + clock-names = "iface"; + #sound-dai-cells = <1>; + qcom,dports-type = <0>; + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; + + /* Left Speaker */ + left{ + .... + }; + + /* Right Speaker */ + right{ + .... + }; +}; -- cgit v1.2.3 From 884a90bdf42bf15b1d07b88b72d93c955eb19ad9 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 9 Jan 2020 10:31:45 +0000 Subject: dt-bindings: SLIMBus: add slim devices optional properties This patch adds an optional SLIMBus Interface device phandle property that could be used by some of the SLIMBus devices. Interface device is mostly used with devices that are dealing with streaming. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200109103148.5612-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/slimbus/bus.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/slimbus/bus.txt b/Documentation/devicetree/bindings/slimbus/bus.txt index 52fa6426388c..bbe871f82a8b 100644 --- a/Documentation/devicetree/bindings/slimbus/bus.txt +++ b/Documentation/devicetree/bindings/slimbus/bus.txt @@ -32,6 +32,10 @@ Required property for SLIMbus child node if it is present: Product Code, shall be in lower case hexadecimal with leading zeroes suppressed +Optional property for SLIMbus child node if it is present: +- slim-ifc-dev - Should be phandle to SLIMBus Interface device. + Required for devices which deal with streams. + SLIMbus example for Qualcomm's slimbus manager component: slim@28080000 { @@ -43,8 +47,14 @@ SLIMbus example for Qualcomm's slimbus manager component: #address-cells = <2>; #size-cell = <0>; + codec_ifd: ifd@0,0{ + compatible = "slim217,60"; + reg = <0 0>; + }; + codec: wcd9310@1,0{ compatible = "slim217,60"; reg = <1 0>; + slim-ifc-dev = <&codec_ifd>; }; }; -- cgit v1.2.3 From 5098cae1f79cc0580dc2741ce250307a60451eca Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 14 Jan 2020 09:48:06 +0000 Subject: dt-bindings: soundwire: fix example As wsa881x schema mentions #sound-dai-cells as required property, so update soundwire-controller.yaml example so that dt_bindings_check does not fail as below: Documentation/devicetree/bindings/soundwire/soundwire-controller.example.dt.yaml: speaker@0,1: '#sound-dai-cells' is a required property Documentation/devicetree/bindings/soundwire/soundwire-controller.example.dt.yaml: speaker@0,2: '#sound-dai-cells' is a required property Reported-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20200114094806.15846-1-srinivas.kandagatla@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml b/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml index 1b43993bccdb..330924b8618e 100644 --- a/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml +++ b/Documentation/devicetree/bindings/soundwire/soundwire-controller.yaml @@ -69,6 +69,7 @@ examples: reg = <0 1>; powerdown-gpios = <&wcdpinctrl 2 0>; #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; }; speaker@0,2 { @@ -76,6 +77,7 @@ examples: reg = <0 2>; powerdown-gpios = <&wcdpinctrl 2 0>; #thermal-sensor-cells = <0>; + #sound-dai-cells = <0>; }; }; -- cgit v1.2.3 From 4ad3ad18990d6f6ceabce04ca830cd2607473b84 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 16 Jan 2020 16:10:58 +0000 Subject: dt-bindings: imx-ocotp: Add i.MX8MP compatible Add compatible and description for i.MX8MP. Signed-off-by: Anson Huang Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20200116161100.30637-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index 904dadf3d07b..6e346d5cddcf 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -2,7 +2,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings This binding represents the on-chip eFuse OTP controller found on i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, -i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM and i.MX8MN SoCs. +i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. Required properties: - compatible: should be one of @@ -17,6 +17,7 @@ Required properties: "fsl,imx8mq-ocotp" (i.MX8MQ), "fsl,imx8mm-ocotp" (i.MX8MM), "fsl,imx8mn-ocotp" (i.MX8MN), + "fsl,imx8mp-ocotp" (i.MX8MP), followed by "syscon". - #address-cells : Should be 1 - #size-cells : Should be 1 -- cgit v1.2.3 From 9664a6b54c57c920e345a621f42d1eb006a7fb73 Mon Sep 17 00:00:00 2001 From: Shyam Kumar Thella Date: Thu, 16 Jan 2020 16:10:59 +0000 Subject: dt-bindings: nvmem: add binding for QTI SPMI SDAM QTI SDAM allows PMIC peripherals to access the shared memory that is available on QTI PMICs. Add documentation for it. Signed-off-by: Shyam Kumar Thella Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20200116161100.30637-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/qcom,spmi-sdam.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml new file mode 100644 index 000000000000..7bbd4e62044e --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/qcom,spmi-sdam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI SDAM DT bindings + +maintainers: + - Shyam Kumar Thella + +description: | + The SDAM provides scratch register space for the PMIC clients. This + memory can be used by software to store information or communicate + to/from the PBUS. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - qcom,spmi-sdam + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + - ranges + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + description: + Offset and size in bytes within the storage device. + + bits: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 + items: + items: + - minimum: 0 + maximum: 7 + description: + Offset in bit within the address range specified by reg. + - minimum: 1 + description: + Size in bit within the address range specified by reg. + + required: + - reg + + additionalProperties: false + +examples: + - | + sdam_1: nvram@b000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,spmi-sdam"; + reg = <0xb000 0x100>; + ranges = <0 0xb000 0x100>; + + /* Data cells */ + restart_reason: restart@50 { + reg = <0x50 0x1>; + bits = <6 2>; + }; + }; +... -- cgit v1.2.3