From 20b4f0f120eaa9b865205cc2788fa9a27b38421e Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Fri, 10 Jul 2026 00:12:02 +0530 Subject: dt-bindings: arm-smmu: Document GPU SMMU for Shikra SoC Add specific compatible strings to document the GPU SMMU present in the Shikra SoC. Signed-off-by: Bibek Kumar Patro Reviewed-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a701dec2fa0a..ad15fda5c25e 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -108,6 +108,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 @@ -543,6 +544,7 @@ allOf: - enum: - qcom,milos-smmu-500 - qcom,sar2130p-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm8550-smmu-500 - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 -- cgit v1.2.3 From 925f98235a729a87e632d6366fc749faac0463b4 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 18 Jul 2026 02:11:29 +0530 Subject: dt-bindings: arm-smmu: Document GPU SMMU for Eliza SoC Add specific compatible strings to document the GPU SMMU present in the Eliza SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Akhil P Oommen Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ad15fda5c25e..d87281026a71 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -95,6 +95,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,eliza-smmu-500 - qcom,glymur-smmu-500 - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 @@ -572,6 +573,7 @@ allOf: compatible: items: - enum: + - qcom,eliza-smmu-500 - qcom,glymur-smmu-500 - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 -- cgit v1.2.3 From 57f63e7082f66eccb2e6a3cf34f048c834a62e88 Mon Sep 17 00:00:00 2001 From: Bhargav Joshi Date: Wed, 8 Jul 2026 22:21:43 +0530 Subject: dt-bindings: iommu: ti,omap-iommu: Convert to DT schema Convert Texas Instruments OMAP2+ IOMMU from text to DT schema. Make the 'ti,hwmods' property optional and mark it deprecated as it is no longer used, it is kept to support legacy dtbs. Signed-off-by: Bhargav Joshi Reviewed-by: Rob Herring (Arm) Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/ti,omap-iommu.txt | 59 ----------- .../devicetree/bindings/iommu/ti,omap-iommu.yaml | 114 +++++++++++++++++++++ 2 files changed, 114 insertions(+), 59 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt deleted file mode 100644 index 4bd10dd881b8..000000000000 --- a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt +++ /dev/null @@ -1,59 +0,0 @@ -OMAP2+ IOMMU - -Required properties: -- compatible : Should be one of, - "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances - "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances - "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances - "ti,dra7-iommu" for DRA7xx IOMMU instances -- ti,hwmods : Name of the hwmod associated with the IOMMU instance -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, - and needs no additional data in the pargs specifier. Please - also refer to the generic bindings document for more info - on this property, - Documentation/devicetree/bindings/iommu/iommu.txt - -Optional properties: -- ti,#tlb-entries : Number of entries in the translation look-aside buffer. - Should be either 8 or 32 (default: 32) -- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing - back a bus error response on MMU faults. -- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM - syscon node that contains the additional control - register for enabling the MMU, and the MMU instance - number (0-indexed) within the sub-system. This property - is required for DSP IOMMU instances on DRA7xx SoCs. The - instance number should be 0 for DSP MDMA MMUs and 1 for - DSP EDMA MMUs. - -Example: - /* OMAP3 ISP MMU */ - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - /* DRA74x DSP2 MMUs */ - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - }; - - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - }; diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml new file mode 100644 index 000000000000..9588eb60376e --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/ti,omap-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP2+ IOMMU + +maintainers: + - Bhargav Joshi + +properties: + compatible: + enum: + - ti,omap2-iommu + - ti,omap4-iommu + - ti,dra7-dsp-iommu + - ti,dra7-iommu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#iommu-cells': + const: 0 + + ti,#tlb-entries: + description: Number of entries in the translation look-aside buffer. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 32] + default: 32 + + ti,iommu-bus-err-back: + description: + Indicates the IOMMU instance supports throwing back a bus error response + on MMU faults. + type: boolean + + ti,syscon-mmuconfig: + description: + Pair of the phandle to the DSP_SYSTEM syscon node that + contains the additional control register for enabling the MMU, and the + MMU instance number (0-indexed) within the sub-system. The instance number + should be 0 for DSP MDMA MMUs and 1 for DSP EDMA MMUs. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: phandle to the DSP_SYSTEM syscon node + - description: MMU instance number + enum: [0, 1] + + ti,hwmods: + description: Name of the hwmod associated with the IOMMU instance + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - '#iommu-cells' + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,dra7-dsp-iommu + then: + required: + - ti,syscon-mmuconfig + else: + properties: + ti,syscon-mmuconfig: false + +additionalProperties: false + +examples: + - | + mmu@480bd400 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x480bd400 0x80>; + interrupts = <24>; + ti,hwmods = "mmu_isp"; + ti,#tlb-entries = <8>; + }; + + - | + #include + + mmu@41501000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41501000 0x100>; + interrupts = ; + ti,hwmods = "mmu0_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + }; + + - | + #include + + mmu@41502000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41502000 0x100>; + interrupts = ; + ti,hwmods = "mmu1_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + }; -- cgit v1.2.3 From 7b97226bfb4ff96ecff7408160e8e50a5d70e48b Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Fri, 3 Jul 2026 00:50:33 -0700 Subject: dt-bindings: arm-smmu: qcom: Add compatible for Maili SoC Qualcomm Maili SoC includes apps smmu that implements arm,mmu-500, which is used to translate device-visible virtual addresses to physical addresses. Add compatible for it. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index d87281026a71..f2188942f877 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -39,6 +39,7 @@ properties: - qcom,glymur-smmu-500 - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 + - qcom,maili-smmu-500 - qcom,milos-smmu-500 - qcom,nord-smmu-500 - qcom,qcm2290-smmu-500 @@ -625,6 +626,7 @@ allOf: - qcom,glymur-smmu-500 - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 + - qcom,maili-smmu-500 - qcom,milos-smmu-500 - qcom,nord-smmu-500 - qcom,qcs615-smmu-500 -- cgit v1.2.3 From 20df8037968d3c088e507586bcac44b51aae3cbd Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Mon, 22 Jun 2026 06:54:09 +0000 Subject: dt-bindings: iommu: Fix interrupt type in example The CMDQV interrupt on Tegra264 is edge-triggered per the hardware interrupt documentation, but the binding example describes it as level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so that it does not propagate the wrong trigger type. Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support") Reported-by: Nicolin Chen Signed-off-by: Ashish Mhetre Acked-by: Jon Hunter Acked-by: Nicolin Chen Acked-by: Conor Dooley Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = ; + interrupts = ; }; -- cgit v1.2.3