From 2c12d05d863708bc2e9d1ee13c6c1534bb990c0d Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Thu, 7 May 2026 22:25:12 +0800 Subject: dt-bindings: interconnect: qcom,sc8280xp-rpmh: Add reg and clocks for QoS Add the register range and clock properties needed for programming NoC QoS configuration on SC8280XP. Require a register range for the real NoC providers, require QoS clocks for aggre1_noc and aggre2_noc, and keep the virtual clk_virt and mc_virt providers without MMIO resources or clocks. Signed-off-by: Xilin Wu Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260507-sc8280xp-qos-v1-1-15135858cd98@radxa.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,sc8280xp-rpmh.yaml | 99 +++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml index 2a5a7594bafd..cd327a3bf3b9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml @@ -32,18 +32,115 @@ properties: - qcom,sc8280xp-nspb-noc - qcom,sc8280xp-system-noc + reg: + maxItems: 1 + + clocks: + minItems: 7 + maxItems: 8 + required: - compatible allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-mc-virt + then: + properties: + reg: false + clocks: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 MP AXI clock + - description: aggre USB4 AXI clock + - description: aggre USB4 1 AXI clock + - description: aggre USB NOC SOUTH AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre NOC PCIE0 tunnel AXI clock + - description: aggre NOC PCIE1 tunnel AXI clock + - description: aggre NOC PCIE 4 AXI clock + - description: aggre NOC PCIE SOUTH SF AXI clock + - description: aggre UFS CARD AXI clock + - description: DDRSS GPU AXI clock + - description: DDRSS PCIE SF TBU clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false unevaluatedProperties: false examples: - | - interconnect-0 { + #include + #include + + interconnect { + compatible = "qcom,sc8280xp-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@9100000 { + compatible = "qcom,sc8280xp-gem-noc"; + reg = <0x9100000 0xb8400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@16c0000 { compatible = "qcom,sc8280xp-aggre1-noc"; + reg = <0x16c0000 0x3af80>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; -- cgit v1.2.3 From b09a9fc46657f210e5fbc5299b7624ff54f7ee6e Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 27 May 2026 05:37:09 +0000 Subject: dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS Some interconnect nodes on X1E80100 have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock-gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-1-305c6539e6d2@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,x1e80100-rpmh.yaml | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml index 0840b0ec6e27..d863cddb21ac 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml @@ -46,6 +46,10 @@ properties: reg: maxItems: 1 + clocks: + minItems: 1 + maxItems: 6 + required: - compatible @@ -65,6 +69,73 @@ allOf: required: - reg + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-north-anoc + then: + properties: + clocks: + items: + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 MP AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-south-anoc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 TERT AXI clock + - description: aggre USB4_0 AXI clock + - description: aggre USB4_1 AXI clock + - description: aggre USB4_2 AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre2-noc + - qcom,x1e80100-clk-virt + - qcom,x1e80100-cnoc-cfg + - qcom,x1e80100-cnoc-main + - qcom,x1e80100-gem-noc + - qcom,x1e80100-lpass-ag-noc + - qcom,x1e80100-lpass-lpiaon-noc + - qcom,x1e80100-lpass-lpicx-noc + - qcom,x1e80100-mc-virt + - qcom,x1e80100-mmss-noc + - qcom,x1e80100-nsp-noc + - qcom,x1e80100-pcie-center-anoc + - qcom,x1e80100-pcie-north-anoc + - qcom,x1e80100-pcie-south-anoc + - qcom,x1e80100-system-noc + - qcom,x1e80100-usb-center-anoc + then: + properties: + clocks: false + unevaluatedProperties: false examples: @@ -80,4 +151,5 @@ examples: reg = <0x016e0000 0x14400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>; }; -- cgit v1.2.3 From 070c42f9e6d937087ac95cd00381d36d3b3c1de9 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 3 Jun 2026 11:26:12 +0000 Subject: dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-1-3c2e0b796e78@oss.qualcomm.com Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 41b9f758bf8b..3b8ebe17a976 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -17,6 +17,8 @@ description: properties: compatible: oneOf: + - enum: + - qcom,shikra-epss-l3 - items: - enum: - qcom,sc7180-osm-l3 -- cgit v1.2.3 From 565de44266e64bec1554e86584083b41ab76d9bd Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Mon, 22 Jun 2026 06:34:45 +0000 Subject: dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili SoC. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260622-maili_icc-v2-1-18b5ac08c04f@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,maili-rpmh.yaml | 127 +++++++++++++++ include/dt-bindings/interconnect/qcom,maili-rpmh.h | 171 +++++++++++++++++++++ 2 files changed, 298 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,maili-rpmh.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml new file mode 100644 index 000000000000..3db8d8b23219 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,maili-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Maili SoC + +maintainers: + - Raviteja Laggyshetty + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,maili-rpmh.h + +properties: + compatible: + enum: + - qcom,maili-aggre-noc + - qcom,maili-clk-virt + - qcom,maili-cnoc-main + - qcom,maili-gem-noc + - qcom,maili-llclpi-noc + - qcom,maili-lpass-ag-noc + - qcom,maili-lpass-lpiaon-noc + - qcom,maili-lpass-lpicx-noc + - qcom,maili-mc-virt + - qcom,maili-mmss-noc + - qcom,maili-nsp-noc + - qcom,maili-pcie-anoc + - qcom,maili-stdst-cfg + - qcom,maili-stdst-main + - qcom,maili-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-clk-virt + - qcom,maili-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-aggre-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-aggre-noc + - qcom,maili-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + gem_noc: interconnect@31100000 { + compatible = "qcom,maili-gem-noc"; + reg = <0x31100000 0x160200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible = "qcom,maili-aggre-noc"; + reg = <0x00f00000 0x56200>; + #interconnect-cells = <2>; + clocks = <&gcc_phy_axi_clk>, + <&gcc_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/include/dt-bindings/interconnect/qcom,maili-rpmh.h b/include/dt-bindings/interconnect/qcom,maili-rpmh.h new file mode 100644 index 000000000000..ae3e48b14eab --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,maili-rpmh.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_2 1 +#define MASTER_QUP_3 2 +#define MASTER_QUP_4 3 +#define MASTER_QUP_5 4 +#define MASTER_CRYPTO 5 +#define MASTER_IPA 6 +#define MASTER_QUP_1 7 +#define MASTER_SOCCP_PROC 8 +#define MASTER_QDSS_ETR 9 +#define MASTER_QDSS_ETR_1 10 +#define MASTER_SDCC_2 11 +#define MASTER_SDCC_4 12 +#define MASTER_UFS_MEM 13 +#define MASTER_USB3 14 +#define SLAVE_A1NOC_SNOC 15 + +#define MASTER_DDR_EFF_VETO 0 +#define MASTER_QUP_CORE_0 1 +#define MASTER_QUP_CORE_1 2 +#define MASTER_QUP_CORE_2 3 +#define MASTER_QUP_CORE_3 4 +#define MASTER_QUP_CORE_4 5 +#define MASTER_QUP_CORE_5 6 +#define SLAVE_DDR_EFF_VETO 7 +#define SLAVE_QUP_CORE_0 8 +#define SLAVE_QUP_CORE_1 9 +#define SLAVE_QUP_CORE_2 10 +#define SLAVE_QUP_CORE_3 11 +#define SLAVE_QUP_CORE_4 12 +#define SLAVE_QUP_CORE_5 13 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_FENCE 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_CNOC_CFG 7 +#define SLAVE_DDRSS_CFG 8 +#define SLAVE_IMEM 9 +#define SLAVE_PCIE_0 10 +#define SLAVE_PCIE_1 11 + +#define MASTER_GIC 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_GFX3D 4 +#define MASTER_LPASS_GEM_NOC 5 +#define MASTER_MSS_PROC 6 +#define MASTER_MNOC_HF_MEM_NOC 7 +#define MASTER_MNOC_SF_MEM_NOC 8 +#define MASTER_COMPUTE_NOC 9 +#define MASTER_ANOC_PCIE_GEM_NOC 10 +#define MASTER_QPACE 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define MASTER_WLAN_Q6 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC_LLCLPI_NOC 0 +#define SLAVE_LPASS_LPI_CC 1 +#define SLAVE_LLCC_ISLAND 2 +#define SLAVE_SERVICE_LLCLPI_NOC 3 +#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define MASTER_DDR_RT 1 +#define SLAVE_EBI1 2 +#define SLAVE_DDR_RT 3 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_MDSS_DCP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO_CV_PROC 7 +#define MASTER_VIDEO_EVA 8 +#define MASTER_VIDEO_MVP 9 +#define MASTER_VIDEO_V_PROC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_CFG_CENTER 0 +#define MASTER_CFG_EAST 1 +#define MASTER_CFG_MM_HF 2 +#define MASTER_CFG_MM_SF 3 +#define MASTER_CFG_NORTH 4 +#define MASTER_CFG_SOUTH 5 +#define MASTER_CFG_WEST 6 +#define SLAVE_AHB2PHY_SOUTH 7 +#define SLAVE_BOOT_ROM 8 +#define SLAVE_CAMERA_CFG 9 +#define SLAVE_CLK_CTL 10 +#define SLAVE_CRYPTO_CFG 11 +#define SLAVE_DISPLAY_CFG 12 +#define SLAVE_EVA_CFG 13 +#define SLAVE_GFX3D_CFG 14 +#define SLAVE_I2C 15 +#define SLAVE_IMEM_CFG 16 +#define SLAVE_IPC_ROUTER_CFG 17 +#define SLAVE_IRIS_CFG 18 +#define SLAVE_CNOC_MSS 19 +#define SLAVE_PCIE_0_CFG 20 +#define SLAVE_PCIE_1_CFG 21 +#define SLAVE_PRNG 22 +#define SLAVE_QSPI_0 23 +#define SLAVE_QUP_1 24 +#define SLAVE_QUP_2 25 +#define SLAVE_QUP_3 26 +#define SLAVE_QUP_4 27 +#define SLAVE_QUP_5 28 +#define SLAVE_SDCC_2 29 +#define SLAVE_SDCC_4 30 +#define SLAVE_TLMM 31 +#define SLAVE_UFS_MEM_CFG 32 +#define SLAVE_USB3 33 +#define SLAVE_VSENSE_CTRL_CFG 34 +#define SLAVE_PCIE_ANOC_CFG 35 +#define SLAVE_QDSS_CFG 36 +#define SLAVE_QDSS_STM 37 +#define SLAVE_TCSR 38 +#define SLAVE_TCU 39 + +#define MASTER_CNOC_STARDUST 0 +#define SLAVE_STARDUST_CENTER_CFG 1 +#define SLAVE_STARDUST_EAST_CFG 2 +#define SLAVE_STARDUST_MM_HF_CFG 3 +#define SLAVE_STARDUST_MM_SF_CFG 4 +#define SLAVE_STARDUST_NORTH_CFG 5 +#define SLAVE_STARDUST_SOUTH_CFG 6 +#define SLAVE_STARDUST_WEST_CFG 7 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_APSS_NOC 1 +#define MASTER_CNOC_SNOC 2 +#define SLAVE_SNOC_GEM_NOC_SF 3 + +#endif -- cgit v1.2.3