From c67b3c631a1bc02dba2c93bcb75eda54b607eae6 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:05:56 +0000 Subject: dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family RZ/V2H, RZ/V2N, and RZ/G3E support two optional external audio clock inputs (AUDIO_CLKB and AUDIO_CLKC) that can be used by the Audio Clock Generator (ADG) to derive internal audio clocks. The third ADG input (AUDIO_CLKA) is fed internally by the AUDIO_EXTAL pin and does not need a separate binding entry. Update the bindings to allow these optional clocks for all RZ/V2H family SoCs. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley Link: https://patch.msgid.link/20260525110603.4018170-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index f261445bf341..dd3e66a4559b 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -26,16 +26,22 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: AUDIO_EXTAL clock input - description: RTXIN clock input - description: QEXTAL clock input + - description: AUDIO_CLKB clock input + - description: AUDIO_CLKC clock input clock-names: + minItems: 3 items: - const: audio_extal - const: rtxin - const: qextal + - const: audio_clkb + - const: audio_clkc '#clock-cells': description: | -- cgit v1.2.3 From 91fb4643954379f8493dba649d520c23f0d1f4e6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 23 Jun 2026 17:20:37 +0100 Subject: dt-bindings: clock: renesas,versaclock7: Update maintainer Alex' email is bouncing. Update the maintainers list with my contact details to take over the schema maintenance. While at it, extend the entry in MAINTAINERS to the Versaclock 3 clock driver. Signed-off-by: Biju Das Reviewed-by: Brian Masney Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250905143441.7082-1-biju.das.jz@bp.renesas.com Link: https://patch.msgid.link/20260623162039.153291-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml | 2 +- MAINTAINERS | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml index b339f1f9f072..990d287d0a90 100644 --- a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas Versaclock7 Programmable Clock maintainers: - - Alex Helms + - Biju Das description: | Renesas Versaclock7 is a family of configurable clock generator and diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..112e5f031007 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23090,10 +23090,12 @@ L: linux-renesas-soc@vger.kernel.org S: Maintained F: drivers/phy/renesas/phy-rcar-gen3-usb*.c -RENESAS VERSACLOCK 7 CLOCK DRIVER -M: Alex Helms +RENESAS VERSACLOCK 3 and VERSACLOCK 7 CLOCK DRIVER +M: Biju Das S: Maintained +F: Documentation/devicetree/bindings/clock/renesas,5p35023.yaml F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml +F: drivers/clk/clk-versaclock3.c F: drivers/clk/clk-versaclock7.c RENESAS X9250 DIGITAL POTENTIOMETERS DRIVER -- cgit v1.2.3