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This was supposed to loop over the individual evicted list, as the
kernel and always_valid evicted lists were already handled in
amdgpu_vm_validate.
Without this, BOs that were created and evicted before a userq was made
would never end up in an eviction fence rearm.
Also add the missing ref to the BO before drm_exec locks and refs it.
Fixes: 4cdbba5a16aa ("drm/amdgpu: restructure VM state machine v4")
Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Set vm_manager.spm_vmid to the top GFXHUB VMID so the SPM reservation
path hands out a fixed, isolated VMID on gfx8 instead of borrowing one
from the graphics pool.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Set vm_manager.spm_vmid to the top GFXHUB VMID so the SPM reservation
path hands out a fixed, isolated VMID on gfx7 instead of borrowing one
from the graphics pool.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This adds the regCP_ME1_INT_STAT_DEBUG and regCP_ME2_INT_STAT_DEBUG registers that
were missing from the GC 11.0.0 headers but found in GC 11.0.3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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The uapi documents drm_amdgpu_gem_list_handles_entry.alignment as
"physical start_addr alignment in bytes", and GEM_OP
GET_GEM_CREATE_INFO returns the same value in bytes, but
GEM_LIST_HANDLES returns tbo.page_alignment, which is in pages. For a BO
created with a 64 KiB alignment on navi31:
GET_GEM_CREATE_INFO: alignment=65536
GEM_LIST_HANDLES: alignment=16
so a user such as CRIU that recreates BOs from this list uses the wrong
alignment. Convert it to bytes.
Fixes: f9db1fc52ceb ("drm/amdgpu: Add ioctl to get all gem handles for a process")
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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The SPM (Streaming Performance Monitor) path needs a VMID that is
isolated from other GPU contexts. Introduce vm_manager.spm_vmid to let
a GFXHUB dedicate a VMID to SPM.
When spm_vmid is set, exclude it from both the kernel-queue pool and
vmid_uq_mask_gfxhub, so neither the round-robin kernel-queue allocator
nor MES/Userqueues ever maps another context onto it.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Fix the ambiguous names in amdgpu_vmid_mgr_set_vmid_mask()'s
parameters so there is no confusion.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Report the actual bad page count and convert the record threshold to
pages using the per-ASIC row size. Keep threshold decisions in record
units.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Report a bad page threshold breach only when the saved record count
exceeds the configured limit. Allow unlocking at equality to keep the
EEPROM status consistent with that boundary.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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The RAS core derives the bad page threshold from
con->reserved_pages_in_bytes when amdgpu_ras_mgr_sw_init() builds the
EEPROM configuration. That field is still zero at this point, so the
threshold falls back to the 16MB default and ends up at 128 pages on
ASICs that reserve 32MB.
Set the reserved vram size before RAS core sw init so the threshold is
computed from the per-ASIC value.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Read the feature status of RAS_CORE_FW_FEATURE_BIT_RAS_EEPROM to determine
whether to use firmware-managed EEPROM.
Signed-off-by: Ce Sun <cesun102@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Build and program doorbell entry control values through the common
NBIO helpers while preserving the existing nbif v6_3_1 client
routing and field values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Build and program doorbell entry control values through the common
NBIO helpers while preserving the existing nbio v7_11_4 client
routing and field values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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nbio v7_11_4 and v7_11_5 now have dedicated implementations.
Select nbio v7_11_4 function and HDP flush tables during IP
discovery, and remove the version-specific register offsets
and doorbell handling from nbif v6_3_1.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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RAS early init executes prior to smu_sw_init, leaving feature_num as 0
and triggering invalid bitmap operations.
Signed-off-by: Ce Sun <cesun102@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Only the mode that halts runtime services flags the device once the bad
page threshold is reached, so on a default or warn-only threshold the
in-band CPER record and the out-of-band RMA reason are not emitted even
though the table records that the threshold was hit.
Track the threshold condition separately from the halt decision and use
it to drive the report, so every mode except the debug one tells the
host that the device reached its bad page budget.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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The EEPROM table is tagged as over threshold while the new bad page
records are written out, so the table status queried while the records
are only queued still reports the table as writable. The device is
therefore never flagged as having reached the threshold and neither the
in-band CPER record nor the out-of-band RMA reason is emitted.
Re-evaluate the table status once the records have been appended, so the
report is driven by the state that was just persisted.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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In hqd_dump function
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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nbio v7_11_4 uses different bif doorbell port registers than
nbif v6_3_1, and different HDP flush and memory coherency
registers than nbio v7_11_5.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Add header files for nbif v4_10_0 register offsets
and shift masks
These register definitions are derived from nbif
v6_3_1 source file which uses the _nbif_4_10 suffix
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Describe the nbio v7_11_5 S2A doorbell layout and
existing client-to-port mappings, then build and
program the CP, RLC, IH, SDMA, and VPE entries
through the common NBIO helpers.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Describe the nbio v7_9 S2A doorbell layout and
client-to-port mappings, then build and program
the IH, SDMA, and VCN entries through the common
NBIO helpers.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Some NBIO generations expose doorbell control register
instances through global SMN addresses. Extend the common
doorbell entry description and programming helper to
select this access path
The IP-specific mapping records the target register
instance while callers remain responsible for invoking
their doorbell callback for each required instance.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Build and program the CP, RLC, IH, SDMA, and VCN
doorbell entries through the common NBIO helpers
while retaining the existing callback interface
and v4_3 client routing values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Describe the nbio v4_3 doorbell entry ctrl
field layout and initialize the CP, IH, SDMA,
RLC, and VCN port and register assignments.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Build doorbell_entry_ctrl and doorbell_entry_ctrl1
values through the common field helper while retaining
the existing nbio callback interface and preserving
nbio v6_3_2 client routing values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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When a debugged process exits, kfd_process_notifier_release_internal()
first removes it from kfd_processes_table and then calls
kfd_dbg_trap_disable(), which drains the process interrupts. The drain
sends a fence through the IH and waits, without a timeout, for
kfd_process_close_interrupt_drain() to wake it up. That wakeup looks
the process up by PASID in kfd_processes_table, which no longer holds
it, so the wakeup is lost and the exiting task sleeps forever. The
fatal signal has already been consumed in do_exit(), so the
interruptible wait cannot be broken either.
The wait happens inside the mmu_notifier release callback, i.e. within
the global mmu_notifier SRCU read-side critical section, so every
synchronize_srcu() on it stalls as well. Any other process releasing
its mm then hangs in D state and the system needs a reboot. This is
seen with rocgdb on MI300X.
Fix this by:
- Waiting on a completion in struct amdgpu_fpriv, looked up by PASID
through amdgpu_pasid_xa, instead of looking the process up in
kfd_processes_table. The DRM file owning the PASID is still
referenced by KFD while it drains, so the drain fence always finds
its waiter. The drain logic moves to amdgpu_ids.c and KFD only
passes the PASID.
- Bounding the wait with a timeout, since the fence can be lost when
the IH ring or the KFD interrupt FIFO overflows, and warning when the
drain does not complete.
- Passing drain_irqs to kfd_dbg_trap_disable() and skipping the drain
when the process itself exits. Its interrupts are no longer delivered
once it is out of kfd_processes_table, and its PASID owner is cleared
before the PASID is freed and later reallocated cyclically.
v2: track drains with a completion in amdgpu_fpriv via amdgpu_pasid_xa
and move the drain logic to amdgpu_ids.c; pass drain_irqs to
kfd_dbg_trap_disable() and skip the drain on process exit instead
of deferring it (Felix)
v3: use AMDGPU_FENCE_JIFFIES_TIMEOUT for the drain timeout; drop
kfd_process_close_interrupt_drain() and call
amdgpu_pasid_drain_irq_done() directly from the interrupt handlers
(Felix)
Fixes: 12fb1ad70d65 ("drm/amdkfd: update process interrupt handling for debug events")
Signed-off-by: Heng Zhou <Heng.Zhou@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Describe nbio v6_3_2 doorbell_entry_ctrl and
doorbell_entry_ctrl1 field layout from IP register
header and initialize gc, ih, vcn, and sdma
port and register assignments.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Add doorbell layout and field descriptions together
with common helpers to build and program nbio
doorbell entries.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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CP resume through MMIO programming is no longer
supported on GFX 12.0 and later generations. Remove
this obsolete code to prevent it from being carried
forward into future GFX generations.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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amdgpu_cs_parser_bos() allocates an HMM range for every userptr entry of
the BO list and looks up the user pages. Those ranges are only freed when
amdgpu_cs_parser_bos() itself fails or when amdgpu_cs_submit() checks
them under the notifier lock. If amdgpu_cs_patch_jobs(),
amdgpu_cs_vm_handling(), amdgpu_cs_sync_rings() or the early part of
amdgpu_cs_submit() fails, nothing frees them: neither
amdgpu_cs_parser_fini() nor amdgpu_bo_list_free() touch e->range.
Each such CS then leaks the range, its hmm_pfns array (8 bytes per page
of the userptr BO) and the BO reference the range holds. An IB on a ring
that patches the CS in place (e.g. VCN) with an unmapped va_start fails
in amdgpu_cs_patch_ibs() and takes this path.
Free the ranges on those error paths. Ranges amdgpu_cs_submit() already
dropped are NULL, so freeing them again is a no-op.
Fixes: fec8fdb54e8f ("drm/amdgpu: fix userptr HMM range handling v2")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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amdgpu_debugfs_gpr_read() drops its runtime PM reference right after
reading the wave registers. When copying them to userspace fails, it
jumps to the err label, which drops the reference a second time. A read
into a bad buffer on Navi31 either steals a reference somebody else
holds (power/runtime_usage goes from 1 to 0) or underflows the count:
amdgpu 0000:03:00.0: Runtime PM usage count underflow!
The registers are already in the kernel buffer at that point, so finish
the hardware access first and copy the buffer with a single
copy_to_user() instead of the put_user() loop with its own error path.
Fixes: 9eee152aab56 ("drm/amdgpu/debugfs: fix ref count leak when pm_runtime_get_sync fails")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This version brings along the following updates:
- Refactor DC IP request control in HWSS.
- Fix rotate 90 degrees surface corruption issue.
- Refactor DPP root clock control in HWSS.
- Fix upsampling and linear scaling.
- Use aux hw inst if no ddc pin exists.
- Directly include compiler_attributes.h.
- Fix frac_urg_bw conversion to correct U0.10 format.
- Do full link training during HDR/SDR seamless switch.
- Fix SPL format handling for linear scaling and upsampling.
- Update DCN42 cstate latencies.
- Invalidate the DRR shadow after a hardware re-init.
- Program HDR visual confirm based on per pipe info.
- Split link_set_dsc_on_stream into encoder and DSC components.
- Add new config_dsc hwseq function for DCN60.
- Program DSC prior to OTG enable starting DCN60.
- Improve mandatory pstate optimization and check.
- Disable HUBP/DPP power gating on DCN42.
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
Driver-controlled HUBP and DPP power gating can cause display underflow
on DCN42.
[How]
Set disable_hubp_power_gate and disable_dpp_power_gate in the DCN42
driver debug defaults as a temporary workaround.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[WHY&HOW]
Improves the optimization heuristic for "ideal" disallow time to clamp
to a number more likely to pass the mandatory pstate checks.
Fixes core calculations to account for reserved time when considering
the allow time for mandatory pstate checks.
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
Current DSC enable sequence is intertwined with the DPMS on sequence.
The sequence has become unnecessarily confusing, and resulted in cases
where DSC is programmed unexpectedly, or in an incorrect sequence.
Current sequence enables OTG before DSC. After discussing with HW team,
there should be no issue with enabling DSC first before OTG.
[How]
Starting with DCN60, skip DSC HW programming in the DPMS sequences.
Add enable DSC function call prior to OTG enable, and similarly for the
disable case.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
The current DSC block programming sequence is intertwined with the
stream encoder DSC-related programming. Logically, the programming of
the DSC (front end) and stream encoder (back end) blocks should be
independent of each other.
[How]
Create a new hwseq function config_dsc to handle the DSC block
programming sequence.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
DSC block programming should be independent from link programming. This
should be refactored such that DSC block programming is in HWSS.
[How]
The first step to the refactor is to split the existing logic into the
encoder portion and the DSC block portion.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Description]
HDR visual confirm should be programmed based on per-pipe info, not
top pipe info. There exists scenarios where an HDR app has a desktop
plane still active (due to SW cursor) which is ARGB8888. Taking the top
pipe info will give the wrong visual confirm color.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
dc_stream_adjust_vmin_vmax() skips hardware programming when
stream->adjust already matches the request and timing_adjust_pending is
clear. That treats stream->adjust as a faithful shadow of the OTG, but
dc_set_power_state(D0) calls init_hw(),
which returns OTG_V_TOTAL_MIN/MAX and the static screen triggers to
their reset defaults without touching any stream. After an S3/S4 resume
or a GPU reset the shadow claims hardware is current when it is not.
A resume that reuses the same stream object also short-circuits
dc_commit_streams() on !streams_changed(), so enable_stream_timing()
never runs either and nothing reprograms DRR. Replay then fails to arm:
the static screen trigger is at its reset value and the coasting vtotal
no longer matches the OTG.
The max_v_total overflow path has a second problem. When OTG v_count
halt is not allowed it stores the new values and marks the adjustment
pending even though nothing was programmed, and no later call with the
same values can clear that flag.
[How]
Add invalidate_drr_adjust() to mark every stream in current_state as
having a pending timing adjustment, and call it once hardware has been
re-initialized in dc_set_power_state(),
so the next dc_stream_adjust_vmin_vmax() reprograms the OTG.
Hoist the max_v_total check above the point where stream->adjust is
updated and return early when v_count halt is not allowed, leaving the
shadow describing the OTG instead of latching a flag nothing can clear.
On the paths that do update stream->adjust, set the flag up front and
clear it only after set_long_vtotal() or set_drr() has actually run.
Reviewed-by: Josip Pavic <josip.pavic@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[WHY]
New cstate exit latency measurements from DCN IPSE for DCN42.
[HOW]
Update stutter latencies in the DCN42 soc bb:
- LPDDR5: exit 13.5us, enter plus exit 15.5us
- DDR5: exit 23.0us, enter plus exit 25.0us
Pstate change latency is already 36us for both.
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why/How]
For upsampling/linear scaling case, SPL needs to consider format
to be rgb and not yuv.
Reviewed-by: Samson Tam <samson.tam@amd.com>
Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
The forced_psr_active gates added across hwseq skipped backlight, ABM,
CRTC/OTG, PHY link output and DPMS teardown whenever seamless switch happens.
This meant the link was not fully retrained during an HDR/SDR switch, going beyond the
intended scope of just preventing the frozen frame from being disrupted.
[How]
Removed the forced_psr_active conditionals from early return, the dpms_on gate,
the disable_link_output gates, and the reset_back_end_for_pipe
dpms_off/abm/disable_crtc/enable_optc_clock skips and hwseq,
restoring their unconditional behavior so full link training runs during the HDR/SDR
switch even with seamless switch
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[why * how]
DCHUBBUB_ARB_FRAC_URG_BW_* registers only have 10 programmable bits that are formatted in
U0.10 fixed point. Multiplying the fraction by 1000 is incorrect, and understates the
fraction by 2.34%.
Rounding or truncating is not correct either since it can cut off 0.1% of the fraction
which has direct implications on the assumed deadlines and TTU, albeit minor.
Scale the fraction by the correct 1024 value, use ceiling to ensure the assumed fraction is
maintained, and clamp to 1023 since the register field is only 10 bits wide.
Clamping from 1024 -> 1023 only impacts modes at > 99.9% fractions.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why & How]
External improvements will allow DC to directly include Linux Kernel
headers without the os_types.h proxy. As a test, dc_memory_pool can
directly include compiler_attributes.h for __must_check and _aligned.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Description]
On newer products no DDC / I2C pins exist for DP. In this case
instance "ddc line" using aux hw inst, matching the i2c scenario
where we must rely on I2C over aux.
Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
When a subsampled YUV surface is scaled in linear space, the chroma
planes are interpolated before being upsampled to 4:4:4, producing
incorrect chroma on the scaled output.
[How]
Enable the CNVC chroma upsampler for these cases:
- resource_is_upsp_required() selects the mode from the surface format
- DPP programs the pre-CSC matrix
- DCN60 programs the CNVC_UPSP coefficients
- SPL and DSCL treat a pipe with upsp enabled as 4:4:4 RGB
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[WHY]
DPP_ROOT_CLOCK_CONTROL carried a dce_hwseq handle and re-evaluated
dc->debug in the executor, mixing build-time policy with execution.
DCCG DPP root clock gating also read dc->debug directly, so the policy
lived in several layers and could diverge.
[HOW]
- Store struct dccg *dccg in struct dpp_root_clock_control_params. The
executor calls dccg->funcs->dpp_root_clock_control on the captured
instance without looking up dc or policy.
- Add is_dpp_root_clock_control_supported(root_clock_optimization_dpp,
clock_on) to hwseq_private_funcs as a pure ASIC policy: DCN314 needs
the optimization for both directions, DCN35/351/42 only for gating.
- Add hwss_is_dpp_root_clock_control_allowed() as the single
qualification point for the BLS builder and legacy HWSS call-sites.
Without an ASIC hook it applies the DCN35 rule. The hwseq
dpp_root_clock_control wrappers become pass-through.
- The builder skips the step instead of emitting a no-op when the hwseq
hook is absent or the policy rejects the direction.
- Add root_clock_optimization_dpp to struct dccg as a mirror of
dc->debug.root_clock_optimization.bits.dpp. dc core syncs it for all
ASICs after resource pool creation and before every init_hw, so DM
overrides applied after dc_create are honored. DCCG35/42 no longer
read dc->debug for the DPP bit; the RCG allow check moves from
dccg35_set_dppclk_rcg to its callers.
- Validate builder and executor inputs, including physical DPP index
bounds for harvested configurations.
- Update BLS/DCCG documentation, golden serialization, DML2.1 stub
headers and unit tests in core, dccg and hwss.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why&How]
Incorrect dcc_control mode causes visual corruption in vertical mode.
For vertical scan with req128_vert_wc clear, use dcc_control__256_64_64
when the vertical segment order is non-contiguous and
dcc_control__256_256_xxx otherwise.
Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[WHY]
Refactor DC_IP_REQUEST_CNTL to follow BLS rules: replace struct dc *dc
with dce_hwseq handle in parameter structure and vtable signature, and
add comprehensive hardware access guards.
[HOW]
- Update struct dc_ip_request_cntl_params to store struct dce_hwseq *hws
instead of struct dc *dc.
- Update hwseq_private_funcs.dc_ip_request_cntl signature and dcn401 implementation
to take (struct dce_hwseq *hws, bool enable).
- Add null checks for hws context, registers, shifts, and masks in dcn401_dc_ip_request_cntl.
- Update hwss_dc_ip_request_cntl executor and hwss_add_dc_ip_request_cntl builder.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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