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path: root/drivers/gpu/drm/amd/amdgpu
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2026-07-28drm/amdgpu/mes11: drop all BUG()sAlex Deucher
There's no need to crash the kernel for these cases. Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu/imu12: WARN() rather than BUG()Alex Deucher
There's no need to crash the kernel for this case. Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: avoid resource leak on SR-IOV VF with AMDGIM_FEATURE_RAS_CPER ↵Ce Sun
enabled Original amdgpu_cper_fini skips all CPER cleanup work for any SR-IOV VF directly. When AMDGIM_FEATURE_RAS_CPER is enabled on VF side, CPER related buffers/workitems are allocated during initialization, but the old code returns early without releasing these resources, which leads to kernel memory leak. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: normalize error return of RAS command wrapper functionsCe Sun
User-space read/write syscalls interpret positive driver return values as successful transfer sizes. Our current RAS wrappers return positive error codes, so we must convert them to standard negative error codes. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: reduce early full GPU access during SR-IOV initchong li
Allow early FB reads to fall back to BAR0 when the VRAM aperture is not ready. This lets SR-IOV VFs consume host-provided init data before requesting full GPU access. For ASICs that support request_init_data, defer full GPU access until after non-GPU early init to shorten the full-access window. Legacy ASICs(before NV12) do not send request_init_data; the host dumps init data only during full GPU access, so keep the original early full-access request path for them. Signed-off-by: chong li <chongli2@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: convert ptl_hw_supported to enumVictor Zhao
Convert ptl_hw_supported to enum with three states: - AMDGPU_PTL_HW_UNINIT: not yet initialized - AMDGPU_PTL_HW_SUPPORTED: initialized and supported - AMDGPU_PTL_HW_NOT_SUPPORTED: initialized and not supported This allows skipping PTL initialization attempts when hardware is known to not support it, avoiding repeated initialization failures after GPU resets. v2:move ptl_hw_supported_state to AMDGPU_PTL_HW_NOT_SUPPORTED regardless of error code during first time initialization. Print init fail log when error code is not EOPNOTSUPP. Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: always get PTL state from PSP under sriovVictor Zhao
In SR-IOV mode, always query the latest PTL status from host via psp_performance_monitor_hw() to ensure the sysfs shows real-time hardware state. Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: add generic interfaces for PTL requests in virtualizationVictor Zhao
Add Performance Throttle Limiter (PTL) support for SR-IOV guest. Since VF cannot communicate with PSP directly at runtime in SR-IOV environment, use mailbox data fields to pass PTL parameters to PF, and parse response status from host mailbox registers. v2: - remove redundent checks - remove unused marco Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: enable mode2 reset for SMU IP v15.0.5Kanala Ramalingeswara Reddy
Set the default reset method to mode2 for SMU 15.0.5. Signed-off-by: Kanala Ramalingeswara Reddy <Kanala.RamalingeswaraReddy@amd.com> Reviewed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Fix NBIO 7.11.5 offsetsShubhankar Milind Sardeshpande
Fix NBIO 7.11.5 related offsets Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Enable support for PSP 15_0_5Shubhankar Milind Sardeshpande
Add PSP 15.0.5 related offsets for GFX to KMD interface and enable support for it. Co-developed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: move debug_vm handling to amdgpu_cs_parser_finiPierre-Eric Pelloux-Prayer
The commit referenced below restarts the CS if the validation is still in progress. When debug_vm is enabled, all BOs from the CS are invalidated so we will hit an infinite loop. To avoid that, defer BO invalidation to amdgpu_cs_parser_fini. Fixes: 59720bfd8c6d ("drm/amdgpu: restart the CS if some parts of the VM are still invalidated") Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Update message IDs to PMFW to correctly gather GFXOFF residency logsFares Soliman
Updates PPSMC_MSGs and set/get functions for gathering GFXOFF logs on Van Gogh. Logs are now gathered live rather than starting then stopping logging and reading an average value afterwards. This is in accordance to changes made in PMFW. In regards to messageID 0x52, the old interface uses a start/stop parameter, and the new one doesn't. The firmware is checked to determine which method to use. v2: added firmware guard to new interface, old interface kept as fallback Signed-off-by: Fares Soliman <Fares.Soliman@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Add missing MES helper parameter descriptionsSrinivasan Shanmugam
Complete the kernel-doc comments for the MES RS64 memory, process context, and gang context helper functions by documenting the missing function parameters to keep the kernel-doc comments consistent with their function signatures. Fixes: 56f7ea845e7d ("drm/amdgpu: add RS64 local memory context array init/fini") Fixes: cf5f98609a03 ("drm/amdgpu: add mes process context alloc/free") Fixes: 5ab89b491f21 ("drm/amdgpu: add mes gang contex alloc/free helper") Cc: Prike Liang <Prike.Liang@amd.com> Cc: Michael Chen <michael.chen@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Fix writeback completion timingAlex Hung
[WHY] The out fence was signalled on the first vblank after arming, before the DMA finished copying, and the old code worked around this with an mdelay() in the IRQ handler. [HOW] Hold a vblank reference while writeback is pending and signal the out fence on the second vblank instead of using mdelay(). Add amdgpu_dm_crtc_complete_writeback() to finish and clean up writeback from both the IRQ and teardown paths. This can be verified by running IGT's kms_writeback 20 times without timeout errors. Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Pack nested ucode_info structAlex Hung
Building for ARCH=um with W=1 C=1 makes the "amd_sriov_msg_vf2pf_info must be 1 KB" static assertion in amdgv_sriovmsg.h fail under sparse, exposed after UML builds were enabled. Sparse does not honor #pragma pack(push, 1) for the nested ucode_info struct, so it sizes each element as 8 bytes instead of 5 and computes the surrounding structure as larger than 1 KB. The compilers get this right via the enclosing pragma, but the annotation should be explicit. Fixes: af3f2f5db265 ("drm/amdgpu: Remove UML build exclusion from Kconfig") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607091659.SHEscT0c-lkp@intel.com/ Cc: Harry Wentland <harry.wentland@amd.com> Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Fix __rcu fence pointer accessesAlex Hung
Building for ARCH=um with W=1 C=1 makes sparse report "incompatible types in comparison expression (different address spaces)" warnings in the KFD code, exposed after UML builds were enabled: - amdgpu_amdkfd_fence.c compares the __rcu-annotated dma_fence.ops pointer directly in to_amdgpu_amdkfd_fence(). - amdgpu_amdkfd_gpuvm.c compares the __rcu eviction fence pointer directly in amdgpu_amdkfd_gpuvm_restore_process_bos(). Fixes: af3f2f5db265 ("drm/amdgpu: Remove UML build exclusion from Kconfig") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607091659.SHEscT0c-lkp@intel.com/ Cc: Harry Wentland <harry.wentland@amd.com> Assisted-by: Copilot:Claude-Opus-4.8 Signed-off-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Drop vm_manager PASID to VM mappingSrinivasan Shanmugam
VM lookup users now resolve DRM PASIDs through the global PASID xarray: PASID -> fpriv -> VM The per-device vm_manager.pasids xarray is no longer needed. Remove PASID registration and removal from the VM init/fini paths, drop vm_manager PASID initialization/cleanup, and remove the xarray from struct amdgpu_vm_manager. The PASID is allocated only after amdgpu_vm_init() completes, so the initializer no longer consumes or assigns a PASID. Remove the now-unused argument while keeping vm->pasid as per-VM state for TLB flushes and other hardware programming paths. v6: - Remove the now-unused PASID argument from amdgpu_vm_init(). - Remove the related vm->pasid assignment and error-path reset from VM init. - Keep vm->pasid in struct amdgpu_vm for existing hardware users. Cc: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Resolve VM through DRM PASID ownershipSrinivasan Shanmugam
Allocate DRM PASIDs with fpriv and resolve VM lookup users through: PASID -> fpriv -> VM This preserves the root BO reference and revalidation flow in amdgpu_vm_lock_by_pasid(). The obsolete per-device vm_manager.pasids mapping is removed by the following patch in this series. v6: - Allocate and publish the DRM PASID after amdgpu_vm_init() completes. - Assign the allocated PASID to vm->pasid in the DRM open path. - Unpublish PASID ownership before tearing down the VM in both the open-failure and normal file-close paths. v5: - Delay DRM PASID allocation until after amdgpu_vm_init() completes. v4: - Allocate DRM PASIDs with fpriv directly. - Squash ownership registration and PASID lookup conversion. Cc: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: Allow PASID allocator to store fpriv ownerSrinivasan Shanmugam
AMDGPU already has a global PASID xarray used for PASID allocation. Allow amdgpu_pasid_alloc() to optionally store the owning DRM file-private object directly. Initial callers pass NULL. A later patch in this series passes the DRM file-private object for DRM PASIDs. This prepares for using: PASID -> fpriv -> VM instead of: PASID -> VM Clear the stored owner from amdgpu_pasid_free_delayed() before waiting for outstanding fences so PASID lookups cannot observe a stale fpriv while the PASID itself is pending delayed release. v6: - Correct the PASID allocator kernel-doc to refer to the XArray cyclic allocator. - Document that PASID owner lookup may return NULL and that the returned fpriv remains valid only while the PASID lock is held. - No code changes. Retain Christian's Reviewed-by tag. v5: - Store NULL instead of xa_mk_value(0) for ownerless PASIDs. - Simplify owner clearing by unconditionally storing NULL. v4: - Add fpriv as an optional parameter to amdgpu_pasid_alloc(). - Drop separate amdgpu_pasid_set_fpriv()/clear_fpriv() helpers. - Clear PASID owner from amdgpu_pasid_free_delayed(). Cc: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu/ras: Add debug mask to disable CE logs for unirasCe Sun
Add debug mask to disable kernel logs of RAS correctable errors, including both ACA and CE error counter kernel messages. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu/imu11: WARN() rather than BUG()Alex Deucher
There's no need to crash the kernel for this case. Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amdgpu: skip clearing empty freed VM list on GEM closeBob Zhou
amdgpu_vm_clear_freed() allocates an amdgpu_sync object and walks the VM reservation fences via amdgpu_sync_resv() before checking whether vm->freed has anything to clear. Return early when the list is empty to skip this overhead on a hot path (every GEM close and command submission). Signed-off-by: Bob Zhou <bobzhou2@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-17drm/amdgpu/ttm: Consider concurrent VM flushes for buffer entitiesTimur Kristóf
Allow using multiple SDMA schedulers only on GPUs where we are allowed to do concurrent VM flushes. This consideration is necessary because all GART windows are mapped in VMID 0 (the kernel VMID) so each buffer entity would flush VMID 0 concurrently. Practically this means that we can't use multiple SDMA engines for TTM on GFX6-8 and Navi 1x. Fixes: 01c836788b37 ("drm/amdgpu: pass all the sdma scheds to amdgpu_mman") Fixes: e4029f7a9474 ("drm/amdgpu: only use working sdma schedulers for ttm") Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit a8171229bc836607fbc225d323ebc4d14489cfbb)
2026-07-17drm/amdgpu: Disable PCIe dynamic speed switching on Ryzen Pinnacle RidgeMario Limonciello
AMD Ryzen Pinnacle Ridge (Zen+, family 0x17 model 0x08) CPUs have PCI controllers that don't support PCIe dynamic speed switching, causing system freezes during GPU initialization when enabled. Disable dynamic speed switching when this CPU is detected. Assisted-by: Claude:sonnet Fixes: 466a7d115326 ("drm/amd: Use the first non-dGPU PCI device for BW limits") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5436 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Link: https://patch.msgid.link/20260709031520.841611-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 9ceb4e034a327a04155f32f1cd1a5031dfa5fe02) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: always emit the job vm fenceAlex Deucher
We need the fence to reemit the gds switch or spm update after a queue reset. Fixes: a17ef941212b ("drm/amdgpu: rework ring reset backup and reemit v9") Cc: timur.kristof@gmail.com Cc: christian.koenig@amd.com Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit bc639a9eadc75822f7f15a4315c198a4b5513bd2) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: Reserve space for IB contents in devcoredumpsTimur Kristóf
Currently the contents of IBs are abruptly cut off and don't show the full contents. This patch makes sure to reserve space for those contents too so they may be printed. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 4e2c0821509fed754e8c31d5053d152fbb3484a5) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: Print vmid, pasid and more task info in devcoredumpTimur Kristóf
These are in the dmesg logs but are missing from devcoredumps. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit fed7aa36d79802c3e02acd05aeae8b0a877e47c2) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: Release VFCT ACPI table referenceMario Limonciello
amdgpu_acpi_vfct_bios() fetches the VFCT table with acpi_get_table() but never releases it. acpi_get_table() takes a reference on the table (incrementing its validation_count and mapping it on the 0->1 transition); without a paired acpi_put_table() the mapping is leaked on every call, whether or not a matching VBIOS image is found. Route all exit paths after the table is acquired through a common acpi_put_table(). The VBIOS image is copied out with kmemdup() before the table is released, so it remains valid for the caller. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260708193518.702584-3-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ca5988682b4cba4cd125a0fa99b2de1239164ae4) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: Fix VFCT bus number matching with soft filterMario Limonciello
On systems where PCI bus renumbering occurs (e.g. pci=realloc, resource conflicts), the runtime bus number may differ from the BIOS POST bus number recorded in the VFCT table. This causes amdgpu_acpi_vfct_bios() to fail finding the VBIOS even though the correct device entry exists. Introduce amdgpu_acpi_vfct_match() which treats the bus number as a soft filter: vendor/device/function identity is the hard requirement, while exact bus match is the preferred path. When bus numbers disagree but device identity matches, accept the VFCT entry and log a dev_notice for diagnostics. Reported-by: Oz Tiram <oz@shift-computing.de> Closes: https://lore.kernel.org/amd-gfx/20260621173211.28443-1-oz@shift-computing.de/ Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260708193518.702584-2-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 11c141672045ffc0187aa604f2c0f597bc334fb2) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu: fix bo->pin leaking in amdgpu_bo_create_reservedZhu Lingshan
amdgpu_bo_create_reserved() only allocates a new BO when *bo_ptr (struct amdgpu_bo **bo_ptr as input parameter) is NULL, it simply skips creation when *bo_ptr is non-NULL. But it unconditionally reserves, pins, gart allocates and maps the BO afterwards. When the same non-NULL BO pointer is passed in again, for example firmware buffers that live in adev and are re-loaded on every resume / cp_resume / start under AMDGPU_FW_LOAD_DIRECT, amdgpu_bo_pin() just increases pin_count unconditionally, however the matching teardown only unpins once, so pin_count never drops to zero, so TTM is not able to move, swap or evict a BO, causing BO leaks. This commit fixes this issue by only pinning the bo once at creation, and repeated calls no longer take additional pin references. Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 3ddc0ae76202c447b6aec61e907b852bc94671cf) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu/userq: fix indefinite fence wait during GPU resetJesse Zhang
pre_reset only force-completes fences of MAPPED queues. A queue in any other state (e.g. mid-eviction) keeps its last_fence pending; after a GPU reset that fence never signals, so the eviction/suspend worker and process teardown (amdgpu_evf_mgr_flush_suspend) wait on it forever and wedge the machine: INFO: task kworker/6:28 blocked for more than 120 seconds. Workqueue: events amdgpu_eviction_fence_suspend_worker [amdgpu] Call Trace: dma_fence_wait_timeout+0x7e/0x130 amdgpu_userq_evict+0x67/0x140 [amdgpu] amdgpu_eviction_fence_suspend_worker+0xd8/0x160 [amdgpu] process_scheduled_works+0xa6/0x420 Force-complete every queue's fence regardless of state. The unmap and mark-hung step stays gated on MAPPED, since unmapping a queue that is not mapped is invalid. Fixes: 290f46cf5726 ("drm/amdgpu: Implement user queue reset functionality") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 9102b39fa924dcc3dc75a3137bfa9633c40b88c0) Cc: stable@vger.kernel.org
2026-07-17drm/amdgpu/discovery: Fix device family for DCN42Roman Li
GC 11.7.0 and 11.7.1 should map to AMDGPU_FAMILY_GC_11_5_4 for DCN42. Fixes: cf591e67c095 ("drm/amdgpu: add support for GC IP version 11.7.0") Fixes: a928d8d81ec5 ("drm/amdgpu: add support for GC IP version 11.7.1") Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit f8ee6447e7ec1d75d6663c817e45566dd01f440b)
2026-07-16drm/amdgpu: dont pin wptr bo instead use eviction fenceSunil Khatri
Instead of pinning the wptr bo attach the eviction fence to the bo to make sure it remains valid all the time. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: Use just sriov capability bit for xgmi ext peer link supportWill Aitken
The legacy xgmi ta without EXTEND_PEER_LINKS support in sriov still reports it as enabled. It then fails when the command is called. Rely on the host capability bit instead. v2: Replace other instances of supports_ext_link_info with this method. Including sysfs emission for xgmi_port_num. Now amd-smi xgmi --metric will output N/A for all cells when port_nums cannot be mapped in sriov Signed-off-by: Will Aitken <will.aitken@amd.com> Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: use correct gfp_t for job allocationChristian König
For job allocation in GPU reset and page fault handling we must use GFP_ATOMIC to guarantee that we don't cycle back and depend on a dma_fence submission for the memory allocation. Add gfp_flags argument to amdgpu_job_alloc() and expose the gfp_flags of IB pools with amdgpu_ib_pool_gfp_flags() so that we can use different flags when allocating jobs. Assisted-by: Claude:Sonnet 4 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: move job parameter to the end in amdgpu_job_alloc() and *_with_ib()Christian König
Move the job output parameter to be the last parameter in the amdgpu_job_alloc() and amdgpu_job_alloc_with_ib() function signature. This aligns with the common kernel coding convention where output parameters typically come last. Assisted-by: Claude:Sonnet 4 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: add gfp_flags to amdgpu_sa_manager v2Christian König
Make sure that we use the emmergency reserves for unrecoverable page faults and GPU resets. v2: improve code comments a bit based on Timur's feedback Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: give different sizes for each SA pool typeChristian König
The IMMEDIATE (page fault) and DIRECT (reset) pool should be used only very rarely and by a single thread. Saves roughly 1.25MiB of memory and GART space for each amdgpu device. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu: properly account for resets with user queuesAlex Deucher
We need to increment the reset counter, force fence completion, and set the wedged event when a user queue is reset, but only for the guilty queue. We don't want additional events for collateral damage. Only increment the reset counter and set the wedged event in the top level userq reset callers (both KGD and KFD). This aligns with how this is managed for kernel queue resets. v2: fix task info refcount handling, align with kfd error reporting. v3: check for has_reset_queue in KFD path (Prike) Cc: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Cc: Prike Liang <Prike.Liang@amd.com> Cc: Sunil Khatri <sunil.khatri@amd.com> Cc: Lazar, Lijo <lijo.lazar@amd.com> Reviewed-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu/gfx9.4.3: Fix MEC rollback loop in EOP IRQ setupSrinivasan Shanmugam
Fix the error cleanup path in gfx_v9_4_3_set_userq_eop_interrupts() by using the correct loop condition. This ensures all previously enabled EOP IRQs are released if setup fails. Fixes: 832f0aa050ff ("drm/amdgpu/gfx9.4.3: add support for disabling kernel queues") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Kent Russell <kent.russell@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-16drm/amdgpu : update mmhub eco sec lvl for vcn5_3Suresh Guttula
This patch requests PSP to set the sec lvl for vcn and jpeg. Signed-off-by: Suresh Guttula <suresh.guttula@amd.com> Reviewed-by: McRae Geoffrey<Geoffrey.McRae@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amdgpu: add mes gang contex alloc/free helperPrike Liang
Implement the MES gang contex alloc and free heplers. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amd: Move dynamic PCIe switching quirks to X86_MATCH_* macrosMario Limonciello
Use the X86_MATCH_VENDOR_FAM() and X86_MATCH_VENDOR_FAM_MODEL() macros to make the quirks for dynamic speed switching more scalable. Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260713172431.1599801-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amdgpu/ttm: Consider concurrent VM flushes for buffer entitiesTimur Kristóf
Allow using multiple SDMA schedulers only on GPUs where we are allowed to do concurrent VM flushes. This consideration is necessary because all GART windows are mapped in VMID 0 (the kernel VMID) so each buffer entity would flush VMID 0 concurrently. Practically this means that we can't use multiple SDMA engines for TTM on GFX6-8 and Navi 1x. Fixes: 01c836788b37 ("drm/amdgpu: pass all the sdma scheds to amdgpu_mman") Fixes: e4029f7a9474 ("drm/amdgpu: only use working sdma schedulers for ttm") Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amdgpu: debugfs: avoid extra EOLs in amdgpu_gem_infoMichał Mirosław
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amd/amdgpu/cgs: Avoid redundant copying of firmware filenameMichał Mirosław
While at it, remove redundant error message - request_firmware() will log a failure anyway. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amd/ras: initialize CPER after XGMI reset on initXiang Liu
The XGMI reset-on-init path can run while the device is still at the minimal init level, such as during an NPS memory partition switch. In that flow the normal RAS IP block hw_init is skipped, so unified RAS is not enabled when the early CPER initialization is attempted, leaving CPER disabled for the rest of the device's lifetime. Resume RAS after the XGMI reset-on-init completes. Once the RAS manager resume succeeds, the RAS resume wrapper performs deferred CPER initialization, keeping the path a no-op for devices where CPER was already initialized. Keep the deferred CPER retry and its debugfs registration together in the CPER helper. The normal debugfs ring walk skips the CPER ring until CPER is enabled, so the ring debugfs entry is created either by the deferred helper when debugfs is already available or by the normal debugfs walk. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Xiang Liu <xiang.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amdgpu: Fix IP block NULL check during soft resetTimur Kristóf
We can't print the IP block name when the IP block is NULL. Note that it should never be NULL, the only way that can happen is when amdgpu_ip_from_ring() is missing the given ring type. The check is just there to be sure. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <error27@gmail.com> Closes: https://lore.kernel.org/r/202607031711.yLwFhGfp-lkp@intel.com/ Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-15drm/amdgpu: Inline drm_simple_encoder_init()Nicolás Antinori
Simple KMS helpers are deprecated because they introduce an unnecessary intermediate layer between atomic modesetting and the DRM driver. Inline the functionality of drm_simple_encoder_init() to remove dependencies on these deprecated helpers. Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Nicolás Antinori <nico.antinori.7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>