summaryrefslogtreecommitdiff
path: root/arch/riscv
AgeCommit message (Collapse)Author
3 daysriscv/sifive: remove warning in errataYong-Xuan Wang
The alternative patching of sifive vendor extensions also calls the sifive_errata_patch_func(), but the patch_id of the vendor extension (ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE) is always larger than ERRATA_SIFIVE_NUMBER. Remove this unnecessary warning. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Link: https://patch.msgid.link/20260503-sifive_errata-v1-1-6f12a81bc267@sifive.com [pjw@kernel.org: drop unnecessary braces] Signed-off-by: Paul Walmsley <pjw@kernel.org>
3 daysriscv: time: Add missing __iomem in get_cycles() and get_cycles_hi()Nam Cao
__iomem is missing while calling readl_relaxed() in get_cycles() and get_cycles_hi() and sparse complains. Add __iomem to silence the sparse warnings. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202607160619.14G8GHp5-lkp@intel.com/ Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://patch.msgid.link/20260716053319.2178937-1-namcao@linutronix.de Signed-off-by: Paul Walmsley <pjw@kernel.org>
3 daysMerge branch 'soc/dt' into for-nextArnd Bergmann
* soc/dt: (27 commits) arm64: dts: socfpga: use consistent QSPI boot partition label riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions riscv: dts: thead: Add IO labels for the IO expansion on I2C1 riscv: dts: thead: lpi4a: sort nodes riscv: dts: thead: Add TH1520 I2C nodes riscv: dts: thead: th1520: remove pclk for I2C1 arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries arm64: dts: realtek: Add GPIO support for RTD1625 arm64: dts: realtek: Add EL2 virtual timer interrupt MAINTAINERS: Add entry for Samsung Exynos8855 SoC arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk dt-binding: ARM: samsung: Add Samsung Exynos8855 ARM: dts: rockchip: Add Alientek DLRV1126 ARM: dts: rockchip: Add RV1126 I2C5 dt-bindings: arm: rockchip: Add Alientek DLRV1126 dt-bindings: vendor-prefixes: add alientek ARM: dts: rockchip: add eeprom node to rk3288-tinker ARM: dts: intel: arria10: Correct indentation arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 ...
3 daysMerge tag 'thead-dt-for-v7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt T-HEAD device tree changes for v7.3 There is just one set of changes that the remaining IO expansion chips on the TH1520-based LicheePi 4a board. * tag 'thead-dt-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions riscv: dts: thead: Add IO labels for the IO expansion on I2C1 riscv: dts: thead: lpi4a: sort nodes riscv: dts: thead: Add TH1520 I2C nodes riscv: dts: thead: th1520: remove pclk for I2C1 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 daysriscv/runtime-const: Introduce runtime_const_mask_32()K Prateek Nayak
Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. Since all the current use-cases are of the form GENMASK(n, 0), with n > 0, following sequence: srli a0, a1, imm slli a0, a0, imm is used for RISC-V where imm = (31 - width) to improve instruction density and performance. "The RISC-V Instruction Set Manual, Volume I - Unprivileged Architecture" [1] Sec. 2.4.1 "Integer Register-Immediate Instructions" notes the immediate shift for SRLI and SLLI are 5 bits wide starting at bit #10. __runtime_fixup_shift() is reused to patch the immediate shifts for the two instructions. If a future use case arises that needs to tackle arbitrary mask, consider using: lui a0, 0x12346 # upper; +0x800 then >>12 for correct rounding addi a0, a0, 0x678 # lower 12 bits to patch the 32-bit mask in the asm block and return "__ret & (val)" from runtime_const_mask_32() which allows compiler to further optimize the logical and operation. __runtime_fixup_ptr() already patches a lui + addi sequence which can be reused when the need arises. A possible implementation for this alternate scheme can be found at [2]. Suggested-by: Samuel Holland <samuel.holland@sifive.com> Suggested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf [1] Link: https://lore.kernel.org/lkml/20260430094730.31624-6-kprateek.nayak@amd.com/ [2] Link: https://patch.msgid.link/20260728052540.4728-6-kprateek.nayak@amd.com
4 daysriscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on ↵Inochi Amaoto
K3 com260 board Since the previous commit does not change the phy node name, the dtschema can not recognize the type of the ethernet phy, so the following error is produced: /arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml /arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', ' reset-deassert-us', 'reset-gpios' were unexpected) from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml Change the nodename to make the dtschema can recognize the right PHY type. Fixes: 9db839d52ccd ("riscv: dts: spacemit: Fix phy id check for the phy on com260 board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260729012418.154652-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
4 daysriscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on ↵Inochi Amaoto
K3 pico-itx board Since the previous commit does not change the phy node name, the dtschema can not recognize the type of the ethernet phy, so the following error is produced: /arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml /arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', 're set-deassert-us', 'reset-gpios' were unexpected) from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml Change the nodename to make the dtschema can recognize the right PHY type. Fixes: 6d6536c880fe ("riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260729012418.154652-1-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
4 daysriscv: dts: sophgo: Add Milk-V Duo 256M board supportChen-Yu Yeh
The Milk-V Duo 256M is a small form factor development board based on the Sophgo SG2002 SoC. This patch adds basic device tree support for the board, including: - UART console - SD/MMC controller - USB host - Onboard blue status LED (connected to PWR_GPIO[2] / porte 2) Tested on actual Milk-V Duo 256M hardware, verified boot to shell and heartbeat LED functionality. Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com> Link: https://patch.msgid.link/20260725175346.139173-4-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
4 daysriscv: dts: sophgo: cv180x: Add PWR_GPIO controllerChen-Yu Yeh
The CV180x/CV181x family has an additional DesignWare APB GPIO controller (PWR_GPIO) located in the always-on power domain at 0x5021000. Add the node so that boards can reference GPIOs in this bank, such as status LEDs. Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com> Link: https://patch.msgid.link/20260725175346.139173-3-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
4 daysriscv64: dts: sophgo: add initial Milk-V Duo S board supportJoshua Milas
This adds initial riscv support for the Milk-V Duo S board [1] making it possible to boot Linux to the command line. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas <josh.milas@gmail.com> Link: https://milkv.io/duo-s [1] Link: https://patch.msgid.link/20260615120324.1527881-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> # Trim empty line Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
4 daysriscv64: dts: sophgo: add SG2000 dtsiJoshua Milas
Adds sg2000.dtsi on the RISCV side. Signed-off-by: Joshua Milas <josh.milas@gmail.com> Tested-by: Gui-Dong Han <hanguidong02@gmail.com> Reviewed-by: Gui-Dong Han <hanguidong02@gmail.com> Link: https://patch.msgid.link/20260615120324.1527881-3-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
4 daysriscv: dts: spacemit: k3: add i2s0-i2s5 nodesTroy Mitchell
Add the six SSPA-based I2S controller nodes for the K3 SoC. i2s0 and i2s2-i2s5 each have a dedicated per-controller sysclk divider, so they use the published 7-clock layout (sysclk, bclk, bus, func, sysclk_div, c_sysclk, c_bclk). i2s1 uses 6 clocks (sysclk, bclk, bus, func, c_sysclk, c_bclk) because its sysclk is driven directly by a DDN (ISCCR0) and has no separate divider stage. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260721-kx-i2s-dts-v1-3-d22cb6cfaab5@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@kernel.org>
4 daysriscv/mm: use physical alignment for vmemmap_start_pfnJiakai Xu
RISC-V computes vmemmap_start_pfn by rounding phys_ram_base down to VMEMMAP_ADDR_ALIGN. That alignment must therefore be expressed in the physical-address domain. Commit 476849b0fba4 ("riscv/mm: align vmemmap to maximal folio size") attempted to account for the maximal folio alignment by feeding MAX_FOLIO_VMEMMAP_ALIGN directly into VMEMMAP_ADDR_ALIGN. However, MAX_FOLIO_VMEMMAP_ALIGN is measured in bytes of struct page storage, whereas VMEMMAP_ADDR_ALIGN is used to align a physical address. The mask-based compound_info encoding requires pfn_to_page(0) to be naturally aligned to MAX_FOLIO_VMEMMAP_ALIGN. Commit 9f94db4c7eaa ("mm/sparse: check memmap alignment for compound_info_has_mask()") added a check for that requirement and exposed the unit mismatch on systems such as QEMU virt, where the DRAM base is not aligned to MAX_FOLIO_NR_PAGES * PAGE_SIZE. Here is the log: [ 0.000000][ C0] ------------[ cut here ]------------ [ 0.000000][ C0] WARNING: mm/sparse.c:365 at sparse_init+0x58a/0x6fe, CPU#0: swapper/0 [ 0.000000][ C0] Modules linked in: [ 0.000000][ C0] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 7.2.0-rc3-g1d8304bdd65f #2 PREEMPT [ 0.000000][ C0] Hardware name: riscv-virtio,qemu (DT) [ 0.000000][ C0] epc : sparse_init+0x58a/0x6fe [ 0.000000][ C0] ra : sparse_init+0x58a/0x6fe [ 0.000000][ C0] epc : ffffffff86851c88 ra : ffffffff86851c88 sp : ffffffff88807a30 [ 0.000000][ C0] gp : ffffffff8a3bf240 tp : ffffffff88842080 t0 : ff600000ffab6000 [ 0.000000][ C0] t1 : 000000017fab6000 t2 : 65203a6573726363 s0 : ffffffff88807bc0 [ 0.000000][ C0] s1 : 000000000e000000 a0 : 0000000000000007 a1 : 0000000000000000 [ 0.000000][ C0] a2 : 0000000000000002 a3 : ffffffff86851c88 a4 : 0000000000000000 [ 0.000000][ C0] a5 : ffffffff88843080 a6 : 0000000000000003 a7 : 0000000000000000 [ 0.000000][ C0] s2 : ff60000000000000 s3 : 0040000000000000 s4 : 0004000000000000 [ 0.000000][ C0] s5 : ffffffff8a4d92e0 s6 : ff600000ffab55e0 s7 : ffffffff88384d00 [ 0.000000][ C0] s8 : 0000000000000003 s9 : ffffffff88384cc1 s10: ffffffff88384cc0 [ 0.000000][ C0] s11: ffffffff8a4daae0 t3 : ffffffff915e8b20 t4 : ffffffff915e8b20 [ 0.000000][ C0] t5 : ffffffff915e8b20 t6 : ffffffff915e8bc8 ssp : 0000000000000000 [ 0.000000][ C0] status: 0000000200000100 badaddr: ffffffff86851c88 cause: 0000000000000003 [ 0.000000][ C0] [<ffffffff86851c88>] sparse_init+0x58a/0x6fe [ 0.000000][ C0] [<ffffffff8683d396>] mm_core_init_early+0x116/0x1e30 [ 0.000000][ C0] [<ffffffff86801edc>] start_kernel+0xd2/0x848 Convert MAX_FOLIO_VMEMMAP_ALIGN to the equivalent physical alignment before using it in VMEMMAP_ADDR_ALIGN. This keeps the existing round_down() logic while making the resulting vmemmap base satisfy the mask-alignment requirement. Link: https://lore.kernel.org/20260716115326.3466926-1-xujiakai2025@iscas.ac.cn Fixes: 476849b0fba4 ("riscv/mm: align vmemmap to maximal folio size") Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Reviewed-by: Kiryl Shutsemau (Meta) <kas@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: David Hildenbrand <david@kernel.org> Cc: Guo Ren <guoren@kernel.org> Cc: Mike Rapoport <rppt@kernel.org> Cc: Muchun Song <muchun.song@linux.dev> Cc: Nam Cao <namcao@linutronix.de> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Vishal Moola (Oracle) <vishal.moola@gmail.com> Assisted-by: YuanSheng:DeepSeek-V4-Flash Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
4 daysriscv: dts: starfive: jh7110-common: fix jh7110 SoC boot from SD-card.Ilya Sorochan
Add bootph-pre-ram to mmc1_pins clk-pins. U-Boot pruned their overrides recently in favor of Linux which broke booting from sd-card for me and Heinrich Schuchardt [1]. Pruning commit: 27f617019dd070cb61f2 ("riscv: dts: starfive: prune redundant jh7110-common overrides") [1] https://lore.kernel.org/all/ffdfc550-559b-4c59-9873-3f040fc3bb0e@canonical.com/ Signed-off-by: Ilya Sorochan <k0tran@altlinux.org> Signed-off-by: Conor Dooley <mail@conchuod.ie>
5 daysriscv: dts: spacemit: k3: add USB controller and USB phy supportInochi Amaoto
Add all USB device node to the Spacemit K3. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260727094726.890179-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
5 daysriscv/runtime-const: Replace open-coded placeholder with RUNTIME_MAGICK Prateek Nayak
Define the placeholder used for lui + addi[w] patching sequence as RUNTIME_MAGIC and use that instead of open coding the constants in the inline assembly. No functional changes intended. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Guo Ren <guoren@kernel.org> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://patch.msgid.link/20260728052540.4728-5-kprateek.nayak@amd.com
6 daysMerge branch 'acpi-irqchip' into linux-nextRafael J. Wysocki
* acpi-irqchip: irqchip/gic-v5: Enable GICv5 IWB ACPI probe ordering detection ACPI/IORT: Implement ACPI infrastructure to enable GICv5 IWB probe deferral ACPI: irq: Move RISC-V interrupt controllers autodep to ACPI IRQ code ACPI: RISC-V: Fix riscv_acpi_add_prt_dep() loop handling ACPI: RISC-V: Check acpi_get_handle() status in riscv_acpi_add_prt_dep() ACPI: RISC-V: Fix riscv_acpi_irq_get_dep() loop termination ACPI: Add acpi_device_clear_deps() helper function
7 daysriscv: dts: spacemit: enable PCIe on OrangePi R2SChukun Pan
Enable the two RTL8125 network controllers and corresponding PHYs connected via the PCIe controllers on the OrangePi R2S. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260602100000.2402784-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1Jennifer Berringer
Enable i2c1 for k3-com260-ifx and use it for a 24c02 eeprom. This eeprom, unlike the one connected to i2c2, is part of the carrier board. Some boards do not have any data programmed on this eeprom from factory. Signed-off-by: Jennifer Berringer <jberring@redhat.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260722202848.1817988-3-jberring@redhat.com Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: k3-com260: add eeprom on i2c2Jennifer Berringer
Enable i2c2 on the K3 CoM260 compute module and use it for a 24c02 eeprom. This eeprom stores the product name, a MAC address, and a serial number. Signed-off-by: Jennifer Berringer <jberring@redhat.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260722202848.1817988-2-jberring@redhat.com Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: add SPI controllers for K3Zhengyu He
Add the SPI controller nodes for K3. Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-3-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: add K3 PDMA request numbersliyeshan
Add a local DTS header that gives symbolic names to the SpacemiT K3 PDMA request lines of the non-secure peripherals. Device trees can use these K3_PDMA_* macros instead of hard-coded request numbers when wiring a peripheral "dmas" property. Signed-off-by: liyeshan <yeshan.li@spacemit.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-1-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: Fix phy id check for the phy on com260 boardInochi Amaoto
Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board com260 manually so the phy id dectection can be skipped. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260725233351.55004-3-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
7 daysriscv: dts: spacemit: Fix phy id check for the phy on pico-itx boardInochi Amaoto
Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board pico-itx manually so the phy id detection can be skipped. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Reported-by: E Shattow <e@freeshell.de> Reported-by: Inochi Amaoto <inochiama@gmail.com> Closes: https://lore.kernel.org/netdev/20260712045233.800748-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Tested-by: E Shattow <e@freeshell.de> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260725233351.55004-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
8 daysMerge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf 7.2-rc5Eduard Zingerman
Cross-merge BPF and other fixes after downstream PR. Conflicts: net/core/filter.c Changes [2] in bpf-next conflict with a recent fix [1] from the 'net' tree. Resolved by using [1] as a base and applying same flags handling logic as in [2] in the bpf_redirect_peer() helper. [1] https://lore.kernel.org/all/20260706185609.330006-2-daniel@iogearbox.net/ [2] https://lore.kernel.org/all/20260618182035.43811-2-jordan@jrife.io/ Signed-off-by: Eduard Zingerman <eddyz87@gmail.com>
8 daysriscv: dts: spacemit: Add enough deassert time for the PHY on com260 boardInochi Amaoto
RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://patch.msgid.link/20260710063314.1030249-2-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
8 daysriscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITXInochi Amaoto
RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Tested-by: E Shattow <e@freeshell.de> Link: https://patch.msgid.link/20260710063314.1030249-1-inochiama@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
8 daysbpf, riscv: Add support for timed may_gotoFeng Jiang
Implement arch_bpf_timed_may_goto() for the RV64 JIT. The argument and return value are carried in BPF_REG_AX, and BPF R0-R5 are preserved across the call to the generic bpf_check_timed_may_goto(). Enable bpf_jit_supports_timed_may_goto() so the verifier uses the timed expansion path. Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn> Reviewed-by: Pu Lehui <pulehui@huawei.com> Reviewed-by: Björn Töpel <bjorn@kernel.org> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/bpf/20260723-riscv-bpf-timed-may-goto-v5-1-86acb54e5642@kylinos.cn Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
8 daysMerge branch 'soc/defconfig' into for-nextArnd Bergmann
* soc/defconfig: riscv: defconfig: thead: enable PCA953X GPIO driver
8 daysMerge branch 'soc/dt' into for-nextArnd Bergmann
* soc/dt: ARM: dts: ixp4xx: Drop the reg-offset hack riscv: dts: canaan: Add clock definition for K230 riscv: dts: canaan: add reset controller for K230 riscv: dts: canaan: k230: Add "b" ISA extension riscv: dts: canaan: Add k230's pinctrl node riscv: dts: canaan: Correct the formatting issues about k230 dts riscv: dts: add initial canmv-k230 and k230-evb dts dt-bindings: interrupt-controller: Add Canaan K230 PLIC dt-bindings: timer: Add Canaan K230 CLINT dt-bindings: add Canaan K230 boards compatible strings
8 daysMerge tag 'riscv-dt-for-v7.3-early-k230' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V devicetrees for v7.3 - early k230 material Canaan: Support for the k230 SoC that was too late for the 7.2 window. Consists of some bindings not taken by the various subsystem maintainers, the original dts patches from Yangyu back in 2024 and the more recent clock, reset and pinctrl additions from various contributors. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: canaan: Add clock definition for K230 riscv: dts: canaan: add reset controller for K230 riscv: dts: canaan: k230: Add "b" ISA extension riscv: dts: canaan: Add k230's pinctrl node riscv: dts: canaan: Correct the formatting issues about k230 dts riscv: dts: add initial canmv-k230 and k230-evb dts dt-bindings: interrupt-controller: Add Canaan K230 PLIC dt-bindings: timer: Add Canaan K230 CLINT dt-bindings: add Canaan K230 boards compatible strings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
8 daysMerge tag 'riscv-config-for-v7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/defconfig RISC-V defconfig changes for 7.3 Enable PCA953X GPIO driver to properly probe Wifi pwrseq driver on the Sipeed Lichee Pi 4a board which is based on the T-HEAD TH1520 SoC. * tag 'riscv-config-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: riscv: defconfig: thead: enable PCA953X GPIO driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
10 daysriscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number ↵Inochi Amaoto
for DMA controller Change the DMA controller compatible to the sophgo,cv1800b-axi-dma, which supports setting DMA channel number in DMA phandle args. This dts change does not break backward compatibility as a fallback compatiable string is added. Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller") Reported-by: Anton D. Stavinskii <stavinsky@gmail.com> Closes: https://github.com/sophgo/linux/issues/9 Tested-by: Anton D. Stavinskii <stavinsky@gmail.com> Link: https://patch.msgid.link/20260511063818.463877-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
10 daysriscv: dts: thead: Add remaining Lichee Pi 4A IO expansionsEmil Renner Berthing
Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the I2C0/1/3 busses. The I2C1 one is already added to the device tree, but the I2C0/3 ones are not yet added. Add device tree nodes for them. Link: https://lore.kernel.org/r/20260714074515.1959352-6-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [Icenowy: added commit description, enable SoC pull-up, remove I2C1 and aliases] Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Drew Fustini <fustini@kernel.org>
10 daysriscv: dts: thead: Add IO labels for the IO expansion on I2C1Emil Renner Berthing
Add labels for GPIOs on the IO expansion chip on the I2C1 bus. Link: https://lore.kernel.org/r/20260714074515.1959352-5-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [Icenowy: Splitted off the patch adding all 3 IO expansions] Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> [fustini: align ioexp2 gpio-line-names with schematic] Signed-off-by: Drew Fustini <fustini@kernel.org>
10 daysriscv: dts: thead: lpi4a: sort nodesIcenowy Zheng
Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU, HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A device tree; in addition the PADCTRL1 node is placed before the PADCTRL0 one. Sort the nodes in this device tree. Link: https://lore.kernel.org/r/20260714074515.1959352-4-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Drew Fustini <fustini@kernel.org>
10 daysriscv: dts: thead: Add TH1520 I2C nodesThomas Bonnefille
Add nodes for the remaining five I2C controllers on the T-Head TH1520 RISCV SoC. Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> [Icenowy: rebase and reword commit message to exclude I2C1] Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Drew Fustini <fustini@kernel.org>
10 daysriscv: dts: thead: th1520: remove pclk for I2C1Icenowy Zheng
The I2C1 node added previously to the th1520.dtsi file has two clocks set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK). However, the CLK_I2C1 clock is just a clock gate with the CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated, reading registers from the I2C controller returns fixed value (the last read value) for all registers. These facts indicate that the CLK_I2C1 clock is the true APB clock fed into the I2C controller instead of a dedicated reference clock. Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1 device node and remove `clock-names` property, which represents the I2C controller only takes a single clock both as the APB clock and the reference clock. Fixes: 2f60e3516330 ("riscv: dts: thead: Add TH1520 I2C1 controller") Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Drew Fustini <fustini@kernel.org> Link: https://lore.kernel.org/r/20260714074515.1959352-2-zhengxingda@iscas.ac.cn Signed-off-by: Drew Fustini <fustini@kernel.org>
10 daysriscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO boardJunhui Liu
The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with an IO carrier board. The core module integrates the SpacemiT K1 SoC, PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion IO carrier board extends it by providing the eth1 PHY and exposing standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A ports, a USB Type-C port, two PCIe M.2 slots, and a serial console. The board also has two I2C EEPROMs. One is on the core module, which stores factory manufacturing data and is marked read-only. The other is on the carrier board, which is shipped unprogrammed and left writable for evaluation purposes. Add initial support for UART console, eMMC, SD card, I2C, EEPROMs, PCIe, USB, and dual Ethernet interfaces. Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6 Reviewed-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Tested-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260712-bpi-cm6-v3-3-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: k1: Split gmac_clk_ref into independent pinctrl groupsJunhui Liu
The gmac_clk_ref signal is optional for the GMAC controller and is not strictly required for all hardware designs. The pins for gmac0_clk_ref (GPIO 45) and gmac1_clk_ref (GPIO 46) may also be used as GPIOs for other functions even when the Ethernet controller is active. Split the refclk pins into independent pinctrl groups so boards can request them only when the reference clock path is actually needed. Among the already mainlined boards, BPI-F3, Jupiter and MusePi Pro have optional hardware paths for the GMAC refclk pins. BPI-F3 and Jupiter route both GMAC refclk pins to the PHYs through NC/0R option resistors, while MusePi Pro only does so for GMAC0. Keep referencing the new clk-ref pinctrl groups on these boards so the optional hardware paths remain usable if the option resistors are populated. OrangePi R2S has no publicly available schematic, so also keep the clk-ref groups there to preserve the previous pinmux behavior. Fixes: 60775f28cfb7 ("riscv: dts: spacemit: Add Ethernet support for K1") Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260712-bpi-cm6-v3-2-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: Add cpu scaling for K1 SoCShuwei Wu
Add CPU clock properties and OPP tables for the two CPU clusters in the SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU supply is shared by both clusters. Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and wiring the CPU nodes to the CPU regulator supply. Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> Tested-by: Andre Heider <a.heider@gmail.com> # k1-musepi-pro Reviewed-by: Yixun Lan <dlan@kernel.org> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Milan P. Stanić <mps@arvanta.net> Tested-by: Gong Shuai <gsh517025@gmail.com> # OrangePi-RV2 Link: https://patch.msgid.link/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: k3: Add QSPI support for Pico-ITX boardZhengyu He
Enable QSPI with proper pinmux on the Pico-ITX board, and describe the NOR flash wired to it. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: improve RTL8211F PHY configuration on K3 Pico-ITX boardAurelien Jarno
Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the RTL8211F PHY to save power when link down. Vendor kernel also disabled the 125MHz clkout clock signal, and indeed the schematics confirms that it only goes to a test point (TP14), so let's do the same. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Yixun Lan <dlan@kernel.org> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260623204431.498700-6-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: add i2c aliases on K3 Pico-ITX boardAurelien Jarno
Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful to keep a stable number for the /dev entries after loading the i2c-dev module. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260623204431.498700-5-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: add 24c02 eeprom on K3 Pico-ITX boardAurelien Jarno
The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product name, the part name, the MAC address of the network interfaces and the board's serial number. These values are also exposed via an onie,tlv-layout nvmem layout. The eeprom is marked as read-only since its contents are not supposed to be modified. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260623204431.498700-4-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: enable the i2c2 adapter on K3 Pico-ITX boardAurelien Jarno
Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board. It will be used by the 24c02 eeprom. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260623204431.498700-3-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
10 daysriscv: dts: spacemit: set console baud rate on K3 Pico-ITX boardAurelien Jarno
Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. Fixes: 7a6131804986 ("riscv: dts: spacemit: add K3 Pico-ITX board support") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Guodong Xu <docular.xu@gmail.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260623204431.498700-2-aurelien@aurel32.net Signed-off-by: Yixun Lan <dlan@kernel.org>
11 daysriscv, bpf: Add 32 bit atomic operations to RV32 JITKuan-Wei Chiu
The RV32 BPF JIT compiler currently only supports the BPF_ADD atomic operation. Other 32 bit atomic operations (and, or, xor, xchg) and their BPF_FETCH variants are not supported and gracefully fall back to the interpreter. Since the RISC-V A extension is required for Linux on RV32, we can natively support these 32-bit BPF atomic operations by mapping them directly to the corresponding RISC-V amo*.w instructions. Implement BPF_ADD, BPF_AND, BPF_OR, BPF_XOR, and BPF_XCHG with and without BPF_FETCH. BPF_CMPXCHG requires a more complex lr.w/sc.w loop and is left to fall back to the interpreter. Before this patch: [ 138.862161] test_bpf: Summary: 1054 PASSED, 0 FAILED, [843/1042 JIT'ed] After this patch: [ 157.024124] test_bpf: Summary: 1054 PASSED, 0 FAILED, [902/1042 JIT'ed] Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/bpf/20260714002451.4091139-4-visitorckw@gmail.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
11 daysriscv, bpf: Add support for BPF_MOVSX in RV32 JITKuan-Wei Chiu
The current rv32 bpf jit compiler incorrectly treats BPF_MOVSX as a standard zero-extended move operation. The bpf instruction set allows sign-extension moves by reusing the BPF_MOV opcode with the instruction offset set to 8, 16, or 32. Update the bpf_jit_emit_insn() function to check the offset field for both ALU and ALU64 MOV operations. If the offset is non-zero, emit the correct slli and srai instructions to perform the sign extension. Before this patch: [ 19.549705] test_bpf: #82 ALU_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.551354] test_bpf: #83 ALU_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.552576] test_bpf: #84 ALU64_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.553542] test_bpf: #85 ALU64_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) [ 19.554807] test_bpf: #86 ALU64_MOVSX | BPF_W jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) After this patch: [ 17.931172] test_bpf: #82 ALU_MOVSX | BPF_B jited:1 125 PASS [ 17.932198] test_bpf: #83 ALU_MOVSX | BPF_H jited:1 124 PASS [ 17.933039] test_bpf: #84 ALU64_MOVSX | BPF_B jited:1 124 PASS [ 17.933918] test_bpf: #85 ALU64_MOVSX | BPF_H jited:1 124 PASS [ 17.934751] test_bpf: #86 ALU64_MOVSX | BPF_W jited:1 122 PASS Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/bpf/20260714002451.4091139-3-visitorckw@gmail.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
11 daysriscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JITKuan-Wei Chiu
The current rv32 bpf jit compiler incorrectly treats BPF_SDIV and BPF_SMOD as unsigned operations. The BPF instruction set allows signed division and modulo by reusing the BPF_DIV and BPF_MOD opcodes with the instruction offset set to 1. Update the emit_alu_r32() function to accept an 'is_sdiv' variable and emit the correct div and rem instructions when the offset is 1. Before this patch: [ 44.161771] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) [ 44.167385] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) [ 44.171053] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) [ 44.172081] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) After this patch: [ 16.002192] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 95 PASS [ 16.002983] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 1059 PASS [ 16.017167] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 136 PASS [ 16.023002] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 109 PASS Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/bpf/20260714002451.4091139-2-visitorckw@gmail.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>