From 501f72e9c5205b9d70d5d61e9b186ae7ba873f73 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 22 Dec 2015 18:27:56 +0000 Subject: ASoC: da7219: Remove support for 32KHz PLL mode PLL mode based on 32KHz master clock not supported in AB silicon so remove support from the driver. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7219.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'sound/soc/codecs/da7219.h') diff --git a/sound/soc/codecs/da7219.h b/sound/soc/codecs/da7219.h index 2b3f4471a17f..5a787e738084 100644 --- a/sound/soc/codecs/da7219.h +++ b/sound/soc/codecs/da7219.h @@ -206,7 +206,6 @@ #define DA7219_PLL_MODE_BYPASS (0x0 << 6) #define DA7219_PLL_MODE_NORMAL (0x1 << 6) #define DA7219_PLL_MODE_SRM (0x2 << 6) -#define DA7219_PLL_MODE_32KHZ (0x3 << 6) /* DA7219_PLL_FRAC_TOP = 0x22 */ #define DA7219_PLL_FBDIV_FRAC_TOP_SHIFT 0 @@ -780,7 +779,6 @@ enum da7219_sys_clk { DA7219_SYSCLK_MCLK = 0, DA7219_SYSCLK_PLL, DA7219_SYSCLK_PLL_SRM, - DA7219_SYSCLK_PLL_32KHZ }; /* Regulators */ -- cgit v1.2.3