From 439797980af4bddfc2b86a44ddb573c5e48a1fcc Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Thu, 21 Mar 2013 14:22:34 -0300 Subject: [media] exynos4-is: Correct input DMA YUV order configuration This patch fixes erroneous setup of the YUV order caused by not clearing FIMC_REG_MSCTRL_ORDER422_MASK bit field before setting proper FIMC_REG_MSCTRL_ORDER422 bits. This resulted in false colors for YUYV, YVYU, UYVY, VYUY color formats, depending in what sequence those were configured by user space. YUV order definitions are corrected so that following convention is used: | byte3 | byte2 | byte1 | byte0 -------+-------+-------+-------+------ YCBYCR | CR | Y | CB | Y YCRYCB | CB | Y | CR | Y CBYCRY | Y | CR | Y | CB CRYCBY | Y | CB | Y | CR Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/exynos4-is/fimc-reg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/media/platform/exynos4-is/fimc-reg.c') diff --git a/drivers/media/platform/exynos4-is/fimc-reg.c b/drivers/media/platform/exynos4-is/fimc-reg.c index c82e9bdaae94..f079f36099de 100644 --- a/drivers/media/platform/exynos4-is/fimc-reg.c +++ b/drivers/media/platform/exynos4-is/fimc-reg.c @@ -449,7 +449,8 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx) | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK | FIMC_REG_MSCTRL_INPUT_MASK | FIMC_REG_MSCTRL_C_INT_IN_MASK - | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK); + | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK + | FIMC_REG_MSCTRL_ORDER422_MASK); cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4) | FIMC_REG_MSCTRL_INPUT_MEMORY -- cgit v1.2.3