From 3e8d74cb128fb1a4d56270ffbecea6056c55739a Mon Sep 17 00:00:00 2001
From: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Date: Tue, 9 May 2023 14:41:59 -0400
Subject: drm/amd/display: Trigger DIO FIFO resync on commit streams
[WHY]
Currently, there is an intermittent issue where a screen can either go
blank or be corrupted.
[HOW]
To resolve the issue we trigger the ramping logic for DIO FIFO so that
it goes back up to the correct speed.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 3 +++
1 file changed, 3 insertions(+)
(limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index ad6acd1b34e1..0b700b3d7d97 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -159,6 +159,9 @@ struct dccg_funcs {
int otg_inst,
int pixclk_khz);
+ void (*trigger_dio_fifo_resync)(
+ struct dccg *dccg);
+
void (*dpp_root_clock_control)(
struct dccg *dccg,
unsigned int dpp_inst,
--
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