From 067d9fd7eed2bde170cba8ed12f49fb68c4e78ae Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Fri, 6 Sep 2024 16:31:11 +0530 Subject: dt-bindings: pinctrl: Add support for Xilinx Versal platform Add Xilinx Versal compatible string and corresponding groups, function and pins properties to support pin controller features on Versal platform. Signed-off-by: Sai Krishna Potthuri Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/20240906110113.3154327-2-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/xlnx,versal-pinctrl.yaml | 278 +++++++++++++++++++++ 1 file changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml new file mode 100644 index 000000000000..55ece6a8be5e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal Pinctrl + +maintainers: + - Sai Krishna Potthuri + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + Versal's pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, slew rate, etc. + + Each configuration node can consist of multiple nodes describing the pinmux and + pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +properties: + compatible: + const: xlnx,versal-pinctrl + +patternProperties: + '^(.*-)?(default|gpio-grp)$': + type: object + patternProperties: + '^mux': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + $ref: pinmux-node.yaml# + + properties: + pins: + description: + List of pins to select (either this or "groups" must be specified) + $ref: "#/$defs/pins/properties/pins" + + groups: + description: + List of groups to select (either this or "pins" must be + specified), available groups for this subnode. + anyOf: + - pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + - $ref: "#/$defs/pins/properties/groups" + + function: + description: + Specify the alternative function to be configured for the + given pin groups. + enum: [spi0, spi0_ss, spi1, spi1_ss, can0, can1, i2c0, i2c1, i2c_pmc, ttc0_clk, + ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, ttc3_clk, ttc3_wav, wwdt0, + wwdt1, sysmon_i2c0, sysmon_i2c0_alrt, uart0, uart0_ctrl, uart1, uart1_ctrl, + gpio0, gpio1, gpio2, emio0, gem0, gem1, trace0, trace0_clk, mdio0, mdio1, gem_tsu0, + pcie0, smap0, usb0, sd0, sd0_pc, sd0_cd, sd0_wp, sd1, sd1_pc, sd1_wp, sd1_cd, + ospi0, ospi0_ss, qspi0, qspi0_fbclk, qspi0_ss, test_clk, test_scan, tamper_trigger] + + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + '^conf': + type: object + description: + Pinctrl node's client devices use subnodes for pin configurations, + which in turn use the standard properties below. + allOf: + - $ref: pincfg-node.yaml# + - $ref: "#/$defs/pins" + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +$defs: + pins: + properties: + groups: + description: + List of pin groups to select in this subnode. + items: + enum: [spi0_0_grp, spi0_1_grp, spi0_2_grp, spi0_3_grp, spi0_4_grp, spi0_5_grp, + spi0_ss_0_grp, spi0_ss_1_grp, spi0_ss_2_grp, spi0_ss_3_grp, spi0_ss_4_grp, + spi0_ss_5_grp, spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, spi0_ss_9_grp, + spi0_ss_10_grp, spi0_ss_11_grp, spi0_ss_12_grp, spi0_ss_13_grp, spi0_ss_14_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, spi1_0_grp, spi1_1_grp, + spi1_2_grp, spi1_3_grp, spi1_4_grp, spi1_5_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_ss_3_grp, spi1_ss_4_grp, spi1_ss_5_grp, spi1_ss_6_grp, + spi1_ss_7_grp, spi1_ss_8_grp, spi1_ss_9_grp, spi1_ss_10_grp, spi1_ss_11_grp, + spi1_ss_12_grp, spi1_ss_13_grp, spi1_ss_14_grp, spi1_ss_15_grp, spi1_ss_16_grp + spi1_ss_17_grp, can0_0_grp, can0_1_grp, can0_2_grp, can0_3_grp, can0_4_grp, + can0_5_grp, can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp, can0_10_grp, + can0_11_grp, can0_12_grp, can0_13_grp, can0_14_grp, can0_15_grp, can0_16_grp, + can0_17_grp, can1_0_grp, can1_1_grp, can1_2_grp, can1_3_grp, can1_4_grp, + can1_5_grp, can1_6_grp, can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp, + can1_11_grp, can1_12_grp, can1_13_grp, can1_14_grp, can1_15_grp, can1_16_grp, + can1_17_grp, can1_18_grp, i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp, + i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, i2c0_8_grp, i2c0_9_grp, + i2c0_10_grp, i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, i2c0_14_grp, i2c0_15_grp, + i2c0_16_grp, i2c0_17_grp, i2c1_0_grp, i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, i2c_pmc_0_grp, i2c_pmc_1_grp, + i2c_pmc_2_grp, i2c_pmc_3_grp, i2c_pmc_4_grp, i2c_pmc_5_grp, i2c_pmc_6_grp, + i2c_pmc_7_grp, i2c_pmc_8_grp, i2c_pmc_9_grp, i2c_pmc_10_grp, i2c_pmc_11_grp, + i2c_pmc_12_grp, ttc0_clk_0_grp, ttc0_clk_1_grp, ttc0_clk_2_grp, ttc0_clk_3_grp, + ttc0_clk_4_grp, ttc0_clk_5_grp, ttc0_clk_6_grp, ttc0_clk_7_grp, ttc0_clk_8_grp, + ttc0_wav_0_grp, ttc0_wav_1_grp, ttc0_wav_2_grp, ttc0_wav_3_grp, ttc0_wav_4_grp, + ttc0_wav_5_grp, ttc0_wav_6_grp, ttc0_wav_7_grp, ttc0_wav_8_grp, ttc1_clk_0_grp, + ttc1_clk_1_grp, ttc1_clk_2_grp, ttc1_clk_3_grp, ttc1_clk_4_grp, ttc1_clk_5_grp, + ttc1_clk_6_grp, ttc1_clk_7_grp, ttc1_clk_8_grp, ttc1_wav_0_grp, ttc1_wav_1_grp, + ttc1_wav_2_grp, ttc1_wav_3_grp, ttc1_wav_4_grp, ttc1_wav_5_grp, ttc1_wav_6_grp, + ttc1_wav_7_grp, ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_clk_1_grp, ttc2_clk_2_grp, + ttc2_clk_3_grp, ttc2_clk_4_grp, ttc2_clk_5_grp, ttc2_clk_6_grp, ttc2_clk_7_grp, + ttc2_clk_8_grp, ttc2_wav_0_grp, ttc2_wav_1_grp, ttc2_wav_2_grp, ttc2_wav_3_grp, + ttc2_wav_4_grp, ttc2_wav_5_grp, ttc2_wav_6_grp, ttc2_wav_7_grp, ttc2_wav_8_grp, + ttc3_clk_0_grp, ttc3_clk_1_grp, ttc3_clk_2_grp, ttc3_clk_3_grp, ttc3_clk_4_grp, + ttc3_clk_5_grp, ttc3_clk_6_grp, ttc3_clk_7_grp, ttc3_clk_8_grp, ttc3_wav_0_grp, + ttc3_wav_1_grp, ttc3_wav_2_grp, ttc3_wav_3_grp, ttc3_wav_4_grp, ttc3_wav_5_grp, + ttc3_wav_6_grp, ttc3_wav_7_grp, ttc3_wav_8_grp, wwdt0_0_grp, wwdt0_1_grp, + wwdt0_2_grp, wwdt0_3_grp, wwdt0_4_grp, wwdt0_5_grp, wwdt1_0_grp, wwdt1_1_grp, + wwdt1_2_grp, wwdt1_3_grp, wwdt1_4_grp, wwdt1_5_grp, sysmon_i2c0_0_grp, + sysmon_i2c0_1_grp, sysmon_i2c0_2_grp, sysmon_i2c0_3_grp, sysmon_i2c0_4_grp, + sysmon_i2c0_5_grp, sysmon_i2c0_6_grp, sysmon_i2c0_7_grp, sysmon_i2c0_8_grp, + sysmon_i2c0_9_grp, sysmon_i2c0_10_grp, sysmon_i2c0_11_grp, sysmon_i2c0_12_grp, + sysmon_i2c0_13_grp, sysmon_i2c0_14_grp, sysmon_i2c0_15_grp, + sysmon_i2c0_16_grp, sysmon_i2c0_17_grp, sysmon_i2c0_alrt_0_grp, + sysmon_i2c0_alrt_1_grp, sysmon_i2c0_alrt_2_grp, sysmon_i2c0_alrt_3_grp, + sysmon_i2c0_alrt_4_grp, sysmon_i2c0_alrt_5_grp, sysmon_i2c0_alrt_6_grp, + sysmon_i2c0_alrt_7_grp, sysmon_i2c0_alrt_8_grp, sysmon_i2c0_alrt_9_grp, + sysmon_i2c0_alrt_10_grp, sysmon_i2c0_alrt_11_grp, sysmon_i2c0_alrt_12_grp, + sysmon_i2c0_alrt_13_grp, sysmon_i2c0_alrt_14_grp, sysmon_i2c0_alrt_15_grp, + sysmon_i2c0_alrt_16_grp, sysmon_i2c0_alrt_17_grp, uart0_0_grp, uart0_1_grp, + uart0_2_grp, uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp, uart0_7_grp, + uart0_8_grp, uart0_ctrl_0_grp, uart0_ctrl_1_grp, uart0_ctrl_2_grp, + uart0_ctrl_3_grp, uart0_ctrl_4_grp, uart0_ctrl_5_grp, uart0_ctrl_6_grp, + uart0_ctrl_7_grp, uart0_ctrl_8_grp, uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_ctrl_0_grp, uart1_ctrl_1_grp, uart1_ctrl_2_grp, uart1_ctrl_3_grp, + uart1_ctrl_4_grp, uart1_ctrl_5_grp, uart1_ctrl_6_grp, uart1_ctrl_7_grp, + uart1_ctrl_8_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp, + gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, gpio0_19_grp, + gpio0_20_grp, gpio0_21_grp, gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio1_0_grp, gpio1_1_grp, gpio1_2_grp, gpio1_3_grp, gpio1_4_grp, + gpio1_5_grp, gpio1_6_grp, gpio1_7_grp, gpio1_8_grp, gpio1_9_grp, + gpio1_10_grp, gpio1_11_grp, gpio1_12_grp, gpio1_13_grp, gpio1_14_grp, + gpio1_15_grp, gpio1_16_grp, gpio1_17_grp, gpio1_18_grp, gpio1_19_grp, + gpio1_20_grp, gpio1_21_grp, gpio1_22_grp, gpio1_23_grp, gpio1_24_grp, + gpio1_25_grp, gpio2_0_grp, gpio2_1_grp, gpio2_2_grp, gpio2_3_grp, gpio2_4_grp, + gpio2_5_grp, gpio2_6_grp, gpio2_7_grp, gpio2_8_grp, gpio2_9_grp, gpio2_10_grp, + gpio2_11_grp, gpio2_12_grp, gpio2_13_grp, gpio2_14_grp, gpio2_15_grp, + gpio2_16_grp, gpio2_17_grp, gpio2_18_grp, gpio2_19_grp, gpio2_20_grp, + gpio2_21_grp, gpio2_22_grp, gpio2_23_grp, gpio2_24_grp, gpio2_25_grp, + emio0_0_grp, emio0_1_grp, emio0_2_grp, emio0_3_grp, emio0_4_grp, emio0_5_grp, + emio0_6_grp, emio0_7_grp, emio0_8_grp, emio0_9_grp, emio0_10_grp, + emio0_11_grp, emio0_12_grp, emio0_13_grp, emio0_14_grp, emio0_15_grp, + emio0_16_grp, emio0_17_grp, emio0_18_grp, emio0_19_grp, emio0_20_grp, + emio0_21_grp, emio0_22_grp, emio0_23_grp, emio0_24_grp, emio0_25_grp, + emio0_26_grp, emio0_27_grp, emio0_28_grp, emio0_29_grp, emio0_30_grp, + emio0_31_grp, emio0_32_grp, emio0_33_grp, emio0_34_grp, emio0_35_grp, + emio0_36_grp, emio0_37_grp, emio0_38_grp, emio0_39_grp, emio0_40_grp, + emio0_41_grp, emio0_42_grp, emio0_43_grp, emio0_44_grp, emio0_45_grp, + emio0_46_grp, emio0_47_grp, emio0_48_grp, emio0_49_grp, emio0_50_grp, + emio0_51_grp, emio0_52_grp, emio0_53_grp, emio0_54_grp, emio0_55_grp, + emio0_56_grp, emio0_57_grp, emio0_58_grp, emio0_59_grp, emio0_60_grp, + emio0_61_grp, emio0_62_grp, emio0_63_grp, emio0_64_grp, emio0_65_grp, + emio0_66_grp, emio0_67_grp, emio0_68_grp, emio0_69_grp, emio0_70_grp, + emio0_71_grp, emio0_72_grp, emio0_73_grp, emio0_74_grp, emio0_75_grp, + emio0_76_grp, emio0_77_grp, gem0_0_grp, gem0_1_grp, gem1_0_grp, gem1_1_grp, + trace0_0_grp, trace0_1_grp, trace0_2_grp, trace0_clk_0_grp, trace0_clk_1_grp, + trace0_clk_2_grp, mdio0_0_grp, mdio0_1_grp, mdio1_0_grp, mdio1_1_grp, + gem_tsu0_0_grp, gem_tsu0_1_grp, gem_tsu0_2_grp, gem_tsu0_3_grp, pcie0_0_grp, + pcie0_1_grp, pcie0_2_grp, smap0_0_grp, usb0_0_grp, sd0_0_grp, sd0_1_grp, + sd0_2_grp, sd0_3_grp, sd0_4_grp, sd0_5_grp, sd0_6_grp, sd0_7_grp, sd0_8_grp, + sd0_9_grp, sd0_10_grp, sd0_11_grp, sd0_12_grp, sd0_13_grp, sd0_14_grp, + sd0_15_grp, sd0_16_grp, sd0_17_grp, sd0_18_grp, sd0_19_grp, sd0_20_grp, + sd0_21_grp, sd0_pc_0_grp, sd0_pc_1_grp, sd0_cd_0_grp, sd0_cd_1_grp, + sd0_wp_0_grp, sd0_wp_1_grp, sd1_0_grp, sd1_1_grp, sd1_2_grp, sd1_3_grp, + sd1_4_grp, sd1_5_grp, sd1_6_grp, sd1_7_grp, sd1_8_grp, sd1_9_grp, sd1_10_grp, + sd1_11_grp, sd1_12_grp, sd1_13_grp, sd1_14_grp, sd1_15_grp, sd1_16_grp, + sd1_17_grp, sd1_18_grp, sd1_19_grp, sd1_20_grp, sd1_21_grp, sd1_pc_0_grp, + sd1_pc_1_grp, sd1_cd_0_grp, sd1_cd_1_grp, sd1_wp_0_grp, sd1_wp_1_grp, + ospi0_0_grp, ospi0_ss_0_grp, qspi0_0_grp, qspi0_fbclk_0_grp, qspi0_ss_0_grp, + test_clk_0_grp, test_scan_0_grp, tamper_trigger_0_grp] + minItems: 1 + maxItems: 78 + + pins: + description: + List of pin names to select in this subnode. + items: + pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + minItems: 1 + maxItems: 78 + + bias-pull-up: true + bias-pull-down: true + bias-disable: true + input-schmitt-enable: true + input-schmitt-disable: true + bias-high-impedance: true + low-power-enable: true + low-power-disable: true + + slew-rate: + enum: [0, 1] + + output-enable: + description: + This will internally disable the tri-state for MIO pins. + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 8, 12] + + power-source: + enum: [0, 1] + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + +examples: + - | + #include + pinctrl { + compatible = "xlnx,versal-pinctrl"; + + uart0-default { + mux { + groups = "uart0_4_grp", "uart0_5_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "PMC_MIO42"; + bias-pull-up; + }; + + conf-tx { + pins = "PMC_MIO43"; + bias-disable; + input-schmitt-disable; + }; + }; + }; + +... -- cgit v1.2.3 From 88dbf374a5748c09e2a1eef3f3ad43cc73c6f69a Mon Sep 17 00:00:00 2001 From: Nikunj Kela Date: Thu, 5 Sep 2024 13:02:18 -0700 Subject: dt-bindings: pinctrl: Add SA8255p TLMM Add compatible for TLMM block representing support on SA8255p. SA8255p uses the same TLMM block as SA8775p however the ownership of pins are split between Firmware VM and Linux VM on SA8255p. For example, pins used by UART are owned and configured by Firmware VM while pins used by ethernet are owned and configured by Linux VM. Therefore, adding a sa8255p specific compatible to mark the difference. Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20240905200218.3810712-1-quic_nkela@quicinc.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml index e9abbf2c0689..749dbc563ac5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -17,7 +17,13 @@ allOf: properties: compatible: - const: qcom,sa8775p-tlmm + oneOf: + - items: + - enum: + - qcom,sa8255p-tlmm + - const: qcom,sa8775p-tlmm + - items: + - const: qcom,sa8775p-tlmm reg: maxItems: 1 -- cgit v1.2.3 From 01be3ac0ab77d4ffcd425aee05dc81d5d10117e2 Mon Sep 17 00:00:00 2001 From: Daniel Machon Date: Tue, 17 Sep 2024 14:45:40 +0200 Subject: dt-bindings: ocelot: document lan969x-pinctrl Lan969x is going to reuse the existing Ocelot pinctrl driver - document that by adding compatible strings for the different SKU's that we support. Signed-off-by: Daniel Machon Acked-by: Conor Dooley Link: https://lore.kernel.org/20240917-lan969x-pinctrl-v2-1-ea02cbc56831@microchip.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 27 +++++++++++++++------- 1 file changed, 19 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml index dbb3e1bd58c1..31bc30a81752 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -12,14 +12,24 @@ maintainers: properties: compatible: - enum: - - microchip,lan966x-pinctrl - - microchip,sparx5-pinctrl - - mscc,jaguar2-pinctrl - - mscc,luton-pinctrl - - mscc,ocelot-pinctrl - - mscc,serval-pinctrl - - mscc,servalt-pinctrl + oneOf: + - enum: + - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + - items: + - enum: + - microchip,lan9698-pinctrl + - microchip,lan9696-pinctrl + - microchip,lan9694-pinctrl + - microchip,lan9693-pinctrl + - microchip,lan9692-pinctrl + - const: microchip,lan9691-pinctrl reg: items: @@ -85,6 +95,7 @@ allOf: contains: enum: - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl - microchip,sparx5-pinctrl then: properties: -- cgit v1.2.3 From 137ca342ae2d6627496a871f5553ea023cfc77c0 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Mon, 30 Sep 2024 12:50:51 -0700 Subject: dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. Reviewed-by: Rob Herring (Arm) Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing [dfustini: add thead,pad-group to select the pin controller instance] Signed-off-by: Drew Fustini Link: https://lore.kernel.org/20240930-th1520-pinctrl-v3-1-32cea2bdbecb@tenstorrent.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 +++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..21f86740a63d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ranges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For most + pads only a few of those 6 configurations are valid though, and a few pads in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either can't + be configured or has some special functions. The rest have configurable drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and + are then meant to be used by the audio co-processor. Each such pad can then + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is + also configured in different registers. All of this is done from a different + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-pinctrl + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + thead,pad-group: + description: | + Select the pad group that is associated with the pin controller instance. + + Base Address Name Group + 0xFF_FFF4_A000 PADCTRL_AOSYS 1 + 0xFF_E7F3_C000 PADCTRL1_APSYS 2 + 0xFF_EC00_7000 PADCTRL0_APSYS 3 + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + description: List of pads that properties in the node apply to. + + function: + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +additionalProperties: false + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xec007000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <3>; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xe7f3c000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <2>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins = "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f..dd74c9aa2009 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19942,6 +19942,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h -- cgit v1.2.3 From b88752d3133b334fbad83a3d3fee5df9ad65e536 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 27 Sep 2024 12:22:38 +0530 Subject: dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl Add device tree bindings for IPQ5424 TLMM block. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/20240927065244.3024604-4-quic_srichara@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,ipq5424-tlmm.yaml | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml new file mode 100644 index 000000000000..5e64a232fc7a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5424 TLMM pin controller + +maintainers: + - Bjorn Andersson + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5424-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 25 + + gpio-line-names: + maxItems: 50 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5424-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5424-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5424-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9])$" + minItems: 1 + maxItems: 50 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1, + cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest, + gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11, + mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk, + pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, + pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11, + pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk, + qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd, + sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1, + wci_txd, wci_rxd, wsi_clk, wsi_data ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5424-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 50>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <0x2>; + + uart1_pins: uart1-state { + pins = "gpio43", "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; -- cgit v1.2.3 From 561f3e9d21a16df0148f5f209bdc26db3d86632b Mon Sep 17 00:00:00 2001 From: Ze Huang <18771902331@163.com> Date: Thu, 26 Sep 2024 23:57:43 +0800 Subject: dt-bindings: pinctrl: Add support for canaan,k230 SoC Add device tree binding details for Canaan K230 pinctrl device. Signed-off-by: Ze Huang <18771902331@163.com> Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/20240926-k230-pinctrl-v2-1-a9a36fba4b34@163.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/canaan,k230-pinctrl.yaml | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml new file mode 100644 index 000000000000..0b462eb6dfe1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Pin Controller + +maintainers: + - Ze Huang <18771902331@163.com> + +description: + The Canaan Kendryte K230 platform includes 64 IO pins, each capable of + multiplexing up to 5 different functions. Pin function configuration is + performed on a per-pin basis. + +properties: + compatible: + const: canaan,k230-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-cfg$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate enable/disable, + slew-rate, drive strength. + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in + the node apply to. This should be set with the macro + 'K230_PINMUX(pin, mode)' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + minimum: 0 + maximum: 15 + + input-enable: true + + output-enable: true + + input-schmitt-enable: true + + slew-rate: + description: | + slew rate control enable + 0: disable + 1: enable + + enum: [0, 1] + + power-source: + description: | + Specifies the power source voltage for the IO bank that the + pin belongs to. Each bank of IO pins operate at a specific, + fixed voltage levels. Incorrect voltage configuration can + damage the chip. The defined constants represent the + possible voltage configurations: + + - K230_MSC_3V3 (value 0): 3.3V power supply + - K230_MSC_1V8 (value 1): 1.8V power supply + + The following banks have the corresponding voltage + configurations: + + - bank IO0 to IO1: Fixed at 1.8V + - bank IO2 to IO13: Fixed at 1.8V + - bank IO14 to IO25: Fixed at 1.8V + - bank IO26 to IO37: Fixed at 1.8V + - bank IO38 to IO49: Fixed at 1.8V + - bank IO50 to IO61: Fixed at 3.3V + - bank IO62 to IO63: Fixed at 1.8V + + enum: [0, 1] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x91105000 0x100>; + + uart2-pins { + uart2-pins-cfg { + pinmux = <0x503>, /* uart2 txd */ + <0x603>; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = <1>; + input-enable; + output-enable; + bias-disable; + }; + }; + }; -- cgit v1.2.3 From b0c37572a6a4ce61fb5622b87db12f4079ad1826 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 Sep 2024 17:24:38 +0200 Subject: dt-bindings: pinctrl: amlogic,meson-pinctrl: lower gpio-line-names minItems for meson8b The Amlogic Meson8b SoC has 83 CBUS GPIOs, thus lower the minItems for gpio-line-names to account for it, fixing DTBs check on Meson8b based boards. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/20240911-topic-amlogic-arm32-upstream-bindings-fixes-meson-pinctrl-gpio-line-names-v1-1-4345ba336ea4@linaro.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml index 412bbcc276f3..c954761e0150 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -46,7 +46,7 @@ patternProperties: - const: gpio gpio-line-names: - minItems: 86 # AXG + minItems: 83 # Meson8b maxItems: 120 # Meson8 unevaluatedProperties: -- cgit v1.2.3 From 55c487ea6084afa85753916fbbe40c3e658d9788 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 20 Sep 2024 16:00:09 +0800 Subject: dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer Document the Top Level Mode Multiplexer on the QCS615 Platform. It concisely explains the pin multiplexing and configuration in the device tree, and includes simple examples of typical device tree snippets, making it easier for designers to configure and manage chip pins. Signed-off-by: Lijuan Gao Link: https://lore.kernel.org/20240920-add_qcs615_pinctrl_driver-v2-1-e03c42a9d055@quicinc.com Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,qcs615-tlmm.yaml | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml new file mode 100644 index 000000000000..1ce4b5df584a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS615 TLMM block + +maintainers: + - Lijuan Gao + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs615-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: east + - const: west + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 62 + + gpio-line-names: + maxItems: 123 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs615-tlmm-state" + - type: object + patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs615-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs615-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_gp, + copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, + edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc_gp, + gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, + mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out, + pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pll_bist, + pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio, + qlink_enable, qlink_request, qspi, qup0, qup1, rgmii, + sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, usb0_hs, + usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, wsa_clk, + wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@3000000 { + compatible = "qcom,qcs615-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03c00000 0x300000>; + reg-names = "east", "west", "south"; + interrupts = ; + gpio-ranges = <&tlmm 0 0 123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup3-uart2-state { + pins ="gpio16", "gpio17"; + function = "qup0"; + }; + }; +... -- cgit v1.2.3 From 724d52a3cd33774570c43cff06403b4cdda00abe Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 20 Sep 2024 18:45:02 +0300 Subject: dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC Add compatible for Exynos8895 SoC. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240920154508.1618410-5-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 242dd13c276b..a2af2c88a331 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -53,6 +53,7 @@ properties: - samsung,exynos7-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8895-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl -- cgit v1.2.3 From e2d58d1e1c61c1e1d4af400cc0ebcebf98efb49f Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 20 Sep 2024 18:45:04 +0300 Subject: dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible Add a dedicated compatible for exynos8895. Signed-off-by: Ivaylo Ivanov Acked-by: Rob Herring (Arm) Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20240920154508.1618410-7-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 4dfb49b0e07f..91516fedc872 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -42,6 +42,7 @@ properties: - samsung,exynos5433-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint - items: - enum: -- cgit v1.2.3 From f07e2b681edd8d8ed25048b958fdcfb55abaf487 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 4 Oct 2024 13:36:56 +0100 Subject: dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties On the RZ/V2H(P) SoC one can configure the 'input-schmitt-{enable,disable}', 'drive-open-drain' and 'drive-push-pull' of multiplexed pins. Update the binding documentation to include these properties. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/20241004123658.764557-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 56d90c8e1fa3..a1805b6e3f63 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -119,6 +119,10 @@ additionalProperties: bias-disable: true bias-pull-down: true bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + drive-open-drain: true + drive-push-pull: true renesas,output-impedance: description: Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this -- cgit v1.2.3 From ffb30875172eabff727e2896f097ccd4bb68723f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Oct 2024 08:58:47 +0200 Subject: dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with fallbacks Commit 904140fa4553 ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") added samsung,exynos7-wakeup-eint fallback to some compatibles, so the intention in the if:then: conditions was to handle the cases: 1. Single Exynos7 compatible or Exynos5433+Exynos7 or Exynos7885+Exynos7: only one interrupt 2. Exynos850+Exynos7: no interrupts This was not implemented properly however and if:then: block matches only single Exynos5433 or Exynos7885 compatibles, which do not exist in DTS anymore, so basically is a no-op and no enforcement on number of interrupts is made by the binding. Fix the if:then: condition so interrupts in the Exynos5433 and Exynos7885 wake-up pin controller will be properly constrained. Fixes: 904140fa4553 ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") Cc: stable@vger.kernel.org Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20241015065848.29429-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 91516fedc872..49cb2b1a3d28 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -92,14 +92,17 @@ allOf: - if: properties: compatible: - # Match without "contains", to skip newer variants which are still - # compatible with samsung,exynos7-wakeup-eint - enum: - - samsung,s5pv210-wakeup-eint - - samsung,exynos4210-wakeup-eint - - samsung,exynos5433-wakeup-eint - - samsung,exynos7-wakeup-eint - - samsung,exynos7885-wakeup-eint + oneOf: + # Match without "contains", to skip newer variants which are still + # compatible with samsung,exynos7-wakeup-eint + - enum: + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,s5pv210-wakeup-eint + - contains: + enum: + - samsung,exynos5433-wakeup-eint + - samsung,exynos7885-wakeup-eint then: properties: interrupts: -- cgit v1.2.3 From e0f89ba1e04307a0060b354c40d29d008a3fef6e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Oct 2024 08:58:48 +0200 Subject: dt-bindings: pinctrl: samsung: Add missing constraint for Exynos8895 interrupts Expect only one interrupt on Exynos8895 wake-up pin controller. Fixes: e2d58d1e1c61 ("dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible") Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20241015065848.29429-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 49cb2b1a3d28..b7c2692f0ac3 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -103,6 +103,7 @@ allOf: enum: - samsung,exynos5433-wakeup-eint - samsung,exynos7885-wakeup-eint + - samsung,exynos8895-wakeup-eint then: properties: interrupts: -- cgit v1.2.3 From 5b653cb60275e1ad1a85f0d056a3084c4635623c Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Wed, 16 Oct 2024 17:48:36 +0200 Subject: dt-bindings: pinctrl: samsung: Add exynos990-pinctrl compatible Add a dedicated compatible for the exynos990-pinctrl node. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20241016154838.64515-2-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index a2af2c88a331..7e6ef8249de6 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,6 +54,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl -- cgit v1.2.3 From e690012f4f924f4ef4e105427b04ea3d496c6a38 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Wed, 16 Oct 2024 17:48:37 +0200 Subject: dt-bindings: pinctrl: samsung: Add exynos990-wakeup-eint compatible Add a dedicated compatible for the exynos990-wakeup-eint node. This SoC pin controller does not mux interrupts. It's compatible with Exynos 850's node, while also being compatible with the Exynos7 fallback. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20241016154838.64515-3-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index b7c2692f0ac3..565cacadb6be 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -47,6 +47,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint - const: samsung,exynos7-wakeup-eint -- cgit v1.2.3 From 97b7675640928a5de971f43034ba1f41e30001b7 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 16 Oct 2024 08:59:41 +0800 Subject: dt-bindings: pinctrl: spacemit: add support for K1 SoC Add dt-bindings for the pinctrl driver of SpacemiT's K1 SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Yixun Lan Link: https://lore.kernel.org/20241016-02-k1-pinctrl-v5-1-03d395222e4f@gentoo.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml new file mode 100644 index 000000000000..b01ecd83b71b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/spacemit,k1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC Pin Controller + +maintainers: + - Yixun Lan + +properties: + compatible: + const: spacemit,k1-pinctrl + + reg: + items: + - description: pinctrl io memory base + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + drive strength, input schmitt trigger, slew rate, power source. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the K1_PADCONF macro to + construct the value. + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: + description: | + typical value for selecting bias pull up or strong pull up. + 0: normal bias pull up + 1: strong bias pull up + enum: [ 0, 1 ] + + drive-strength: + description: | + typical current when output high level. + 1.8V output: 11, 21, 32, 42 (mA) + 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) + + input-schmitt: + description: | + typical threshold for schmitt trigger. + 0: buffer mode + 1: trigger mode + 2, 3: trigger mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + power-source: + description: external power supplies at 1.8v or 3.3v. + enum: [ 1800, 3300 ] + + slew-rate: + description: | + slew rate for output buffer. + 0: disable it + 1: enable it (via bundled value from drive strength) + 2: slow speed 0 + 3: slow speed 1 + 4: medium speed + 5: fast speed + enum: [ 0, 1, 2, 3, 4, 5 ] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define K1_PADCONF(pin, func) (((pin) << 16) | (func)) + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x400>; + + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { + pinmux = , + ; + + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + }; + }; + +... -- cgit v1.2.3 From 5778535972e2c1eb69e698803a610b43e50cb036 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Fri, 18 Oct 2024 11:19:31 +0800 Subject: dt-bindings: pinctrl: describe qcs8300-tlmm Add DT bindings for the TLMM controller on QCS8300 platforms. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-1-8b8d3957cf1a@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml new file mode 100644 index 000000000000..bb0d7132886a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 TLMM block + +maintainers: + - Jingyi Wang + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm QCS8300 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 67 + + gpio-line-names: + maxItems: 133 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs8300-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs8300-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs8300-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" + - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest_char, atest_usb2, audio_ref, cam_mclk, + cci_async, cci_i2c_scl, cci_i2c_sda, cci_timer, cri_trng, + dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, + edp0_hot, edp0_lcd, edp1_lcd, egpio, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux, + emac0_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5, + gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, jitter_bist, + mdp0_vsync0, mdp0_vsync1, mdp0_vsync3, mdp0_vsync6, mdp0_vsync7, + mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, + mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, + pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, + qdss_cti, qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, + qup0_se4, qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, + qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, + qup2_se0, sailss_emac0, sailss_ospi, sail_top, sgmii_phy, + tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, usb2phy_ac, + vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,qcs8300-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio43", "gpio44"; + function = "qup0_se7"; + }; + }; +... -- cgit v1.2.3 From e89768f63f49fd7a31ebc1699cd209549f27611e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 18 Oct 2024 11:42:39 +0300 Subject: dt-bindings: pinctrl : qcom: document SAR2130P TLMM Add bindings for the pin controller (TLMM) present on the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-1-11a1d09a6e5f@linaro.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sar2130p-tlmm.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml new file mode 100644 index 000000000000..b388380b1ce0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SAR2130P TLMM block + +maintainers: + - Dmitry Baryshkov + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sar2130p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sar2130p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sar2130p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02, + atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk1, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkreqn, + pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, qup0, + qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup10, + qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,sar2130p-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 156>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; + }; + }; +... -- cgit v1.2.3 From 56c9d1a033d628b7abac88a5e19c9a5111b01302 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 17 Oct 2024 23:11:18 +0200 Subject: dt-bindings: pinctrl: fsl,imx6ul-pinctrl: Convert i.MX35/5x/6 to YAML The IOMUXC controller description is almost identical on i.MX35/5x/6 SoCs, except for the configuration bits which differ across SoCs. Rename the fsl,imx6ul-pinctrl.yaml to fsl,imx35-pinctrl.yaml, fill in compatible strings for the other SoCs and fill in the various bits into desciption. This way, i.MX35/5x/6 series SoCs can all be converted to DT schema. Remove the old text DT bindings description. Reviewed-by: Rob Herring (Arm) Signed-off-by: Marek Vasut Link: https://lore.kernel.org/20241017211241.170861-1-marex@denx.de Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx35-pinctrl.txt | 33 ---- .../bindings/pinctrl/fsl,imx35-pinctrl.yaml | 184 +++++++++++++++++++++ .../bindings/pinctrl/fsl,imx50-pinctrl.txt | 32 ---- .../bindings/pinctrl/fsl,imx51-pinctrl.txt | 32 ---- .../bindings/pinctrl/fsl,imx53-pinctrl.txt | 32 ---- .../bindings/pinctrl/fsl,imx6dl-pinctrl.txt | 38 ----- .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 38 ----- .../bindings/pinctrl/fsl,imx6sl-pinctrl.txt | 39 ----- .../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 ----- .../bindings/pinctrl/fsl,imx6sx-pinctrl.txt | 36 ---- .../bindings/pinctrl/fsl,imx6ul-pinctrl.yaml | 116 ------------- 11 files changed, 184 insertions(+), 436 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt deleted file mode 100644 index c083dfd25db9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Freescale IMX35 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx35-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx35 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) -PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE_CMOS (0 << 3) -PAD_CTL_ODE_OPENDRAIN (1 << 3) -PAD_CTL_DSE_NOMINAL (0 << 1) -PAD_CTL_DSE_HIGH (1 << 1) -PAD_CTL_DSE_MAX (2 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx35-pinfunc.h in device tree source folder for all available -imx35 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml new file mode 100644 index 000000000000..265c43ab76f4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller + +maintainers: + - Dong Aisheng + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + oneOf: + - enum: + - fsl,imx35-iomuxc + - fsl,imx51-iomuxc + - fsl,imx53-iomuxc + - fsl,imx6dl-iomuxc + - fsl,imx6q-iomuxc + - fsl,imx6sl-iomuxc + - fsl,imx6sll-iomuxc + - fsl,imx6sx-iomuxc + - fsl,imx6ul-iomuxc + - fsl,imx6ull-iomuxc-snvs + - items: + - const: fsl,imx50-iomuxc + - const: fsl,imx53-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to matching i.MX Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + Common i.MX35 + PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) + PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE_CMOS (0 << 3) + PAD_CTL_ODE_OPENDRAIN (1 << 3) + PAD_CTL_DSE_NOMINAL (0 << 1) + PAD_CTL_DSE_HIGH (1 << 1) + PAD_CTL_DSE_MAX (2 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX50/i.MX51/i.MX53 bits + PAD_CTL_HVE (1 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE (1 << 3) + PAD_CTL_DSE_LOW (0 << 1) + PAD_CTL_DSE_MED (1 << 1) + PAD_CTL_DSE_HIGH (2 << 1) + PAD_CTL_DSE_MAX (3 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX6 bits + PAD_CTL_HYS (1 << 16) + PAD_CTL_PUS_100K_DOWN (0 << 14) + PAD_CTL_PUS_47K_UP (1 << 14) + PAD_CTL_PUS_100K_UP (2 << 14) + PAD_CTL_PUS_22K_UP (3 << 14) + PAD_CTL_PUE (1 << 13) + PAD_CTL_PKE (1 << 12) + PAD_CTL_ODE (1 << 11) + PAD_CTL_SPEED_LOW (0 << 6) + PAD_CTL_SPEED_MED (1 << 6) + PAD_CTL_SPEED_HIGH (3 << 6) + PAD_CTL_DSE_DISABLE (0 << 3) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + i.MX6SL/MX6SLL specific bits + PAD_CTL_LVE (1 << 22) (MX6SL/SLL only) + i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits + PAD_CTL_DSE_260ohm (1 << 3) + PAD_CTL_DSE_130ohm (2 << 3) + PAD_CTL_DSE_87ohm (3 << 3) + PAD_CTL_DSE_65ohm (4 << 3) + PAD_CTL_DSE_52ohm (5 << 3) + PAD_CTL_DSE_43ohm (6 << 3) + PAD_CTL_DSE_37ohm (7 << 3) + i.MX6DL/i.MX6Q/i.MX6SL specific bits + PAD_CTL_DSE_240ohm (1 << 3) + PAD_CTL_DSE_120ohm (2 << 3) + PAD_CTL_DSE_80ohm (3 << 3) + PAD_CTL_DSE_60ohm (4 << 3) + PAD_CTL_DSE_48ohm (5 << 3) + PAD_CTL_DSE_40ohm (6 << 3) + PAD_CTL_DSE_34ohm (7 << 3) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + + mux_uart: uartgrp { + fsl,pins = < + 0x0084 0x0310 0x0000 0 0 0x1b0b1 + 0x0088 0x0314 0x0624 0 3 0x1b0b1 + >; + }; + }; + - | + iomuxc_snvs: pinctrl@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + + pinctrl_snvs_usbc_det: snvsusbcdetgrp { + fsl,pins = < + 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 + >; + }; + }; + - | + iomuxc_mx6q: pinctrl@20e0000 { + compatible = "fsl,imx6q-iomuxc"; + reg = <0x20e0000 0x4000>; + + pinctrl_uart4: uart4grp { + fsl,pins = + <0x288 0x658 0x000 0x3 0x0 0x140>, + <0x28c 0x65c 0x938 0x3 0x3 0x140>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt deleted file mode 100644 index 6da01d619d33..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX50 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx50-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx50 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx50-pinfunc.h in device tree source folder for all available -imx50 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt deleted file mode 100644 index 4d1408fcc99c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX51 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx51-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx51 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx51-pinfunc.h in device tree source folder for all available -imx51 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt deleted file mode 100644 index 25dcb77cfaf7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX53 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx53-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx53 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx53-pinfunc.h in device tree source folder for all available -imx53 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt deleted file mode 100644 index 0ac5bee87505..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6 DualLite/Solo IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6dl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6dl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6dl-pinfunc.h in device tree source folder for all available -imx6dl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index 546610cf2ae7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6Q IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6q-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6q datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6q-pinfunc.h in device tree source folder for all available -imx6q PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt deleted file mode 100644 index e5f6d1f065a4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Freescale IMX6 SoloLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6sl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sl-pinfunc.h in device tree source folder for all available -imx6sl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt deleted file mode 100644 index 175e8939a301..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Freescale i.MX6 SLL IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sll-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6SLL - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sll-pinfunc.h in device tree source folder for all available -imx6sll PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt deleted file mode 100644 index b1b595220f1b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale i.MX6 SoloX IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sx-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml deleted file mode 100644 index 906b264a9e3c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml +++ /dev/null @@ -1,116 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX6UL IOMUX Controller - -maintainers: - - Dong Aisheng - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -allOf: - - $ref: pinctrl.yaml# - -properties: - compatible: - enum: - - fsl,imx6ul-iomuxc - - fsl,imx6ull-iomuxc-snvs - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last integer - CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX6UL Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied: - PAD_CTL_HYS (1 << 16) - PAD_CTL_PUS_100K_DOWN (0 << 14) - PAD_CTL_PUS_47K_UP (1 << 14) - PAD_CTL_PUS_100K_UP (2 << 14) - PAD_CTL_PUS_22K_UP (3 << 14) - PAD_CTL_PUE (1 << 13) - PAD_CTL_PKE (1 << 12) - PAD_CTL_ODE (1 << 11) - PAD_CTL_SPEED_LOW (0 << 6) - PAD_CTL_SPEED_MED (1 << 6) - PAD_CTL_SPEED_HIGH (3 << 6) - PAD_CTL_DSE_DISABLE (0 << 3) - PAD_CTL_DSE_260ohm (1 << 3) - PAD_CTL_DSE_130ohm (2 << 3) - PAD_CTL_DSE_87ohm (3 << 3) - PAD_CTL_DSE_65ohm (4 << 3) - PAD_CTL_DSE_52ohm (5 << 3) - PAD_CTL_DSE_43ohm (6 << 3) - PAD_CTL_DSE_37ohm (7 << 3) - PAD_CTL_SRE_FAST (1 << 0) - PAD_CTL_SRE_SLOW (0 << 0) - - required: - - fsl,pins - - additionalProperties: false - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6ul-iomuxc"; - reg = <0x020e0000 0x4000>; - - mux_uart: uartgrp { - fsl,pins = < - 0x0084 0x0310 0x0000 0 0 0x1b0b1 - 0x0088 0x0314 0x0624 0 3 0x1b0b1 - >; - }; - }; - - | - iomuxc_snvs: pinctrl@2290000 { - compatible = "fsl,imx6ull-iomuxc-snvs"; - reg = <0x02290000 0x4000>; - - pinctrl_snvs_usbc_det: snvsusbcdetgrp { - fsl,pins = < - 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 - >; - }; - }; -- cgit v1.2.3 From 1aad42abae6b9ec104bec5d0ae496f2dc248dd28 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 08:42:45 +0200 Subject: dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: Add SM8750 Document compatible for Qualcomm SM8750 SoC LPASS TLMM pin controller, fully compatible with previous SM8650 generation (same amount of pins and functions). Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://lore.kernel.org/20241022064245.22983-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml index db7214362301..e90a5274647d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml @@ -16,7 +16,11 @@ description: properties: compatible: - const: qcom,sm8650-lpass-lpi-pinctrl + oneOf: + - const: qcom,sm8650-lpass-lpi-pinctrl + - items: + - const: qcom,sm8750-lpass-lpi-pinctrl + - const: qcom,sm8650-lpass-lpi-pinctrl reg: items: -- cgit v1.2.3 From 47c3309d58b5e6fd3fc425253491c1ce014538c0 Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 26 Oct 2024 23:32:34 +0300 Subject: dt-bindings: pinctrl: samsung: Add compatible for Exynos9810 SoC Add a compatible for Samsung Exynos9810 pinctrl block to the schema. Exynos9810 has 9 total pin banks and it's similar to other Samsung SoC pinctrl blocks. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20241026-exynos9810-v3-3-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7e6ef8249de6..5296a9e4faae 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,6 +54,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl -- cgit v1.2.3 From e830431e0ad0501c2e6dcb3c65dabc053e3ce5e4 Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 26 Oct 2024 23:32:35 +0300 Subject: dt-bindings: pinctrl: samsung: Add compatible for exynos9810-wakeup-eint Add the compatible for Samsung Exynos9810 pinctrl eint block to the schema. It is compatible with Exynos850 EINT controller, and doesn't have a dedicated IRQ line. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20241026-exynos9810-v3-4-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 565cacadb6be..68ed714eb0a1 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -47,6 +47,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint -- cgit v1.2.3 From 3ad8d3ec6d87b16cdd336aa065d8e150096a192b Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Mon, 28 Oct 2024 12:09:11 +0530 Subject: dt-bindings: pinctrl: convert pinctrl-mcp23s08.txt to yaml format YAML binding file provides the conversion of the original text-based binding for the pinctrl-mcp23s08 to microchip,mcp23s08.yaml. following compatible strings using the deprecated mcp prefix have been removed from this binding: - mcp,mcp23s08 - mcp,mcp23s17 - mcp,mcp23008 - mcp,mcp23017 Signed-off-by: Himanshu Bhavani Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20241028063939.6276-1-himanshu.bhavani@siliconsignals.io Signed-off-by: Linus Walleij --- .../bindings/pinctrl/microchip,mcp23s08.yaml | 161 +++++++++++++++++++++ .../bindings/pinctrl/pinctrl-mcp23s08.txt | 148 ------------------- 2 files changed, 161 insertions(+), 148 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml new file mode 100644 index 000000000000..e07f4723de17 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mcp23s08.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip I/O expander with serial interface (I2C/SPI) + +maintainers: + - Himanshu Bhavani + +description: + Microchip MCP23008, MCP23017, MCP23S08, MCP23S17, MCP23S18 GPIO expander + chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - microchip,mcp23s08 + - microchip,mcp23s17 + - microchip,mcp23s18 + - microchip,mcp23008 + - microchip,mcp23017 + - microchip,mcp23018 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO specifier for active-low reset pin. + maxItems: 1 + + microchip,spi-present-mask: + description: + Multiple SPI chips can share the same SPI chipselect. Set a bit in + bit0-7 in this mask to 1 if there is a chip connected with the + corresponding spi address set. For example if you have a chip with + address 3 connected, you have to set bit3 to 1, which is 0x08. mcp23s08 + chip variant only supports bits 0-3. It is not possible to mix mcp23s08 + and mcp23s17 on the same chipselect. Set at least one bit to 1 for SPI + chips. + $ref: /schemas/types.yaml#/definitions/uint8 + + microchip,irq-mirror: + type: boolean + description: + Sets the mirror flag in the IOCON register. Devices with two interrupt + outputs (these are the devices ending with 17 and those that have 16 IOs) + have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These chips + have two different interrupt outputs One for bank 1 and another for + bank 2. If irq-mirror is set, both interrupts are generated regardless of + the bank that an input change occurred on. If it is not set,the interrupt + are only generated for the bank they belong to. + + microchip,irq-active-high: + type: boolean + description: + Sets the INTPOL flag in the IOCON register.This configures the IRQ output + polarity as active high. + + drive-open-drain: + type: boolean + description: + Sets the ODR flag in the IOCON register. This configures the IRQ output as + open drain active low. + + pinmux: + type: object + properties: + pins: + description: + The list of GPIO pins controlled by this node. Each pin name + corresponds to a physical pin on the GPIO expander. + items: + pattern: '^gpio([0-9]|[1][0-5])$' + maxItems: 16 + + bias-pull-up: + type: boolean + description: + Configures pull-up resistors for the GPIO pins. Absence of this + property will leave the configuration in its default state. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + gpio@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + microchip,irq-mirror; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>, <&gpiopullups>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + gpiopullups: pinmux { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + bias-pull-up; + }; + }; + }; + + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + gpio@0 { + compatible = "microchip,mcp23s17"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + microchip,spi-present-mask = /bits/ 8 <0x01>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt deleted file mode 100644 index 2fa5edac7a35..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ /dev/null @@ -1,148 +0,0 @@ -Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for -8-/16-bit I/O expander with serial interface (I2C/SPI) - -Required properties: -- compatible : Should be - - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version - - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version - - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or - - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip - - - "microchip,mcp23s08" for 8 GPIO SPI version - - "microchip,mcp23s17" for 16 GPIO SPI version - - "microchip,mcp23s18" for 16 GPIO SPI version - - "microchip,mcp23008" for 8 GPIO I2C version or - - "microchip,mcp23017" for 16 GPIO I2C version of the chip - - "microchip,mcp23018" for 16 GPIO I2C version - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags as described in - 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by - 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW). -- gpio-controller : Marks the device node as a GPIO controller. -- reg : For an address on its bus. I2C uses this a the I2C address of the chip. - SPI uses this to specify the chipselect line which the chip is - connected to. The driver and the SPI variant of the chip support - multiple chips on the same chipselect. Have a look at - microchip,spi-present-mask below. - -Required device specific properties (only for SPI chips): -- mcp,spi-present-mask (DEPRECATED) -- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI - chips - as the name suggests. Multiple SPI chips can share the same - SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a - chip connected with the corresponding spi address set. For example if - you have a chip with address 3 connected, you have to set bit3 to 1, - which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not - possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at - least one bit to 1 for SPI chips. - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- spi-max-frequency = The maximum frequency this chip is able to handle - -Optional properties: -- #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as a interrupt controller. -- drive-open-drain: Sets the ODR flag in the IOCON register. This configures - the IRQ output as open drain active low. -- reset-gpios: Corresponds to the active-low RESET# pin for the chip - -Optional device specific properties: -- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices - with two interrupt outputs (these are the devices ending with 17 and - those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - IO 8-15 are bank 2. These chips have two different interrupt outputs: - One for bank 1 and another for bank 2. If irq-mirror is set, both - interrupts are generated regardless of the bank that an input change - occurred on. If it is not set, the interrupt are only generated for the - bank they belong to. - On devices with only one interrupt output this property is useless. -- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This - configures the IRQ output polarity as active high. - -Example I2C (with interrupt): -gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells=<2>; - microchip,irq-mirror; -}; - -Example SPI: -gpiom1: gpio@0 { - compatible = "microchip,mcp23s17"; - gpio-controller; - #gpio-cells = <2>; - microchip,spi-present-mask = <0x01>; - reg = <0>; - spi-max-frequency = <1000000>; -}; - -Pull-up configuration -===================== - -If pins are used as output, they can also be configured with pull-ups. This is -done with pinctrl. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0 ... gpio7 for the devices with 8 GPIO pins and - gpio0 ... gpio15 for the devices with 16 GPIO pins. - -Optional properties: -------------------- -The following optional property is defined in the pinmux DT binding document -. Absence of this property will leave the configuration -in its default state. - bias-pull-up - -Example with pinctrl to pull-up output pins: -gpio21: gpio@21 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <0x2>; - reg = <0x21>; - interrupt-parent = <&socgpio>; - interrupts = <0x17 0x8>; - interrupt-names = "mcp23017@21 irq"; - interrupt-controller; - #interrupt-cells = <0x2>; - microchip,irq-mirror; - pinctrl-names = "default"; - pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - - gpio21pullups: pinmux { - pins = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15"; - bias-pull-up; - }; -}; -- cgit v1.2.3 From e2adb96f53c0fd323d1aeb2a441c55aa7554bb1e Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Wed, 23 Oct 2024 01:20:01 +0200 Subject: dt-bindings: arm: airoha: Add the chip-scu node for EN7581 SoC This patch adds the chip-scu document bindings for EN7581 SoC. The airoha chip-scu block provides a configuration interface for clock, io-muxing and other functionalities used by multiple controllers (e.g. clock, pinctrl, ecc.) on EN7581 SoC. Reviewed-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/20241023-en7581-pinctrl-v9-1-afb0cbcab0ec@kernel.org Signed-off-by: Linus Walleij --- .../bindings/arm/airoha,en7581-chip-scu.yaml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml new file mode 100644 index 000000000000..67c449d804c2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Chip SCU Controller for EN7581 SoC + +maintainers: + - Lorenzo Bianconi + +description: + The airoha chip-scu block provides a configuration interface for clock, + io-muxing and other functionalities used by multiple controllers (e.g. clock, + pinctrl, ecc) on EN7581 SoC. + +properties: + compatible: + items: + - enum: + - airoha,en7581-chip-scu + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + }; -- cgit v1.2.3 From d0c15cb96b74606b18721dc11637cf494703a617 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Wed, 23 Oct 2024 01:20:02 +0200 Subject: dt-bindings: pinctrl: airoha: Add EN7581 pinctrl Introduce device-tree binding documentation for Airoha EN7581 pinctrl controller. Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/20241023-en7581-pinctrl-v9-2-afb0cbcab0ec@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/airoha,en7581-pinctrl.yaml | 400 +++++++++++++++++++++ 1 file changed, 400 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file mode 100644 index 000000000000..b2601d698dcd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -0,0 +1,400 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha's EN7581 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,en7581-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3, + pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1, pcie_reset2] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; -- cgit v1.2.3 From a24663432fe1dfe1ab4db020cb94942258c1ed24 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Wed, 23 Oct 2024 01:20:03 +0200 Subject: dt-bindings: pwm: airoha: Add EN7581 pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce device-tree binding documentation for Airoha EN7581 pwm controller. Co-developed-by: Christian Marangi Signed-off-by: Christian Marangi Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Lorenzo Bianconi Acked-by: Uwe Kleine-König Link: https://lore.kernel.org/20241023-en7581-pinctrl-v9-3-afb0cbcab0ec@kernel.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/pwm/airoha,en7581-pwm.yaml | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml b/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml new file mode 100644 index 000000000000..f36387572a97 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/airoha,en7581-pwm.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/airoha,en7581-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 PWM Controller + +maintainers: + - Lorenzo Bianconi + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: airoha,en7581-pwm + + "#pwm-cells": + const: 3 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + pwm { + compatible = "airoha,en7581-pwm"; + + #pwm-cells = <3>; + }; -- cgit v1.2.3 From 50dedb1eb1e6755ccab55f6140916c2d192be765 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 23 Oct 2024 01:20:04 +0200 Subject: dt-bindings: mfd: Add support for Airoha EN7581 GPIO System Controller Add support for Airoha EN7581 GPIO System Controller which provide a register map for controlling the GPIO, pinctrl and PWM of the SoC via dedicated pinctrl and pwm child nodes. Signed-off-by: Christian Marangi Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Co-developed-by: Lorenzo Bianconi Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/20241023-en7581-pinctrl-v9-4-afb0cbcab0ec@kernel.org Signed-off-by: Linus Walleij --- .../bindings/mfd/airoha,en7581-gpio-sysctl.yaml | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml b/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml new file mode 100644 index 000000000000..4a81ed82ef34 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,en7581-gpio-sysctl.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 GPIO System Controller + +maintainers: + - Christian Marangi + - Lorenzo Bianconi + +description: + Airoha EN7581 SoC GPIO system controller which provided a register map + for controlling the GPIO, pins and PWM of the SoC. + +properties: + compatible: + items: + - const: airoha,en7581-gpio-sysctl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + pinctrl: + type: object + $ref: /schemas/pinctrl/airoha,en7581-pinctrl.yaml + description: + Child node definition for EN7581 Pin controller + + pwm: + type: object + $ref: /schemas/pwm/airoha,en7581-pwm.yaml + description: + Child node definition for EN7581 PWM controller + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + system-controller@1fbf0200 { + compatible = "airoha,en7581-gpio-sysctl", "syscon", "simple-mfd"; + reg = <0x1fbf0200 0xc0>; + + pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; + + pwm { + compatible = "airoha,en7581-pwm"; + + #pwm-cells = <3>; + }; + }; -- cgit v1.2.3 From fecb6e2af7d430d8819da070aab91a84bda82595 Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Thu, 31 Oct 2024 02:19:42 +0100 Subject: dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the 8 GPIOs found on PM8937. It has holes on 3,4 and 6 pins. Signed-off-by: Barnabás Czémán Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20241031-msm8917-v2-1-8a075faa89b1@mainlining.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index c1b799167d81..055cea5452eb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -48,6 +48,7 @@ properties: - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio + - qcom,pm8937-gpio - qcom,pm8941-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio @@ -184,6 +185,7 @@ allOf: - qcom,pm8226-gpio - qcom,pm8350b-gpio - qcom,pm8550ve-gpio + - qcom,pm8937-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio @@ -468,6 +470,7 @@ $defs: - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 + - gpio1-gpio8 for pm8937 (hole on gpio3, gpio4 and gpio6) - gpio1-gpio36 for pm8941 - gpio1-gpio8 for pm8950 (hole on gpio3) - gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6) -- cgit v1.2.3 From d33d689eda6e477b05d086955b063829c0ad081a Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Thu, 31 Oct 2024 02:19:44 +0100 Subject: dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the Device Tree binding for PM8937 MPPs. Signed-off-by: Barnabás Czémán Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20241031-msm8917-v2-3-8a075faa89b1@mainlining.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 43146709e204..9364ae05f3e6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -22,6 +22,7 @@ properties: - qcom,pm8226-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp + - qcom,pm8937-mpp - qcom,pm8941-mpp - qcom,pm8950-mpp - qcom,pmi8950-mpp @@ -92,6 +93,7 @@ $defs: this subnode. Valid pins are - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 + - mpp1-mpp4 for pm8937 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 -- cgit v1.2.3 From 4905aa25d31f877c5794fbf9e2acd3598ebe01df Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 29 Oct 2024 09:23:12 +0800 Subject: dt-bindings: pinctrl: correct typo of description for cv1800 It should be PINMUX/PINMUX2, not GPIOMUX/GPIOMUX2, see . Fixes: 64aa494de6fa ("dt-bindings: pinctrl: Add pinctrl for Sophgo CV1800 series SoC.") Signed-off-by: Chen Wang Reviewed-by: Inochi Amaoto Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/20241029012312.3448287-1-unicornxw@gmail.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml index 1e6a55afe26a..feb4785a3fac 100644 --- a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml @@ -58,7 +58,7 @@ patternProperties: pinmux: description: | The list of GPIOs and their mux settings that properties in the - node apply to. This should be set using the GPIOMUX or GPIOMUX2 + node apply to. This should be set using the PINMUX or PINMUX2 macro. bias-pull-up: -- cgit v1.2.3 From b8a8a0f268be85e2ad3dd97eaee05c269fb5781b Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Mon, 4 Nov 2024 17:37:04 +0100 Subject: dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the "marvell,pxa1908-padconf" compatible to allow migrating to a separate pinctrl driver later. Reviewed-by: Rob Herring Acked-by: Linus Walleij Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/20241104-pxa1908-lkml-v13-2-e050609b8d6c@skole.hr Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index e02595316c9f..f83dbf32ad18 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -33,6 +33,10 @@ properties: - ti,omap5-padconf - ti,j7200-padconf - const: pinctrl-single + - items: + - enum: + - marvell,pxa1908-padconf + - const: pinconf-single reg: maxItems: 1 -- cgit v1.2.3 From a53643fb30f84a9914a7b7205f4ff4c73fe6e7b6 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 5 Nov 2024 07:42:05 +0100 Subject: dt-bindings: pinctrl: sx150xq: allow gpio line naming Adding gpio-line-names property works fine for this device node, but dtb check drops warning: 'gpio-line-names' does not match any of the regexes: '-cfg$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml# Allow to add property gpio-line-names for this devices. Signed-off-by: Heiko Schocher Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20241105064206.43626-3-hs@denx.de Signed-off-by: Linus Walleij --- .../bindings/pinctrl/semtech,sx1501q.yaml | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml index 4214d7311f6b..39d7dad3313b 100644 --- a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -26,6 +26,10 @@ properties: reg: maxItems: 1 + gpio-line-names: + minItems: 5 + maxItems: 17 + interrupts: maxItems: 1 @@ -87,6 +91,45 @@ required: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + - semtech,sx1507q + then: + properties: + gpio-line-names: + minItems: 5 + maxItems: 5 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + - semtech,sx1508q + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + - semtech,sx1509q + then: + properties: + gpio-line-names: + minItems: 17 + maxItems: 17 - if: not: properties: -- cgit v1.2.3 From b02e9f9172cedc0d0e0417fb91b79f24794cbf02 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 11 Nov 2024 16:28:42 -0800 Subject: dt-bindings: pinctrl: qcom: Add sm8750 pinctrl Add documentation for the Qualcomm sm8750 tlmm. Signed-off-by: Melody Olvera Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/20241112002843.2804490-2-quic_molvera@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8750-tlmm.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml new file mode 100644 index 000000000000..7aecc97745a8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8750-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8750 TLMM block + +maintainers: + - Melody Olvera + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8750 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8750-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 108 + + gpio-line-names: + maxItems: 215 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8750-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8750-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8750-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, + sd_write_protect, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + tsense_pwm4, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8750-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 216>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio60"; + function = "qup1_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio61"; + function = "qup1_se7"; + bias-disable; + }; + }; + }; +... -- cgit v1.2.3