From 2c7b9b936bdc6ff0a7a5f6aed8e55d27ca14807d Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 19 Jul 2022 10:08:27 -0500 Subject: net: ipa: move configuration data files into a subdirectory Reduce the clutter in the main IPA source directory by creating a new "data" subdirectory, and locating all of the configuration data files in there. Signed-off-by: Alex Elder Signed-off-by: Jakub Kicinski --- drivers/net/ipa/Makefile | 2 +- drivers/net/ipa/data/ipa_data-v3.1.c | 537 +++++++++++++++++++++++++++++++++ drivers/net/ipa/data/ipa_data-v3.5.1.c | 422 ++++++++++++++++++++++++++ drivers/net/ipa/data/ipa_data-v4.11.c | 405 +++++++++++++++++++++++++ drivers/net/ipa/data/ipa_data-v4.2.c | 384 +++++++++++++++++++++++ drivers/net/ipa/data/ipa_data-v4.5.c | 461 ++++++++++++++++++++++++++++ drivers/net/ipa/data/ipa_data-v4.9.c | 455 ++++++++++++++++++++++++++++ drivers/net/ipa/ipa_data-v3.1.c | 537 --------------------------------- drivers/net/ipa/ipa_data-v3.5.1.c | 422 -------------------------- drivers/net/ipa/ipa_data-v4.11.c | 405 ------------------------- drivers/net/ipa/ipa_data-v4.2.c | 384 ----------------------- drivers/net/ipa/ipa_data-v4.5.c | 461 ---------------------------- drivers/net/ipa/ipa_data-v4.9.c | 455 ---------------------------- 13 files changed, 2665 insertions(+), 2665 deletions(-) create mode 100644 drivers/net/ipa/data/ipa_data-v3.1.c create mode 100644 drivers/net/ipa/data/ipa_data-v3.5.1.c create mode 100644 drivers/net/ipa/data/ipa_data-v4.11.c create mode 100644 drivers/net/ipa/data/ipa_data-v4.2.c create mode 100644 drivers/net/ipa/data/ipa_data-v4.5.c create mode 100644 drivers/net/ipa/data/ipa_data-v4.9.c delete mode 100644 drivers/net/ipa/ipa_data-v3.1.c delete mode 100644 drivers/net/ipa/ipa_data-v3.5.1.c delete mode 100644 drivers/net/ipa/ipa_data-v4.11.c delete mode 100644 drivers/net/ipa/ipa_data-v4.2.c delete mode 100644 drivers/net/ipa/ipa_data-v4.5.c delete mode 100644 drivers/net/ipa/ipa_data-v4.9.c diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile index 14b313fefa3a..8b2220eb6b92 100644 --- a/drivers/net/ipa/Makefile +++ b/drivers/net/ipa/Makefile @@ -13,4 +13,4 @@ ipa-y := ipa_main.o ipa_power.o ipa_reg.o ipa_mem.o \ ipa_resource.o ipa_qmi.o ipa_qmi_msg.o \ ipa_sysfs.o -ipa-y += $(IPA_VERSIONS:%=ipa_data-v%.o) +ipa-y += $(IPA_VERSIONS:%=data/ipa_data-v%.o) diff --git a/drivers/net/ipa/data/ipa_data-v3.1.c b/drivers/net/ipa/data/ipa_data-v3.1.c new file mode 100644 index 000000000000..00f4e506e6e5 --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v3.1.c @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019-2021 Linaro Ltd. + */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_HDR_SECTORS, + IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v3.1 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL = 0, + IPA_RSRC_GROUP_SRC_DL, + IPA_RSRC_GROUP_SRC_DIAG, + IPA_RSRC_GROUP_SRC_DMA, + IPA_RSRC_GROUP_SRC_UNUSED, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL = 0, + IPA_RSRC_GROUP_DST_DL, + IPA_RSRC_GROUP_DST_DIAG_DPL, + IPA_RSRC_GROUP_DST_DMA, + IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL, + IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v3.1 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 8, + }, + [IPA_QSB_MASTER_PCIE] = { + .max_writes = 2, + .max_reads = 8, + }, +}; + +/* Endpoint data for an SoC having IPA v3.1 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 6, + .endpoint_id = 22, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 18, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 15, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 5, + .endpoint_id = 3, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 8, + .endpoint_id = 16, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_DL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_LAN_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 4, + .endpoint_id = 9, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 5, + .endpoint_id = 18, + .toward_ipa = false, + }, +}; + +/* Source resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 3, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 3, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 2, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 14, .max = 14, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 16, .max = 16, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 19, .max = 19, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 26, .max = 26, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, /* 3 downstream */ + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, /* 7 downstream */ + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 19, .max = 19, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 26, .max = 26, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 3, .max = 3, /* 2 downstream */ + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 3, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 1, .max = 1, /* 0 downstream */ + }, + /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */ + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 3, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 1, .max = 1, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v3.1 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0140, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x07d0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x09d0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x0bd8, + .size = 0x1424, + .canary_count = 0, + }, + { + .id = IPA_MEM_END_MARKER, + .offset = 0x2000, + .size = 0, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v3.1 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146bd000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00002000, +}; + +/* Interconnect bandwidths are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 640000, /* 640 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + { + .name = "imem", + .peak_bandwidth = 640000, /* 640 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + /* Average bandwidth is unused for the next interconnect */ + { + .name = "config", + .peak_bandwidth = 80000, /* 80 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v3.1 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 16 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v3.1 */ +const struct ipa_data ipa_data_v3_1 = { + .version = IPA_VERSION_3_1, + .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v3.5.1.c b/drivers/net/ipa/data/ipa_data-v3.5.1.c new file mode 100644 index 000000000000..b7e32e87733e --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v3.5.1.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019-2021 Linaro Ltd. + */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.5.1 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v3.5.1 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_LWA_DL = 0, + IPA_RSRC_GROUP_SRC_UL_DL, + IPA_RSRC_GROUP_SRC_MHI_DMA, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_LWA_DL = 0, + IPA_RSRC_GROUP_DST_UL_DL_DPL, + IPA_RSRC_GROUP_DST_UNUSED_2, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 8, + }, + [IPA_QSB_MASTER_PCIE] = { + .max_writes = 4, + .max_reads = 12, + }, +}; + +/* Endpoint datdata for an SoC having IPA v3.5.1 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 4, + .endpoint_id = 5, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 5, + .endpoint_id = 9, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 3, + .endpoint_id = 2, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 6, + .endpoint_id = 10, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_LAN_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 3, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 4, + .endpoint_id = 6, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 12, + .toward_ipa = false, + }, +}; + +/* Source resource configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 1, .max = 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { + .min = 10, .max = 10, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 10, .max = 10, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { + .min = 12, .max = 12, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 14, .max = 14, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_MHI_DMA] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { + .min = 14, .max = 14, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 20, .max = 20, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 14, .max = 14, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_LWA_DL] = { + .min = 4, .max = 4, + }, + .limits[1] = { + .min = 4, .max = 4, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { + .min = 3, .max = 3, + } + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_LWA_DL] = { + .min = 2, .max = 63, + }, + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 1, .max = 63, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { + .min = 1, .max = 2, + } + }, +}; + +/* Resource configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v3.5.1 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0140, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x07d0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x09d0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x0bd8, + .size = 0x1024, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_EVENT_RING, + .offset = 0x1c00, + .size = 0x0400, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146bd000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00002000, +}; + +/* Interconnect bandwidths are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 600000, /* 600 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + /* Average bandwidth is unused for the next two interconnects */ + { + .name = "imem", + .peak_bandwidth = 350000, /* 350 MBps */ + .average_bandwidth = 0, /* unused */ + }, + { + .name = "config", + .peak_bandwidth = 40000, /* 40 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v3.5.1 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 75 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v3.5.1 */ +const struct ipa_data ipa_data_v3_5_1 = { + .version = IPA_VERSION_3_5_1, + .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | + BCR_TX_NOT_USING_BRESP_FMASK | + BCR_SUSPEND_L2_IRQ_FMASK | + BCR_HOLB_DROP_L2_IRQ_FMASK | + BCR_DUAL_TX_FMASK, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v4.11.c b/drivers/net/ipa/data/ipa_data-v4.11.c new file mode 100644 index 000000000000..1be823e5c5c2 --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v4.11.c @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2021 Linaro Ltd. */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.11 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v4.11 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL_DL = 0, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_UNUSED_2, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, + IPA_RSRC_GROUP_DST_UNUSED_1, + IPA_RSRC_GROUP_DST_DRB_IP, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v4.11 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 12, + .max_reads = 13, + .max_reads_beats = 120, + }, +}; + +/* Endpoint configuration data for an SoC having IPA v4.11 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 5, + .endpoint_id = 7, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 14, + .endpoint_id = 9, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 2, + .endpoint_id = 2, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 16, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 32768, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 7, + .endpoint_id = 14, + .toward_ipa = false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 8, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v4.11 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 6, .max = 6, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 18, .max = 18, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 2, .max = 2, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 15, .max = 15, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v4.11 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 3, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { + .min = 25, .max = 25, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 2, .max = 2, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v4.11 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v4.11 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0240, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_HEADER, + .offset = 0x08c8, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x0ad0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x0cd0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_NAT_TABLE, + .offset = 0x0ee0, + .size = 0x0d00, + .canary_count = 4, + }, + { + .id = IPA_MEM_PDN_CONFIG, + .offset = 0x1be8, + .size = 0x0050, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_QUOTA_MODEM, + .offset = 0x1c40, + .size = 0x0030, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_AP, + .offset = 0x1c70, + .size = 0x0048, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_TETHERING, + .offset = 0x1cb8, + .size = 0x0238, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_DROP, + .offset = 0x1ef0, + .size = 0x0020, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x1f18, + .size = 0x100c, + .canary_count = 2, + }, + { + .id = IPA_MEM_END_MARKER, + .offset = 0x3000, + .size = 0x0000, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v4.11 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146a8000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00009000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 600000, /* 600 MBps */ + .average_bandwidth = 150000, /* 150 MBps */ + }, + /* Average rate is unused for the next interconnect */ + { + .name = "config", + .peak_bandwidth = 74000, /* 74 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v4.11 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 60 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v4.11 */ +const struct ipa_data ipa_data_v4_11 = { + .version = IPA_VERSION_4_11, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v4.2.c b/drivers/net/ipa/data/ipa_data-v4.2.c new file mode 100644 index 000000000000..683f1f91042f --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v4.2.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2019-2021 Linaro Ltd. */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v4.2 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL_DL = 0, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v4.2 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 12, + /* no outstanding read byte (beat) limit */ + }, +}; + +/* Endpoint configuration data for an SoC having IPA v4.2 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 1, + .endpoint_id = 6, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 2, + .endpoint_id = 8, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 6, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 0, + .endpoint_id = 1, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 8, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, + .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 3, + .endpoint_id = 9, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 6, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_COMMAND_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 1, + .endpoint_id = 5, + .toward_ipa = true, + }, + [IPA_ENDPOINT_MODEM_LAN_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 3, + .endpoint_id = 11, + .toward_ipa = false, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 4, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 10, + .toward_ipa = false, + }, +}; + +/* Source resource configuration data for an SoC having IPA v4.2 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 3, .max = 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 10, .max = 10, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 1, .max = 1, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 5, .max = 5, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v4.2 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 1, .max = 63, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v4.2 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v4.2 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0290, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0310, + .size = 0, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0318, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0398, + .size = 0, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x03a0, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0420, + .size = 0, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0428, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x04a8, + .size = 0x0140, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x05f0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x07f0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_PDN_CONFIG, + .offset = 0x09f8, + .size = 0x0050, + .canary_count = 2, + }, + { + .id = IPA_MEM_STATS_QUOTA_MODEM, + .offset = 0x0a50, + .size = 0x0060, + .canary_count = 2, + }, + { + .id = IPA_MEM_STATS_TETHERING, + .offset = 0x0ab0, + .size = 0x0140, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x0bf0, + .size = 0x140c, + .canary_count = 0, + }, + { + .id = IPA_MEM_END_MARKER, + .offset = 0x2000, + .size = 0, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v4.2 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146a8000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00002000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 465000, /* 465 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + /* Average bandwidth is unused for the next two interconnects */ + { + .name = "imem", + .peak_bandwidth = 68570, /* 68.570 MBps */ + .average_bandwidth = 0, /* unused */ + }, + { + .name = "config", + .peak_bandwidth = 30000, /* 30 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v4.2 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 100 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v4.2 */ +const struct ipa_data ipa_data_v4_2 = { + .version = IPA_VERSION_4_2, + /* backward_compat value is 0 */ + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v4.5.c b/drivers/net/ipa/data/ipa_data-v4.5.c new file mode 100644 index 000000000000..79398f286a9c --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v4.5.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2021 Linaro Ltd. */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v4.5 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UNUSED_0 = 0, + IPA_RSRC_GROUP_SRC_UL_DL, + IPA_RSRC_GROUP_SRC_UNUSED_2, + IPA_RSRC_GROUP_SRC_UNUSED_3, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UNUSED_0 = 0, + IPA_RSRC_GROUP_DST_UL_DL_DPL, + IPA_RSRC_GROUP_DST_UNUSED_2, + IPA_RSRC_GROUP_DST_UNUSED_3, + IPA_RSRC_GROUP_DST_UC, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v4.5 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 0, /* no limit (hardware max) */ + .max_reads_beats = 120, + }, + [IPA_QSB_MASTER_PCIE] = { + .max_writes = 8, + .max_reads = 12, + /* no outstanding read byte (beat) limit */ + }, +}; + +/* Endpoint configuration data for an SoC having IPA v4.5 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 9, + .endpoint_id = 7, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 10, + .endpoint_id = 16, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 2, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 1, + .endpoint_id = 14, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 7, + .endpoint_id = 21, + .toward_ipa = false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 8, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v4.5 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 1, .max = 11, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 1, .max = 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 14, .max = 14, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 18, .max = 18, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = { + .min = 0, .max = 63, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 63, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 24, .max = 24, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v4.5 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 16, .max = 16, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { + .min = 2, .max = 2, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { + .min = 2, .max = 2, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 2, .max = 63, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { + .min = 1, .max = 2, + }, + .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { + .min = 1, .max = 2, + }, + .limits[IPA_RSRC_GROUP_DST_UC] = { + .min = 0, .max = 2, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v4.5 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v4.5 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0240, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_HEADER, + .offset = 0x08c8, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x0ad0, + .size = 0x0b20, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x15f0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_NAT_TABLE, + .offset = 0x1800, + .size = 0x0d00, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_MODEM, + .offset = 0x2510, + .size = 0x0030, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_AP, + .offset = 0x2540, + .size = 0x0048, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_TETHERING, + .offset = 0x2588, + .size = 0x0238, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_FILTER_ROUTE, + .offset = 0x27c0, + .size = 0x0800, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_DROP, + .offset = 0x2fc0, + .size = 0x0020, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x2fe8, + .size = 0x0800, + .canary_count = 2, + }, + { + .id = IPA_MEM_UC_EVENT_RING, + .offset = 0x3800, + .size = 0x1000, + .canary_count = 1, + }, + { + .id = IPA_MEM_PDN_CONFIG, + .offset = 0x4800, + .size = 0x0050, + .canary_count = 0, + }, +}; + +/* Memory configuration data for an SoC having IPA v4.5 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x14688000, + .imem_size = 0x00003000, + .smem_id = 497, + .smem_size = 0x00009000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 600000, /* 600 MBps */ + .average_bandwidth = 150000, /* 150 MBps */ + }, + /* Average rate is unused for the next two interconnects */ + { + .name = "imem", + .peak_bandwidth = 450000, /* 450 MBps */ + .average_bandwidth = 75000, /* 75 MBps (unused?) */ + }, + { + .name = "config", + .peak_bandwidth = 171400, /* 171.4 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v4.5 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v4.5 */ +const struct ipa_data ipa_data_v4_5 = { + .version = IPA_VERSION_4_5, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/data/ipa_data-v4.9.c b/drivers/net/ipa/data/ipa_data-v4.9.c new file mode 100644 index 000000000000..4b96efd05cf2 --- /dev/null +++ b/drivers/net/ipa/data/ipa_data-v4.9.c @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (C) 2021 Linaro Ltd. */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v4.9 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL_DL = 0, + IPA_RSRC_GROUP_SRC_DMA, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, + IPA_RSRC_GROUP_DST_DMA, + IPA_RSRC_GROUP_DST_UC, + IPA_RSRC_GROUP_DST_DRB_IP, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v4.9 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 0, /* no limit (hardware max) */ + .max_reads_beats = 120, + }, +}; + +/* Endpoint configuration data for an SoC having IPA v4.9 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 6, + .endpoint_id = 7, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 20, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 11, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .aggregation = true, + .status_enable = true, + .rx = { + .buffer_size = 8192, + .pad_align = ilog2(sizeof(u32)), + .aggr_time_limit = 500, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 2, + .endpoint_id = 2, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 12, + .endpoint_id = 20, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 9, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .buffer_size = 8192, + .aggr_time_limit = 500, + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 7, + .endpoint_id = 16, + .toward_ipa = false, + }, + [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 2, + .endpoint_id = 8, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, +}; + +/* Source resource configuration data for an SoC having IPA v4.9 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 1, .max = 12, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 1, .max = 12, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 20, .max = 20, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 2, .max = 2, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 38, .max = 38, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 4, .max = 4, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 0, .max = 4, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 4, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 4, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { + .min = 30, .max = 30, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 8, .max = 8, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v4.9 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 9, .max = 9, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_UC] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { + .min = 39, .max = 39, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { + .min = 2, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 1, .max = 2, + }, + .limits[IPA_RSRC_GROUP_DST_UC] = { + .min = 0, .max = 2, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v4.9 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v4.9 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0240, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_HEADER, + .offset = 0x08c8, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x0ad0, + .size = 0x0b20, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x15f0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_NAT_TABLE, + .offset = 0x1800, + .size = 0x0d00, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_MODEM, + .offset = 0x2510, + .size = 0x0030, + .canary_count = 4, + }, + { + .id = IPA_MEM_STATS_QUOTA_AP, + .offset = 0x2540, + .size = 0x0048, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_TETHERING, + .offset = 0x2588, + .size = 0x0238, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_FILTER_ROUTE, + .offset = 0x27c0, + .size = 0x0800, + .canary_count = 0, + }, + { + .id = IPA_MEM_STATS_DROP, + .offset = 0x2fc0, + .size = 0x0020, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x2fe8, + .size = 0x0800, + .canary_count = 2, + }, + { + .id = IPA_MEM_UC_EVENT_RING, + .offset = 0x3800, + .size = 0x1000, + .canary_count = 1, + }, + { + .id = IPA_MEM_PDN_CONFIG, + .offset = 0x4800, + .size = 0x0050, + .canary_count = 0, + }, +}; + +/* Memory configuration data for an SoC having IPA v4.9 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146bd000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00009000, +}; + +/* Interconnect rates are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 600000, /* 600 MBps */ + .average_bandwidth = 150000, /* 150 MBps */ + }, + /* Average rate is unused for the next interconnect */ + { + .name = "config", + .peak_bandwidth = 74000, /* 74 MBps */ + .average_bandwidth = 0, /* unused */ + }, + +}; + +/* Clock and interconnect configuration data for an SoC having IPA v4.9 */ +static const struct ipa_power_data ipa_power_data = { + .core_clock_rate = 60 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v4.9. */ +const struct ipa_data ipa_data_v4_9 = { + .version = IPA_VERSION_4_9, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .power_data = &ipa_power_data, +}; diff --git a/drivers/net/ipa/ipa_data-v3.1.c b/drivers/net/ipa/ipa_data-v3.1.c deleted file mode 100644 index 00f4e506e6e5..000000000000 --- a/drivers/net/ipa/ipa_data-v3.1.c +++ /dev/null @@ -1,537 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2021 Linaro Ltd. - */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_HDR_SECTORS, - IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v3.1 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_UL = 0, - IPA_RSRC_GROUP_SRC_DL, - IPA_RSRC_GROUP_SRC_DIAG, - IPA_RSRC_GROUP_SRC_DMA, - IPA_RSRC_GROUP_SRC_UNUSED, - IPA_RSRC_GROUP_SRC_UC_RX_Q, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_UL = 0, - IPA_RSRC_GROUP_DST_DL, - IPA_RSRC_GROUP_DST_DIAG_DPL, - IPA_RSRC_GROUP_DST_DMA, - IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL, - IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v3.1 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 8, - .max_reads = 8, - }, - [IPA_QSB_MASTER_PCIE] = { - .max_writes = 2, - .max_reads = 8, - }, -}; - -/* Endpoint data for an SoC having IPA v3.1 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 6, - .endpoint_id = 22, - .toward_ipa = true, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 18, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 7, - .endpoint_id = 15, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 8, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 5, - .endpoint_id = 3, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 16, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 8, - .endpoint_id = 16, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 8, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_DL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 8192, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_LAN_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 4, - .endpoint_id = 9, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 5, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 5, - .endpoint_id = 18, - .toward_ipa = false, - }, -}; - -/* Source resource configuration data for an SoC having IPA v3.1 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 3, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 3, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 1, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 1, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 2, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 14, .max = 14, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 16, .max = 16, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 5, .max = 5, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 5, .max = 5, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 19, .max = 19, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 26, .max = 26, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 5, .max = 5, /* 3 downstream */ - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 5, .max = 5, /* 7 downstream */ - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_UL] = { - .min = 19, .max = 19, - }, - .limits[IPA_RSRC_GROUP_SRC_DL] = { - .min = 26, .max = 26, - }, - .limits[IPA_RSRC_GROUP_SRC_DIAG] = { - .min = 5, .max = 5, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 5, .max = 5, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v3.1 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_UL] = { - .min = 3, .max = 3, /* 2 downstream */ - }, - .limits[IPA_RSRC_GROUP_DST_DL] = { - .min = 3, .max = 3, - }, - .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { - .min = 1, .max = 1, /* 0 downstream */ - }, - /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */ - .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { - .min = 3, .max = 3, - }, - .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { - .min = 3, .max = 3, - }, - }, - [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_DST_UL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_DST_DL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_DST_DMA] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { - .min = 0, .max = 255, - }, - .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { - .min = 0, .max = 255, - }, - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_UL] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_DL] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_DMA] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { - .min = 1, .max = 1, - }, - }, -}; - -/* Resource configuration data for an SoC having IPA v3.1 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v3.1 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0308, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0388, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0408, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0488, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x0508, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0588, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0608, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x0688, - .size = 0x0140, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x07d0, - .size = 0x0200, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x09d0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x0bd8, - .size = 0x1424, - .canary_count = 0, - }, - { - .id = IPA_MEM_END_MARKER, - .offset = 0x2000, - .size = 0, - .canary_count = 1, - }, -}; - -/* Memory configuration data for an SoC having IPA v3.1 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x146bd000, - .imem_size = 0x00002000, - .smem_id = 497, - .smem_size = 0x00002000, -}; - -/* Interconnect bandwidths are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 640000, /* 640 MBps */ - .average_bandwidth = 80000, /* 80 MBps */ - }, - { - .name = "imem", - .peak_bandwidth = 640000, /* 640 MBps */ - .average_bandwidth = 80000, /* 80 MBps */ - }, - /* Average bandwidth is unused for the next interconnect */ - { - .name = "config", - .peak_bandwidth = 80000, /* 80 MBps */ - .average_bandwidth = 0, /* unused */ - }, -}; - -/* Clock and interconnect configuration data for an SoC having IPA v3.1 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 16 * 1000 * 1000, /* Hz */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v3.1 */ -const struct ipa_data ipa_data_v3_1 = { - .version = IPA_VERSION_3_1, - .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; diff --git a/drivers/net/ipa/ipa_data-v3.5.1.c b/drivers/net/ipa/ipa_data-v3.5.1.c deleted file mode 100644 index b7e32e87733e..000000000000 --- a/drivers/net/ipa/ipa_data-v3.5.1.c +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2021 Linaro Ltd. - */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.5.1 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v3.5.1 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_LWA_DL = 0, - IPA_RSRC_GROUP_SRC_UL_DL, - IPA_RSRC_GROUP_SRC_MHI_DMA, - IPA_RSRC_GROUP_SRC_UC_RX_Q, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_LWA_DL = 0, - IPA_RSRC_GROUP_DST_UL_DL_DPL, - IPA_RSRC_GROUP_DST_UNUSED_2, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 8, - .max_reads = 8, - }, - [IPA_QSB_MASTER_PCIE] = { - .max_writes = 4, - .max_reads = 12, - }, -}; - -/* Endpoint datdata for an SoC having IPA v3.5.1 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 4, - .endpoint_id = 5, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 256, - .tlv_count = 20, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 5, - .endpoint_id = 9, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 8, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 3, - .endpoint_id = 2, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 16, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, - .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 6, - .endpoint_id = 10, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 8, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 8192, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_LAN_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 3, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 4, - .endpoint_id = 6, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 2, - .endpoint_id = 12, - .toward_ipa = false, - }, -}; - -/* Source resource configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { - .min = 1, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 1, .max = 255, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 1, .max = 63, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { - .min = 10, .max = 10, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 10, .max = 10, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { - .min = 12, .max = 12, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 14, .max = 14, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_MHI_DMA] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 63, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = { - .min = 14, .max = 14, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 20, .max = 20, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 14, .max = 14, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_LWA_DL] = { - .min = 4, .max = 4, - }, - .limits[1] = { - .min = 4, .max = 4, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { - .min = 3, .max = 3, - } - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_LWA_DL] = { - .min = 2, .max = 63, - }, - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 1, .max = 63, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { - .min = 1, .max = 2, - } - }, -}; - -/* Resource configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v3.5.1 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0308, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0388, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0408, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0488, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x0508, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0588, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0608, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x0688, - .size = 0x0140, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x07d0, - .size = 0x0200, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x09d0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x0bd8, - .size = 0x1024, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_EVENT_RING, - .offset = 0x1c00, - .size = 0x0400, - .canary_count = 1, - }, -}; - -/* Memory configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x146bd000, - .imem_size = 0x00002000, - .smem_id = 497, - .smem_size = 0x00002000, -}; - -/* Interconnect bandwidths are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 600000, /* 600 MBps */ - .average_bandwidth = 80000, /* 80 MBps */ - }, - /* Average bandwidth is unused for the next two interconnects */ - { - .name = "imem", - .peak_bandwidth = 350000, /* 350 MBps */ - .average_bandwidth = 0, /* unused */ - }, - { - .name = "config", - .peak_bandwidth = 40000, /* 40 MBps */ - .average_bandwidth = 0, /* unused */ - }, -}; - -/* Clock and interconnect configuration data for an SoC having IPA v3.5.1 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 75 * 1000 * 1000, /* Hz */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v3.5.1 */ -const struct ipa_data ipa_data_v3_5_1 = { - .version = IPA_VERSION_3_5_1, - .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | - BCR_TX_NOT_USING_BRESP_FMASK | - BCR_SUSPEND_L2_IRQ_FMASK | - BCR_HOLB_DROP_L2_IRQ_FMASK | - BCR_DUAL_TX_FMASK, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; diff --git a/drivers/net/ipa/ipa_data-v4.11.c b/drivers/net/ipa/ipa_data-v4.11.c deleted file mode 100644 index 1be823e5c5c2..000000000000 --- a/drivers/net/ipa/ipa_data-v4.11.c +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (C) 2021 Linaro Ltd. */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.11 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v4.11 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_UL_DL = 0, - IPA_RSRC_GROUP_SRC_UC_RX_Q, - IPA_RSRC_GROUP_SRC_UNUSED_2, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, - IPA_RSRC_GROUP_DST_UNUSED_1, - IPA_RSRC_GROUP_DST_DRB_IP, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v4.11 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 12, - .max_reads = 13, - .max_reads_beats = 120, - }, -}; - -/* Endpoint configuration data for an SoC having IPA v4.11 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 5, - .endpoint_id = 7, - .toward_ipa = true, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 20, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 14, - .endpoint_id = 9, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 2, - .endpoint_id = 2, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 16, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 7, - .endpoint_id = 16, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 32768, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 5, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 7, - .endpoint_id = 14, - .toward_ipa = false, - }, - [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 2, - .endpoint_id = 8, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, -}; - -/* Source resource configuration data for an SoC having IPA v4.11 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 6, .max = 6, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 18, .max = 18, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 2, .max = 2, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 15, .max = 15, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v4.11 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 3, .max = 3, - }, - .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { - .min = 25, .max = 25, - }, - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 2, .max = 2, - }, - }, -}; - -/* Resource configuration data for an SoC having IPA v4.11 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v4.11 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0308, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0388, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0408, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0488, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x0508, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0588, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0608, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x0688, - .size = 0x0240, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_HEADER, - .offset = 0x08c8, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x0ad0, - .size = 0x0200, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x0cd0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_NAT_TABLE, - .offset = 0x0ee0, - .size = 0x0d00, - .canary_count = 4, - }, - { - .id = IPA_MEM_PDN_CONFIG, - .offset = 0x1be8, - .size = 0x0050, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_QUOTA_MODEM, - .offset = 0x1c40, - .size = 0x0030, - .canary_count = 4, - }, - { - .id = IPA_MEM_STATS_QUOTA_AP, - .offset = 0x1c70, - .size = 0x0048, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_TETHERING, - .offset = 0x1cb8, - .size = 0x0238, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_DROP, - .offset = 0x1ef0, - .size = 0x0020, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x1f18, - .size = 0x100c, - .canary_count = 2, - }, - { - .id = IPA_MEM_END_MARKER, - .offset = 0x3000, - .size = 0x0000, - .canary_count = 1, - }, -}; - -/* Memory configuration data for an SoC having IPA v4.11 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x146a8000, - .imem_size = 0x00002000, - .smem_id = 497, - .smem_size = 0x00009000, -}; - -/* Interconnect rates are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 600000, /* 600 MBps */ - .average_bandwidth = 150000, /* 150 MBps */ - }, - /* Average rate is unused for the next interconnect */ - { - .name = "config", - .peak_bandwidth = 74000, /* 74 MBps */ - .average_bandwidth = 0, /* unused */ - }, -}; - -/* Clock and interconnect configuration data for an SoC having IPA v4.11 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 60 * 1000 * 1000, /* Hz */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v4.11 */ -const struct ipa_data ipa_data_v4_11 = { - .version = IPA_VERSION_4_11, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; diff --git a/drivers/net/ipa/ipa_data-v4.2.c b/drivers/net/ipa/ipa_data-v4.2.c deleted file mode 100644 index 683f1f91042f..000000000000 --- a/drivers/net/ipa/ipa_data-v4.2.c +++ /dev/null @@ -1,384 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (C) 2019-2021 Linaro Ltd. */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v4.2 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_UL_DL = 0, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v4.2 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 8, - .max_reads = 12, - /* no outstanding read byte (beat) limit */ - }, -}; - -/* Endpoint configuration data for an SoC having IPA v4.2 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 1, - .endpoint_id = 6, - .toward_ipa = true, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 20, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 2, - .endpoint_id = 8, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 6, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 0, - .endpoint_id = 1, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 8, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, - .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 3, - .endpoint_id = 9, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 6, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 8192, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_COMMAND_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 1, - .endpoint_id = 5, - .toward_ipa = true, - }, - [IPA_ENDPOINT_MODEM_LAN_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 3, - .endpoint_id = 11, - .toward_ipa = false, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 4, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 2, - .endpoint_id = 10, - .toward_ipa = false, - }, -}; - -/* Source resource configuration data for an SoC having IPA v4.2 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 3, .max = 63, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 3, .max = 3, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 10, .max = 10, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 1, .max = 1, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 5, .max = 5, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v4.2 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 3, .max = 3, - }, - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 1, .max = 63, - }, - }, -}; - -/* Resource configuration data for an SoC having IPA v4.2 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v4.2 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0290, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0310, - .size = 0, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0318, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0398, - .size = 0, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x03a0, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0420, - .size = 0, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0428, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x04a8, - .size = 0x0140, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x05f0, - .size = 0x0200, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x07f0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_PDN_CONFIG, - .offset = 0x09f8, - .size = 0x0050, - .canary_count = 2, - }, - { - .id = IPA_MEM_STATS_QUOTA_MODEM, - .offset = 0x0a50, - .size = 0x0060, - .canary_count = 2, - }, - { - .id = IPA_MEM_STATS_TETHERING, - .offset = 0x0ab0, - .size = 0x0140, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x0bf0, - .size = 0x140c, - .canary_count = 0, - }, - { - .id = IPA_MEM_END_MARKER, - .offset = 0x2000, - .size = 0, - .canary_count = 1, - }, -}; - -/* Memory configuration data for an SoC having IPA v4.2 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x146a8000, - .imem_size = 0x00002000, - .smem_id = 497, - .smem_size = 0x00002000, -}; - -/* Interconnect rates are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 465000, /* 465 MBps */ - .average_bandwidth = 80000, /* 80 MBps */ - }, - /* Average bandwidth is unused for the next two interconnects */ - { - .name = "imem", - .peak_bandwidth = 68570, /* 68.570 MBps */ - .average_bandwidth = 0, /* unused */ - }, - { - .name = "config", - .peak_bandwidth = 30000, /* 30 MBps */ - .average_bandwidth = 0, /* unused */ - }, -}; - -/* Clock and interconnect configuration data for an SoC having IPA v4.2 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 100 * 1000 * 1000, /* Hz */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v4.2 */ -const struct ipa_data ipa_data_v4_2 = { - .version = IPA_VERSION_4_2, - /* backward_compat value is 0 */ - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; diff --git a/drivers/net/ipa/ipa_data-v4.5.c b/drivers/net/ipa/ipa_data-v4.5.c deleted file mode 100644 index 79398f286a9c..000000000000 --- a/drivers/net/ipa/ipa_data-v4.5.c +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (C) 2021 Linaro Ltd. */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v4.5 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_UNUSED_0 = 0, - IPA_RSRC_GROUP_SRC_UL_DL, - IPA_RSRC_GROUP_SRC_UNUSED_2, - IPA_RSRC_GROUP_SRC_UNUSED_3, - IPA_RSRC_GROUP_SRC_UC_RX_Q, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_UNUSED_0 = 0, - IPA_RSRC_GROUP_DST_UL_DL_DPL, - IPA_RSRC_GROUP_DST_UNUSED_2, - IPA_RSRC_GROUP_DST_UNUSED_3, - IPA_RSRC_GROUP_DST_UC, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v4.5 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 8, - .max_reads = 0, /* no limit (hardware max) */ - .max_reads_beats = 120, - }, - [IPA_QSB_MASTER_PCIE] = { - .max_writes = 8, - .max_reads = 12, - /* no outstanding read byte (beat) limit */ - }, -}; - -/* Endpoint configuration data for an SoC having IPA v4.5 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 9, - .endpoint_id = 7, - .toward_ipa = true, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 20, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 10, - .endpoint_id = 16, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 7, - .endpoint_id = 2, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 16, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 1, - .endpoint_id = 14, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 8192, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 5, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 7, - .endpoint_id = 21, - .toward_ipa = false, - }, - [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 2, - .endpoint_id = 8, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, -}; - -/* Source resource configuration data for an SoC having IPA v4.5 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 1, .max = 11, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 1, .max = 63, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 14, .max = 14, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 3, .max = 3, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 18, .max = 18, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = { - .min = 0, .max = 63, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 63, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 24, .max = 24, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v4.5 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 16, .max = 16, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { - .min = 2, .max = 2, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { - .min = 2, .max = 2, - }, - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 2, .max = 63, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { - .min = 1, .max = 2, - }, - .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { - .min = 1, .max = 2, - }, - .limits[IPA_RSRC_GROUP_DST_UC] = { - .min = 0, .max = 2, - }, - }, -}; - -/* Resource configuration data for an SoC having IPA v4.5 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v4.5 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0308, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0388, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0408, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0488, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x0508, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0588, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0608, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x0688, - .size = 0x0240, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_HEADER, - .offset = 0x08c8, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x0ad0, - .size = 0x0b20, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x15f0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_NAT_TABLE, - .offset = 0x1800, - .size = 0x0d00, - .canary_count = 4, - }, - { - .id = IPA_MEM_STATS_QUOTA_MODEM, - .offset = 0x2510, - .size = 0x0030, - .canary_count = 4, - }, - { - .id = IPA_MEM_STATS_QUOTA_AP, - .offset = 0x2540, - .size = 0x0048, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_TETHERING, - .offset = 0x2588, - .size = 0x0238, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_FILTER_ROUTE, - .offset = 0x27c0, - .size = 0x0800, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_DROP, - .offset = 0x2fc0, - .size = 0x0020, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x2fe8, - .size = 0x0800, - .canary_count = 2, - }, - { - .id = IPA_MEM_UC_EVENT_RING, - .offset = 0x3800, - .size = 0x1000, - .canary_count = 1, - }, - { - .id = IPA_MEM_PDN_CONFIG, - .offset = 0x4800, - .size = 0x0050, - .canary_count = 0, - }, -}; - -/* Memory configuration data for an SoC having IPA v4.5 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x14688000, - .imem_size = 0x00003000, - .smem_id = 497, - .smem_size = 0x00009000, -}; - -/* Interconnect rates are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 600000, /* 600 MBps */ - .average_bandwidth = 150000, /* 150 MBps */ - }, - /* Average rate is unused for the next two interconnects */ - { - .name = "imem", - .peak_bandwidth = 450000, /* 450 MBps */ - .average_bandwidth = 75000, /* 75 MBps (unused?) */ - }, - { - .name = "config", - .peak_bandwidth = 171400, /* 171.4 MBps */ - .average_bandwidth = 0, /* unused */ - }, -}; - -/* Clock and interconnect configuration data for an SoC having IPA v4.5 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v4.5 */ -const struct ipa_data ipa_data_v4_5 = { - .version = IPA_VERSION_4_5, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; diff --git a/drivers/net/ipa/ipa_data-v4.9.c b/drivers/net/ipa/ipa_data-v4.9.c deleted file mode 100644 index 4b96efd05cf2..000000000000 --- a/drivers/net/ipa/ipa_data-v4.9.c +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Copyright (C) 2021 Linaro Ltd. */ - -#include - -#include "gsi.h" -#include "ipa_data.h" -#include "ipa_endpoint.h" -#include "ipa_mem.h" - -/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */ -enum ipa_resource_type { - /* Source resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, - IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, - IPA_RESOURCE_TYPE_SRC_HPS_DMARS, - IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, - - /* Destination resource types; first must have value 0 */ - IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, - IPA_RESOURCE_TYPE_DST_DPS_DMARS, -}; - -/* Resource groups used for an SoC having IPA v4.9 */ -enum ipa_rsrc_group_id { - /* Source resource group identifiers */ - IPA_RSRC_GROUP_SRC_UL_DL = 0, - IPA_RSRC_GROUP_SRC_DMA, - IPA_RSRC_GROUP_SRC_UC_RX_Q, - IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ - - /* Destination resource group identifiers */ - IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, - IPA_RSRC_GROUP_DST_DMA, - IPA_RSRC_GROUP_DST_UC, - IPA_RSRC_GROUP_DST_DRB_IP, - IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ -}; - -/* QSB configuration data for an SoC having IPA v4.9 */ -static const struct ipa_qsb_data ipa_qsb_data[] = { - [IPA_QSB_MASTER_DDR] = { - .max_writes = 8, - .max_reads = 0, /* no limit (hardware max) */ - .max_reads_beats = 120, - }, -}; - -/* Endpoint configuration data for an SoC having IPA v4.9 */ -static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { - [IPA_ENDPOINT_AP_COMMAND_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 6, - .endpoint_id = 7, - .toward_ipa = true, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 20, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .dma_mode = true, - .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, - .tx = { - .seq_type = IPA_SEQ_DMA, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_LAN_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 7, - .endpoint_id = 11, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .aggregation = true, - .status_enable = true, - .rx = { - .buffer_size = 8192, - .pad_align = ilog2(sizeof(u32)), - .aggr_time_limit = 500, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_TX] = { - .ee_id = GSI_EE_AP, - .channel_id = 2, - .endpoint_id = 2, - .toward_ipa = true, - .channel = { - .tre_count = 512, - .event_count = 512, - .tlv_count = 16, - }, - .endpoint = { - .filter_support = true, - .config = { - .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, - .checksum = true, - .qmap = true, - .status_enable = true, - .tx = { - .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, - .status_endpoint = - IPA_ENDPOINT_MODEM_AP_RX, - }, - }, - }, - }, - [IPA_ENDPOINT_AP_MODEM_RX] = { - .ee_id = GSI_EE_AP, - .channel_id = 12, - .endpoint_id = 20, - .toward_ipa = false, - .channel = { - .tre_count = 256, - .event_count = 256, - .tlv_count = 9, - }, - .endpoint = { - .config = { - .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, - .checksum = true, - .qmap = true, - .aggregation = true, - .rx = { - .buffer_size = 8192, - .aggr_time_limit = 500, - .aggr_close_eof = true, - }, - }, - }, - }, - [IPA_ENDPOINT_MODEM_AP_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 0, - .endpoint_id = 5, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, - [IPA_ENDPOINT_MODEM_AP_RX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 7, - .endpoint_id = 16, - .toward_ipa = false, - }, - [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { - .ee_id = GSI_EE_MODEM, - .channel_id = 2, - .endpoint_id = 8, - .toward_ipa = true, - .endpoint = { - .filter_support = true, - }, - }, -}; - -/* Source resource configuration data for an SoC having IPA v4.9 */ -static const struct ipa_resource ipa_resource_src[] = { - [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 1, .max = 12, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 1, .max = 12, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 20, .max = 20, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 2, .max = 2, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 3, .max = 3, - }, - }, - [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 38, .max = 38, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 4, .max = 4, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, - [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 0, .max = 4, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 0, .max = 4, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 0, .max = 4, - }, - }, - [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { - .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { - .min = 30, .max = 30, - }, - .limits[IPA_RSRC_GROUP_SRC_DMA] = { - .min = 8, .max = 8, - }, - .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { - .min = 8, .max = 8, - }, - }, -}; - -/* Destination resource configuration data for an SoC having IPA v4.9 */ -static const struct ipa_resource ipa_resource_dst[] = { - [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 9, .max = 9, - }, - .limits[IPA_RSRC_GROUP_DST_DMA] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_UC] = { - .min = 1, .max = 1, - }, - .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { - .min = 39, .max = 39, - }, - }, - [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { - .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { - .min = 2, .max = 3, - }, - .limits[IPA_RSRC_GROUP_DST_DMA] = { - .min = 1, .max = 2, - }, - .limits[IPA_RSRC_GROUP_DST_UC] = { - .min = 0, .max = 2, - }, - }, -}; - -/* Resource configuration data for an SoC having IPA v4.9 */ -static const struct ipa_resource_data ipa_resource_data = { - .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, - .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, - .resource_src_count = ARRAY_SIZE(ipa_resource_src), - .resource_src = ipa_resource_src, - .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), - .resource_dst = ipa_resource_dst, -}; - -/* IPA-resident memory region data for an SoC having IPA v4.9 */ -static const struct ipa_mem ipa_mem_local_data[] = { - { - .id = IPA_MEM_UC_SHARED, - .offset = 0x0000, - .size = 0x0080, - .canary_count = 0, - }, - { - .id = IPA_MEM_UC_INFO, - .offset = 0x0080, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_V4_FILTER_HASHED, - .offset = 0x0288, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_FILTER, - .offset = 0x0308, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER_HASHED, - .offset = 0x0388, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_FILTER, - .offset = 0x0408, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE_HASHED, - .offset = 0x0488, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V4_ROUTE, - .offset = 0x0508, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE_HASHED, - .offset = 0x0588, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_V6_ROUTE, - .offset = 0x0608, - .size = 0x0078, - .canary_count = 2, - }, - { - .id = IPA_MEM_MODEM_HEADER, - .offset = 0x0688, - .size = 0x0240, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_HEADER, - .offset = 0x08c8, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM_PROC_CTX, - .offset = 0x0ad0, - .size = 0x0b20, - .canary_count = 2, - }, - { - .id = IPA_MEM_AP_PROC_CTX, - .offset = 0x15f0, - .size = 0x0200, - .canary_count = 0, - }, - { - .id = IPA_MEM_NAT_TABLE, - .offset = 0x1800, - .size = 0x0d00, - .canary_count = 4, - }, - { - .id = IPA_MEM_STATS_QUOTA_MODEM, - .offset = 0x2510, - .size = 0x0030, - .canary_count = 4, - }, - { - .id = IPA_MEM_STATS_QUOTA_AP, - .offset = 0x2540, - .size = 0x0048, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_TETHERING, - .offset = 0x2588, - .size = 0x0238, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_FILTER_ROUTE, - .offset = 0x27c0, - .size = 0x0800, - .canary_count = 0, - }, - { - .id = IPA_MEM_STATS_DROP, - .offset = 0x2fc0, - .size = 0x0020, - .canary_count = 0, - }, - { - .id = IPA_MEM_MODEM, - .offset = 0x2fe8, - .size = 0x0800, - .canary_count = 2, - }, - { - .id = IPA_MEM_UC_EVENT_RING, - .offset = 0x3800, - .size = 0x1000, - .canary_count = 1, - }, - { - .id = IPA_MEM_PDN_CONFIG, - .offset = 0x4800, - .size = 0x0050, - .canary_count = 0, - }, -}; - -/* Memory configuration data for an SoC having IPA v4.9 */ -static const struct ipa_mem_data ipa_mem_data = { - .local_count = ARRAY_SIZE(ipa_mem_local_data), - .local = ipa_mem_local_data, - .imem_addr = 0x146bd000, - .imem_size = 0x00002000, - .smem_id = 497, - .smem_size = 0x00009000, -}; - -/* Interconnect rates are in 1000 byte/second units */ -static const struct ipa_interconnect_data ipa_interconnect_data[] = { - { - .name = "memory", - .peak_bandwidth = 600000, /* 600 MBps */ - .average_bandwidth = 150000, /* 150 MBps */ - }, - /* Average rate is unused for the next interconnect */ - { - .name = "config", - .peak_bandwidth = 74000, /* 74 MBps */ - .average_bandwidth = 0, /* unused */ - }, - -}; - -/* Clock and interconnect configuration data for an SoC having IPA v4.9 */ -static const struct ipa_power_data ipa_power_data = { - .core_clock_rate = 60 * 1000 * 1000, /* Hz */ - .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), - .interconnect_data = ipa_interconnect_data, -}; - -/* Configuration data for an SoC having IPA v4.9. */ -const struct ipa_data ipa_data_v4_9 = { - .version = IPA_VERSION_4_9, - .qsb_count = ARRAY_SIZE(ipa_qsb_data), - .qsb_data = ipa_qsb_data, - .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), - .endpoint_data = ipa_gsi_endpoint_data, - .resource_data = &ipa_resource_data, - .mem_data = &ipa_mem_data, - .power_data = &ipa_power_data, -}; -- cgit v1.2.3