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2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula
2024-05-03drm/xe/bmg: Enable the display supportBalasubramani Vivekanandan
2024-05-03drm/i915/display: perform transient flushMatthew Auld
2024-05-03drm/xe/device: implement transient flushNirmoy Das
2024-05-03drm/xe/gt_print: add xe_gt_err_once()Matthew Auld
2024-05-03drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5Balasubramani Vivekanandan
2024-05-03Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"Ankit Nautiyal
2024-05-03drm/i915/bmg: BMG should re-use MTL's south display logicMatt Roper
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza
2024-05-03drm/i915/xe2hpd: Add max memory bandwidth algorithmMatt Roper
2024-05-03drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planesAnusha Srivatsa
2024-05-03drm/i915/xe2hpd: Add display infoLucas De Marchi
2024-05-03drm/i915/xe2hpd: update pll values in sync with BspecRavi Kumar Vodapalli
2024-05-03drm/i915/xe2hpd: Add support for eDP PLL configurationBalasubramani Vivekanandan
2024-05-03drm/i915/xe2hpd: Add new C20 PHY SRAM addressBalasubramani Vivekanandan
2024-05-03drm/i915/xe2hpd: Properly disable power in port AJosé Roberto de Souza
2024-05-03drm/i915/bmg: Extend DG2 tc check to futureRadhakrishna Sripada
2024-05-03drm/i915/xe2hpd: Initial cdclk tableClint Taylor
2024-05-03drm/i915/bmg: Define IS_BATTLEMAGE macroBalasubramani Vivekanandan
2024-05-03drm/i915/bmg: Lane reversal requires writes to both context lanesClint Taylor
2024-05-03Merge drm/drm-next into drm-intel-nextRodrigo Vivi
2024-05-03drm/i915/display: Calculate crtc clock rate based on PLL parametersMika Kahola
2024-05-03drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/Ville Syrjälä
2024-05-03drm/i915: Eliminate extra frame from skl-glk sync->async flip changeVille Syrjälä
2024-05-03drm/i915: Allow the initial async flip to change modifierVille Syrjälä
2024-05-03drm/i915: Reject async flips if we need to change DDB/watermarksVille Syrjälä
2024-05-03drm/i915: Align PLANE_SURF to 16k on ADL for async flipsVille Syrjälä
2024-05-03Merge tag 'drm-xe-next-fixes-2024-05-02' of https://gitlab.freedesktop.org/dr...Dave Airlie
2024-05-02drm/i915/audio: Fix audio time stamp programming for DPChaitanya Kumar Borah
2024-05-02drm/xe: Merge 16021540221 and 18034896535 WAsLucas De Marchi
2024-05-02drm/xe/vm: prevent UAF in rebind_work_func()Matthew Auld
2024-05-02drm/xe: Fix unexpected backmerge resultsThomas Hellström
2024-05-02Merge tag 'drm-intel-next-2024-04-30' of https://anongit.freedesktop.org/git/...Dave Airlie
2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hVille Syrjälä
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä
2024-04-30drm/i915/dpio: Clean up VLV/CHV DPIO PHY register definesVille Syrjälä
2024-04-30drm/i915/dpio: Rename a few CHV DPIO PHY registersVille Syrjälä
2024-04-30drm/i915/dpio: Give VLV DPIO group register a clearer nameVille Syrjälä
2024-04-30drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooksVille Syrjälä
2024-04-30drm/i915/dpio: s/pipe/ch/Ville Syrjälä
2024-04-30drm/i915/dpio: s/port/ch/Ville Syrjälä
2024-04-30drm/i915/dpio: Rename some variablesVille Syrjälä
2024-04-30drm/i915/dpio: Remove pointless variables from vlv/chv DPLL codeVille Syrjälä
2024-04-30drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä