Age | Commit message (Collapse) | Author |
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i.MX is a DT-only platform, so of_match_ptr() can be safely
removed.
Remove the unneeded of_match_ptr().
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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Current driver actually does not support simple ondemand governor
as it's unable to provide device load information. So removing
the unnecessary callback to avoid confusing.
Right now the driver is using userspace governor by default.
polling_ms was also dropped as it's not needed for non-ondemand
governor.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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Fix inconsistent IS_ERR and PTR_ERR in imx8m_ddrc_probe().
Detected using Coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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The IMX_SIP_DDR_DVFS_WAIT_CHANGE and IMX_SIP_DDR_FREQ_SET_HIGH defines
are not used so they can be removed.
Fixes: 518e99e2a22e ("PM / devfreq: Add dynamic scaling for imx8m ddr controller")
Reported-by: Shawn Guo <shawn.guo@kernel.org>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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Add driver for dynamic scaling the DDR Controller on imx8m chips. Actual
frequency switching is implemented inside TF-A, this driver wraps the
SMC calls and synchronizes the clk tree.
The DRAM clocks on imx8m have the following structure (abridged):
+----------+ |\ +------+
| dram_pll |-------|M| dram_core | |
+----------+ |U|---------->| D |
/--|X| | D |
dram_alt_root | |/ | R |
| | C |
+---------+ | |
|FIX DIV/4| | |
+---------+ | |
composite: | | |
+----------+ | | |
| dram_alt |----/ | |
+----------+ | |
| dram_apb |-------------------->| |
+----------+ +------+
The dram_pll is used for higher rates and dram_alt is used for lower
rates. The dram_alt and dram_apb clocks are "imx composite" and their
parent can also be modified.
This driver will prepare/enable the new parents ahead of switching (so
that the expected roots are enabled) and afterwards it will call
clk_set_parent to ensure the parents in clock framework are up-to-date.
The driver relies on dram_pll dram_alt and dram_apb being marked with
CLK_GET_RATE_NOCACHE for rate updates.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
[cw00.choi: Edit the COMPILE_TEST module dependency in Kconfig]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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