Linux kernel documentation tree maintained by Jonathan Corbet http://mirrors.hust.edu.cn/git/lwn.git/atom?h=master 2026-04-09T10:56:37+00:00 2026-04-09T10:56:37+00:00 Song Gao gaosong@loongson.cn 2026-04-09T10:56:37+00:00 urn:sha1:11c840192768a5a63b6aed75273c5e8e416230ee Introduce a basic PMU test that verifies hardware event counting for four performance counters. The test enables the events for CPU cycles, instructions retired, branch instructions, and branch misses, runs a fixed number of loops, and checks that the counter values fall within expected ranges. It also validates that the host supports PMU and that the VM feature is enabled. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2026-04-09T10:56:37+00:00 Song Gao gaosong@loongson.cn 2026-04-09T10:56:37+00:00 urn:sha1:fa19ea9a7bdb97575e05d72305a4c40a3a631357 Add helper macros and functions to read and write CPU configuration registers (cpucfg) from the guest and from the VMM. This interface is required in upcoming selftests for querying and setting CPU features, such as PMU capabilities. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2026-01-08T20:02:08+00:00 Sean Christopherson seanjc@google.com 2025-12-30T23:01:35+00:00 urn:sha1:9f073ac25b4c4cf3b3ea13b155035108c54148bb Add a "struct kvm_mmu" to track a given MMU instance, e.g. a VM's stage-1 MMU versus a VM's stage-2 MMU, so that x86 can share MMU functionality for both stage-1 and stage-2 MMUs, without creating the potential for subtle bugs, e.g. due to consuming on vm->pgtable_levels when operating a stage-2 MMU. Encapsulate the existing de facto MMU in "struct kvm_vm", e.g instead of burying the MMU details in "struct kvm_vm_arch", to avoid more #ifdefs in ____vm_create(), and in the hopes that other architectures can utilize the formalized MMU structure if/when they too support stage-2 page tables. No functional change intended. Reviewed-by: Yosry Ahmed <yosry.ahmed@linux.dev> Link: https://patch.msgid.link/20251230230150.4150236-7-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com> 2025-11-28T06:49:48+00:00 Bibo Mao maobibo@loongson.cn 2025-11-28T06:49:48+00:00 urn:sha1:0f90fa6e2e9d98349492d9968c11ceaf2f958c98 With time counter test, it is to verify that time count starts from 0 and always grows up then. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-11-28T06:49:44+00:00 Bibo Mao maobibo@loongson.cn 2025-11-28T06:49:44+00:00 urn:sha1:df41742343fad11fde06e085096003d64599785f Add timer test case based on common arch_timer code, timer interrupt with one-shot and period mode is tested. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-11-27T03:00:18+00:00 Bibo Mao maobibo@loongson.cn 2025-11-27T03:00:18+00:00 urn:sha1:d84fe2f30b0a0cbe08260c00a84ffe42161c95ce Add interrupt and exception handler register interface. When exception happens, execute registered exception handler if exists, else report an error. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-11-27T03:00:18+00:00 Bibo Mao maobibo@loongson.cn 2025-11-27T03:00:18+00:00 urn:sha1:1c5d3a1eab32db1ebb0d5d30736e9236e8a7014f Add some basic function interfaces such as CSR register access, local irq enable or disable APIs. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-05-20T12:20:26+00:00 Bibo Mao maobibo@loongson.cn 2025-05-20T12:20:26+00:00 urn:sha1:2ebf31d59f583449422f4b2dad59b0130e750117 Add core KVM selftests support for LoongArch, it includes exception handler, mmu page table setup and vCPU startup entry support. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>