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<title>lwn.git/include/linux/mlx5, branch doc/sphinx</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
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<updated>2016-02-16T20:21:47+00:00</updated>
<entry>
<title>net/mlx5: Use offset based reserved field names in the IFC header file</title>
<updated>2016-02-16T20:21:47+00:00</updated>
<author>
<name>Matan Barak</name>
<email>matanb@mellanox.com</email>
</author>
<published>2016-02-09T12:57:42+00:00</published>
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<id>urn:sha1:b4ff3a36d3e409d365a09b6b783ff895063ff4ef</id>
<content type='text'>
mlx5_ifc.h is a header file representing the API and ABI between
the driver to the firmware and hardware. This file is used from
both the mlx5_ib and mlx5_core drivers.

Previously, this file used incrementing counter to indicate
reserved fields, for example:

struct mlx5_ifc_odp_per_transport_service_cap_bits {
        u8         send[0x1];
        u8         receive[0x1];
        u8         write[0x1];
        u8         read[0x1];
        u8         reserved_0[0x1];
        u8         srq_receive[0x1];
        u8         reserved_1[0x1a];
};

If one developer implements through net-next feature A that uses
reserved_0, they replace it with featureA and renames reserved_1 to
reserved_0. In the same kernel cycle, a 2nd developer could implement
feature B through the rdma tree, that uses reserved_1 and split it to
featureB and a smaller reserved_1 field. This will cause a conflict
when the two trees are merged.

The source of this conflict is that the 1st developer changed *all*
reserved fields.

As Linus suggested, we change the layout of structs to:

struct mlx5_ifc_odp_per_transport_service_cap_bits {
	u8         send[0x1];
	u8         receive[0x1];
	u8         write[0x1];
	u8         read[0x1];
	u8         reserved_at_4[0x1];
	u8         srq_receive[0x1];
	u8         reserved_at_6[0x1a];
};

This makes the conflicts much more rare and preserves the locality of
changes.

Signed-off-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Alaa Hleihel &lt;alaa@mellanox.com&gt;
Reported-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma</title>
<updated>2016-01-24T02:45:06+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-01-24T02:45:06+00:00</published>
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<id>urn:sha1:048ccca8c1c8f583deec3367d7df521bb1f542ae</id>
<content type='text'>
Pull rdma updates from Doug Ledford:
 "Initial roundup of 4.5 merge window patches

   - Remove usage of ib_query_device and instead store attributes in
     ib_device struct

   - Move iopoll out of block and into lib, rename to irqpoll, and use
     in several places in the rdma stack as our new completion queue
     polling library mechanism.  Update the other block drivers that
     already used iopoll to use the new mechanism too.

   - Replace the per-entry GID table locks with a single GID table lock

   - IPoIB multicast cleanup

   - Cleanups to the IB MR facility

   - Add support for 64bit extended IB counters

   - Fix for netlink oops while parsing RDMA nl messages

   - RoCEv2 support for the core IB code

   - mlx4 RoCEv2 support

   - mlx5 RoCEv2 support

   - Cross Channel support for mlx5

   - Timestamp support for mlx5

   - Atomic support for mlx5

   - Raw QP support for mlx5

   - MAINTAINERS update for mlx4/mlx5

   - Misc ocrdma, qib, nes, usNIC, cxgb3, cxgb4, mlx4, mlx5 updates

   - Add support for remote invalidate to the iSER driver (pushed
     through the RDMA tree due to dependencies, acknowledged by nab)

   - Update to NFSoRDMA (pushed through the RDMA tree due to
     dependencies, acknowledged by Bruce)"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (169 commits)
  IB/mlx5: Unify CQ create flags check
  IB/mlx5: Expose Raw Packet QP to user space consumers
  {IB, net}/mlx5: Move the modify QP operation table to mlx5_ib
  IB/mlx5: Support setting Ethernet priority for Raw Packet QPs
  IB/mlx5: Add Raw Packet QP query functionality
  IB/mlx5: Add create and destroy functionality for Raw Packet QP
  IB/mlx5: Refactor mlx5_ib_qp to accommodate other QP types
  IB/mlx5: Allocate a Transport Domain for each ucontext
  net/mlx5_core: Warn on unsupported events of QP/RQ/SQ
  net/mlx5_core: Add RQ and SQ event handling
  net/mlx5_core: Export transport objects
  IB/mlx5: Expose CQE version to user-space
  IB/mlx5: Add CQE version 1 support to user QPs and SRQs
  IB/mlx5: Fix data validation in mlx5_ib_alloc_ucontext
  IB/sa: Fix netlink local service GFP crash
  IB/srpt: Remove redundant wc array
  IB/qib: Improve ipoib UD performance
  IB/mlx4: Advertise RoCE v2 support
  IB/mlx4: Create and use another QP1 for RoCEv2
  IB/mlx4: Enable send of RoCE QP1 packets with IP/UDP headers
  ...
</content>
</entry>
<entry>
<title>{IB, net}/mlx5: Move the modify QP operation table to mlx5_ib</title>
<updated>2016-01-21T17:01:09+00:00</updated>
<author>
<name>majd@mellanox.com</name>
<email>majd@mellanox.com</email>
</author>
<published>2016-01-14T17:13:07+00:00</published>
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<id>urn:sha1:427c1e7bcd7e5cd62160fcda0ce215ebbe0da3a1</id>
<content type='text'>
When modifying a QP, the desired operation was determined in
the mlx5_core using a transition table that takes the current
state, the final state, and returns the desired operation.

Since this logic will be used for Raw Packet QP, move the
operation table to the mlx5_ib.

Signed-off-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Reviewed-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Support setting Ethernet priority for Raw Packet QPs</title>
<updated>2016-01-21T17:01:09+00:00</updated>
<author>
<name>majd@mellanox.com</name>
<email>majd@mellanox.com</email>
</author>
<published>2016-01-14T17:13:06+00:00</published>
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<id>urn:sha1:75850d0bcece42416ba81bd38e4c719f101c832d</id>
<content type='text'>
When the user changes the Address Vector(AV) in the modify QP, he
provides an SL. This SL should be translated to Ethernet Priority
by taking the 3 LSB bits, and modify the QP's TIS according to this
Ethernet priority.

Signed-off-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Reviewed-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Add Raw Packet QP query functionality</title>
<updated>2016-01-21T17:01:09+00:00</updated>
<author>
<name>majd@mellanox.com</name>
<email>majd@mellanox.com</email>
</author>
<published>2016-01-14T17:13:05+00:00</published>
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<id>urn:sha1:6d2f89df04b796e7dcc4f9f8dc0d8f04ad7f144b</id>
<content type='text'>
Since Raw Packet QP is composed of RQ and SQ, the IB QP's
state is derived from the sub-objects. Therefore we need
to query each one of the sub-objects, and decide on the
IB QP's state.

Signed-off-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Reviewed-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5_core: Add RQ and SQ event handling</title>
<updated>2016-01-21T17:01:09+00:00</updated>
<author>
<name>majd@mellanox.com</name>
<email>majd@mellanox.com</email>
</author>
<published>2016-01-14T17:13:00+00:00</published>
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<id>urn:sha1:e2013b212f9f201c71fc5826ce41f39ebece0852</id>
<content type='text'>
RQ/SQ will be used to implement IB verbs QPs, so the IB QP affiliated
events are affiliated also with SQs and RQs.

Since SQ, RQ and QP resource numbers do not share the same name
space, a queue type field was added to the event data to specify
the SW object that the event is affiliated with.

Signed-off-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Reviewed-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5_core: Export transport objects</title>
<updated>2016-01-21T17:01:08+00:00</updated>
<author>
<name>majd@mellanox.com</name>
<email>majd@mellanox.com</email>
</author>
<published>2016-01-14T17:12:59+00:00</published>
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<id>urn:sha1:8d7f9ecb371a15e48754fa816e3f716517df7b13</id>
<content type='text'>
To be used by mlx5_ib in the following patches for implementing
RAW PACKET QP.

Add mlx5_core_ prefix to alloc and delloc transport_domain since
they are exposed now.

Signed-off-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Reviewed-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5_core: Fix trimming down IRQ number</title>
<updated>2016-01-17T17:08:04+00:00</updated>
<author>
<name>Doron Tsur</name>
<email>doront@mellanox.com</email>
</author>
<published>2016-01-17T09:25:47+00:00</published>
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<id>urn:sha1:0b6e26ce89391327d955a756a7823272238eb867</id>
<content type='text'>
With several ConnectX-4 cards installed on a server, one may receive
irqn &gt; 255 from the kernel API, which we mistakenly trim to 8bit.

This causes EQ creation failure with the following stack trace:
[&lt;ffffffff812a11f4&gt;] dump_stack+0x48/0x64
[&lt;ffffffff810ace21&gt;] __setup_irq+0x3a1/0x4f0
[&lt;ffffffff810ad7e0&gt;] request_threaded_irq+0x120/0x180
[&lt;ffffffffa0923660&gt;] ? mlx5_eq_int+0x450/0x450 [mlx5_core]
[&lt;ffffffffa0922f64&gt;] mlx5_create_map_eq+0x1e4/0x2b0 [mlx5_core]
[&lt;ffffffffa091de01&gt;] alloc_comp_eqs+0xb1/0x180 [mlx5_core]
[&lt;ffffffffa091ea99&gt;] mlx5_dev_init+0x5e9/0x6e0 [mlx5_core]
[&lt;ffffffffa091ec29&gt;] init_one+0x99/0x1c0 [mlx5_core]
[&lt;ffffffff812e2afc&gt;] local_pci_probe+0x4c/0xa0

Fixing it by changing of the irqn type from u8 to unsigned int to
support values &gt; 255

Fixes: 61d0e73e0a5a ('net/mlx5_core: Use the the real irqn in eq-&gt;irqn')
Reported-by: Jiri Pirko &lt;jiri@mellanox.com&gt;
Signed-off-by: Doron Tsur &lt;doront@mellanox.com&gt;
Signed-off-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Add flow steering support</title>
<updated>2016-01-11T22:48:53+00:00</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2016-01-11T08:26:07+00:00</published>
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<id>urn:sha1:038d2ef87572757861a177b19f9d489def2c48b8</id>
<content type='text'>
Adding flow steering support by creating a flow-table per
priority (if rules exist in the priority). mlx5_ib uses
autogrouping and thus only creates the required destinations.

Also includes adding of these flow steering utilities

1. Parsing verbs flow attributes hardware steering specs.

2. Check if flow is multicast - this is required in order to decide
to which flow table will we add the steering rule.

3. Set outer headers in flow match criteria to zeros.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Signed-off-by: Moni Shoua &lt;monis@mellanox.com&gt;
Signed-off-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5_core: Make ipv4/ipv6 location more clear</title>
<updated>2016-01-11T22:48:53+00:00</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2016-01-11T08:26:05+00:00</published>
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<id>urn:sha1:b4d1f032d75b2efb73304e8c12faa7149ad700c7</id>
<content type='text'>
Change the mlx5 firmware interface header to make it
more clear which bytes should be used by IPv4 or
IPv6 addresses.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Signed-off-by: Moni Shoua &lt;monis@mellanox.com&gt;
Signed-off-by: Matan Barak &lt;matanb@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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