lwn.git/include/asm-xtensa/ide.h, branch v3.10.18Linux kernel documentation tree maintained by Jonathan Corbethttp://mirrors.hust.edu.cn/git/lwn.git/atom?h=v3.10.182008-07-24T20:53:31+00:00ide: remove <asm/ide.h> for some archs2008-07-24T20:53:31+00:00Bartlomiej Zolnierkiewiczbzolnier@gmail.com2008-07-24T20:53:31+00:00urn:sha1:2a8f7450f828eaee49d66f41f99ac2e54f1160a6
* Remove <linux/irq.h> include from <asm-ia64.h> (<linux/ide.h> includes
<linux/interrupt.h> which is enough).
* Remove <asm/ide.h> for alpha/blackfin/h8300/ia64/m32r/sh/x86/xtensa
(this leaves us with arm/frv/m68k/mips/mn10300/parisc/powerpc/sparc[64]).
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
ide: define MAX_HWIFS in <linux/ide.h>2008-07-24T20:53:30+00:00Bartlomiej Zolnierkiewiczbzolnier@gmail.com2008-07-24T20:53:30+00:00urn:sha1:d83b8b85cd56a083d30df73f3fd5e4714591b910
* Now that ide_hwif_t instances are allocated dynamically
the difference between MAX_HWIFS == 2 and MAX_HWIFS == 10
is ~100 bytes (x86-32) so use MAX_HWIFS == 10 on all archs
except these ones that use MAX_HWIFS == 1.
* Define MAX_HWIFS in <linux/ide.h> instead of <asm/ide.h>.
[ Please note that avr32/cris/v850 have no <asm/ide.h>
and alpha/ia64/sh always define CONFIG_IDE_MAX_HWIFS. ]
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
ide: fix <asm-xtensa/ide.h>2008-07-24T20:53:27+00:00Bartlomiej Zolnierkiewiczbzolnier@gmail.com2008-07-24T20:53:27+00:00urn:sha1:b0a62817961796f6dcef5f316134d8bc7279bf6e
* Add missing <asm-generic/ide_iops.h> include.
While at it:
* Remove needless ide_default_{irq,io_base}() inlines.
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Don't include linux/config.h from anywhere else in include/2006-04-26T11:56:16+00:00David Woodhousedwmw2@infradead.org2006-04-26T11:56:16+00:00urn:sha1:62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 62005-06-24T07:05:22+00:00Chris Zankelczankel@tensilica.com2005-06-24T05:01:26+00:00urn:sha1:9a8fd5589902153a134111ed7a40f9cca1f83254
The attached patches provides part 6 of an architecture implementation for the
Tensilica Xtensa CPU series.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>