<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/include/asm-sh/hw_irq.h, branch v3.10.63</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v3.10.63</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v3.10.63'/>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/'/>
<updated>2008-07-28T23:09:44+00:00</updated>
<entry>
<title>sh: migrate to arch/sh/include/</title>
<updated>2008-07-28T23:09:44+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-07-28T23:09:44+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=f15cbe6f1a4b4d9df59142fc8e4abb973302cf44'/>
<id>urn:sha1:f15cbe6f1a4b4d9df59142fc8e4abb973302cf44</id>
<content type='text'>
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&amp;m=121724823706062&amp;w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: add interrupt ack code to sh4a</title>
<updated>2008-07-28T09:10:33+00:00</updated>
<author>
<name>Yoshihiro Shimoda</name>
<email>shimoda.yoshihiro@renesas.com</email>
</author>
<published>2008-07-04T03:37:12+00:00</published>
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<id>urn:sha1:6bdfb22a8e1ffa37ae4ad35b87cb02958d1901e5</id>
<content type='text'>
This patch is based on interrupt acknowledge code for external
interrupt sources on sh3 processors and adds on sh4a processors.

Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: add interrupt ack code to sh3</title>
<updated>2008-05-08T10:52:03+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>magnus.damm@gmail.com</email>
</author>
<published>2008-04-24T12:36:34+00:00</published>
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<id>urn:sha1:d58876e289b0153bf86162aa1a43249e0f0aa03d</id>
<content type='text'>
This patch adds interrupt acknowledge code for external interrupt
sources on sh3 processors. Only really required for edge triggered
interrupts, but we ack regardless of sense configuration.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: unify external irq pin code for sh3</title>
<updated>2008-05-08T10:52:00+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>magnus.damm@gmail.com</email>
</author>
<published>2008-04-24T12:30:09+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=a276e588a92737889c21e736f2bbed8aecda25fb'/>
<id>urn:sha1:a276e588a92737889c21e736f2bbed8aecda25fb</id>
<content type='text'>
This patch unifies the sh3 external irq pin code. It buys us some
savings with reduced code redundancy, but the main feature with
this change is irq sense selection support for all sh3 processors.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - remove default interrupt priority tables</title>
<updated>2008-01-28T04:19:02+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2008-01-10T05:08:55+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=7f3edee81fbd49114c28057512906f169caa0bed'/>
<id>urn:sha1:7f3edee81fbd49114c28057512906f169caa0bed</id>
<content type='text'>
This patch removes interrupt priority tables from the intc code.
Optimal priority assignment varies with embedded application anyway,
so keeping the interrupt priority tables together with cpu-specific
code doesn't make sense.

The function intc_set_priority() should be used instead to set the
desired interrupt priority level.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - initial SMP support.</title>
<updated>2007-09-21T09:16:42+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2007-09-21T09:16:42+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=f18d533e3cd476aedf41fe1e6e9dc3e0a2446bba'/>
<id>urn:sha1:f18d533e3cd476aedf41fe1e6e9dc3e0a2446bba</id>
<content type='text'>
This implements initial support for the SMP INTC (particularly
INTC2) controllers.

These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - irl mode update for sh7780 and sh7785</title>
<updated>2007-09-21T02:57:51+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2007-09-10T03:03:50+00:00</published>
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<id>urn:sha1:953c8ef250fc6c329d1607cf9cd7fac1d72d7579</id>
<content type='text'>
This patch contains the following fixes and improvements:
- Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780.
- Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking.
- Good old IRQ_MODE_IRLnnnn should not register any intc controller.
- plat_irq_setup_pins() now selects IRL or IRQ mode.
- the holding function is now disabled using ICR0.

By default all external pin interrupts are disabled.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - primary priority masking fixes</title>
<updated>2007-09-21T02:57:50+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2007-08-16T15:50:44+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=3d37d94e5aab669f5a492bb3cda67bbbbbca50b8'/>
<id>urn:sha1:3d37d94e5aab669f5a492bb3cda67bbbbbca50b8</id>
<content type='text'>
This patch contains various intc fixes for problems reported by
Markus Brunner on the linuxsh-dev mailing list:

http://marc.info/?l=linuxsh-dev&amp;m=118701948224991&amp;w=1

Apart from added comments, the fixes are:

- add intc_set_priority() function prototype to hw_irq.h
- fix off-by-one error in intc_set_priority()
- make sure _INTC_WIDTH() is set for primary priority masking

Big thanks to Markus for finding these problems. Version two fixes
a compile error and an inverted primary check.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Acked-by: Markus Brunner &lt;super.firetwister@gmail.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - mark data structures as __initdata</title>
<updated>2007-09-21T02:57:50+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2007-08-16T15:45:35+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=5c37e025352b993d8726b0207ff2270b2f2bc7d6'/>
<id>urn:sha1:5c37e025352b993d8726b0207ff2270b2f2bc7d6</id>
<content type='text'>
With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: intc - rework core code</title>
<updated>2007-09-21T02:57:50+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2007-08-12T06:26:12+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=73505b445dbb8ad12df468404c4dd5cde9c40c65'/>
<id>urn:sha1:73505b445dbb8ad12df468404c4dd5cde9c40c65</id>
<content type='text'>
This patch reworks the intc core, implementing the following features:

- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be
  __initdata
- Save memory - allocated memory footprint is smaller than intc
  structures

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
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