<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/include/asm-powerpc/pci-bridge.h, branch v6.8-rc5</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v6.8-rc5</id>
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<updated>2008-08-04T02:02:00+00:00</updated>
<entry>
<title>powerpc: Move include files to arch/powerpc/include/asm</title>
<updated>2008-08-04T02:02:00+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2008-08-01T05:20:30+00:00</published>
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<id>urn:sha1:b8b572e1015f81b4e748417be2629dfe51ab99f9</id>
<content type='text'>
from include/asm-powerpc.  This is the result of a

mkdir arch/powerpc/include/asm
git mv include/asm-powerpc/* arch/powerpc/include/asm

Followed by a few documentation/comment fixups and a couple of places
where &lt;asm-powepc/...&gt; was being used explicitly.  Of the latter only
one was outside the arch code and it is a driver only built for powerpc.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata</title>
<updated>2008-06-17T23:01:38+00:00</updated>
<author>
<name>Josh Boyer</name>
<email>jwboyer@linux.vnet.ibm.com</email>
</author>
<published>2008-06-17T23:01:38+00:00</published>
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<id>urn:sha1:5ce4b59653b2c2053cd9a011918ac1e4747f24cc</id>
<content type='text'>
The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
by looking for a zero value in the PCI cache line size register.  However,
some drivers write to this register upon initialization.  This can cause
MRMs to be used on these chips, which may cause deadlocks on PLB4.

The workaround implemented here introduces a new indirect_type flag, called
PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
the pci fixup function for 4xx PCI bridges by determining if the bridge is
compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
zero, which will disable MRMs for these chips.

A similar workaround has been tested by AMCC on various PCI cards, such as
the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
With the workaround in place, the card functioned properly and only Memory
Reads were seen on the bus with the analyzer.

Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Make pci_bus_to_host()'s struct pci_bus * argument const</title>
<updated>2008-04-18T05:37:14+00:00</updated>
<author>
<name>Trent Piepho</name>
<email>tpiepho@freescale.com</email>
</author>
<published>2008-04-09T02:19:32+00:00</published>
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<id>urn:sha1:f13f4ca8036516ca1b99a41f95f7dea7e4dce104</id>
<content type='text'>
A) It's not modified and so it can be made const.  const is good.
B) If one has a function that was given a const pci_bus pointer and you
want to get a pointer to its pci_controller, you'll get a warning from gcc
when you use pci_bus_to_host().  This is the right way to stop that
warning.

Signed-off-by: Trent Piepho &lt;tpiepho@freescale.com&gt;
Acked-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Remove update_bridge_resource</title>
<updated>2008-01-24T01:32:30+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-01-15T02:42:53+00:00</published>
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<id>urn:sha1:82f0183ef3c8832684ec460cfbd4693cc8732a7a</id>
<content type='text'>
The 85xx/86xx pci code no longer uses update_bridge_resource and it was the
only caller.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] iSeries: eliminate pci_dn bussubno</title>
<updated>2008-01-17T03:57:05+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2007-12-21T04:50:09+00:00</published>
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<id>urn:sha1:885b86e4e7ccc360f8ce4d7fb10dfdfb6e3c8650</id>
<content type='text'>
xlate_iomm_address() really wants the ds_addr to pass to the HV, so store
that value (instead of the BAR number) when we allocate the device bars.
This is not a fast path, so we can look up the device_node property
there instead of using the bussubno field of the pci_dn.

The other user of iseries_ds_addr() was already scanning the device tree,
so looking up a property will not slow it down any more.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] The pci_dn pcidev is only used by EEH</title>
<updated>2008-01-17T03:57:01+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2007-12-21T04:49:11+00:00</published>
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<id>urn:sha1:b6ed42a794e1ca51fb46ff2bdc562315c46dd9a8</id>
<content type='text'>
Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] The pci_dn class_code is only used by EEH</title>
<updated>2008-01-17T03:57:00+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2007-12-21T04:48:18+00:00</published>
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<id>urn:sha1:86bcab492cfdbaad144bdfb453b4e9db6117a7a5</id>
<content type='text'>
... so move it into the #ifdef CONFIG_EEH section.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Pointers marked as __iomem do not need to be volatile</title>
<updated>2007-12-21T11:14:07+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2007-12-21T04:23:48+00:00</published>
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<id>urn:sha1:70fbb9388365c3f6f9f17e6501a67f8636e4af08</id>
<content type='text'>
Fixes this warning:

arch/powerpc/platforms/powermac/pci.c: In function 'u3_ht_cfg_access':
arch/powerpc/platforms/powermac/pci.c:354: warning: return discards qualifiers from pointer target type
arch/powerpc/platforms/powermac/pci.c:358: warning: return discards qualifiers from pointer target type

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] Merge PCI resource fixups</title>
<updated>2007-12-20T05:18:09+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2007-12-20T03:54:51+00:00</published>
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<id>urn:sha1:bf5e2ba28f24f82a64524ef4772c9ebe12e2cd2a</id>
<content type='text'>
The PCI code in 32 and 64 bits fixes up resources differently.

32 bits uses a header quirk plus handles bridges in pcibios_fixup_bus()
while 64 bits does things in various places depending on whether you
are using OF probing, using PCI hotplug, etc...

This merges those by basically using the 32 bits approach for both,
with various tweaks to make 64 bits work with the new approach.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
<entry>
<title>[POWERPC] pci32: Add platform option to enable /proc PCI domains</title>
<updated>2007-12-20T05:18:08+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2007-12-20T03:54:49+00:00</published>
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<id>urn:sha1:fa462f2d75e2437b5757069d3d7d27b1e50285cb</id>
<content type='text'>
This adds flags the platforms can use to enable domain numbers
in /proc/bus/pci.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
</entry>
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