<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/include/asm-mips, branch v2.6.21-rc2</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
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<updated>2007-02-26T23:06:06+00:00</updated>
<entry>
<title>[MIPS] Remove unreferenced _IOC_SLMASK macro in ioctl.h.</title>
<updated>2007-02-26T23:06:06+00:00</updated>
<author>
<name>Robert P. J. Day</name>
<email>rpjday@mindspring.com</email>
</author>
<published>2007-02-24T11:17:09+00:00</published>
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<id>urn:sha1:40139bd459d3fe90ee560f46a2cb00f16b873170</id>
<content type='text'>
Delete the definition of the apparently unreferenced macro _IOC_SLMASK.

Signed-off-by: Robert P. J. Day &lt;rpjday@mindspring.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] SNI: MIPS_CPU_IRQ_BASE cleanup</title>
<updated>2007-02-26T23:06:06+00:00</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2007-02-23T20:39:38+00:00</published>
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<id>urn:sha1:f13cc01d8d3630ba42680ac56b3bedfce812e531</id>
<content type='text'>
Use MIPS_CPU_IRQ_BASE instead of own define.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Add basic SMARTMIPS ASE support</title>
<updated>2007-02-22T00:50:44+00:00</updated>
<author>
<name>Franck Bui-Huu</name>
<email>fbuihuu@gmail.com</email>
</author>
<published>2007-02-02T16:41:47+00:00</published>
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<id>urn:sha1:9693a85378b590cc7a4aa2db2174422585c7c8c4</id>
<content type='text'>
This patch adds trivial support for SMARTMIPS extension. This extension
is currently implemented by 4KS[CD] CPUs.

Basically it saves/restores ACX register, which is part of the SMARTMIPS
ASE, when needed. This patch does *not* add any support for Smartmips MMU
features.

Futhermore this patch does not add explicit support for 4KS[CD] CPUs since
they are respectively mips32 and mips32r2 compliant.  So with the current
processor configuration, a platform that has such CPUs needs to select
both configs:

	CPU_HAS_SMARTMIPS
	SYS_HAS_CPU_MIPS32_R[12]

This is due to the processor configuration which is mixing up all the
architecture variants and the processor types.

The drawback of this, is that we currently pass '-march=mips32' option to
gcc when building a kernel instead of '-march=4ksc' for 4KSC case. This
can lead to a kernel image a little bit bigger than required.

Signed-off-by: Franck Bui-Huu &lt;fbuihuu@gmail.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Fixup copy_from_user_inatomic</title>
<updated>2007-02-20T01:26:42+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-02-19T16:59:24+00:00</published>
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<id>urn:sha1:e03b526932a9ae1ff20b47459c040f3c6407f625</id>
<content type='text'>
From the 01408c4939479ec46c15aa7ef6e2406be50eeeca log message:

The problem is that when we write to a file, the copy from userspace to
pagecache is first done with preemption disabled, so if the source
address is not immediately available the copy fails *and* *zeros* *the*
*destination*.

This is a problem because a concurrent read (which admittedly is an odd
thing to do) might see zeros rather that was there before the write, or
what was there after, or some mixture of the two (any of these being a
reasonable thing to see).

If the copy did fail, it will immediately be retried with preemption
re-enabled so any transient problem with accessing the source won't
cause an error.

The first copying does not need to zero any uncopied bytes, and doing
so causes the problem.  It uses copy_from_user_atomic rather than
copy_from_user so the simple expedient is to change copy_from_user_atomic
to *not* zero out bytes on failure.

&lt; --- end cite --- &gt;

This patch finally implements at least a not so pretty solution by
duplicating the relevant part of __copy_user.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Fix struct sigcontext for N32 userland</title>
<updated>2007-02-20T01:26:42+00:00</updated>
<author>
<name>Atsushi Nemoto</name>
<email>anemo@mba.ocn.ne.jp</email>
</author>
<published>2007-02-17T15:12:57+00:00</published>
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<id>urn:sha1:269dd2b2526d046d8b43554ff27b486e2ddb3f08</id>
<content type='text'>
The kernel use 64-bit for sc_regs[0], and both N32/N64 userland
expects it was 64-bit.  But size of 'long' on N32 is actually 32-bit.
So this definition make some confusion.  Use __u32 and __u64 for
N32/N64 sigcontext to get rid of this confusion.

Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Support for several more SNI RM models.</title>
<updated>2007-02-18T21:31:37+00:00</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2006-12-28T17:22:32+00:00</published>
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<id>urn:sha1:c066a32a890c50ce59e91f8cea8eb5fd8d5821b9</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Add external declaration of pagetable_init() to pgalloc.h</title>
<updated>2007-02-18T21:31:36+00:00</updated>
<author>
<name>Atsushi Nemoto</name>
<email>anemo@mba.ocn.ne.jp</email>
</author>
<published>2007-02-18T16:27:34+00:00</published>
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<id>urn:sha1:6a1e552947b0d73310e534bf4eb09e14db1e5056</id>
<content type='text'>
This fixes some sparse warnings.

pgtable-32.c:15:6: warning: symbol 'pgd_init' was not declared. Should it be static?
pgtable-32.c:32:13: warning: symbol 'pagetable_init' was not declared. Should it be static?

Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Use MIPS R2 instructions for bitops.</title>
<updated>2007-02-18T21:31:35+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-02-16T17:18:50+00:00</published>
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<id>urn:sha1:102fa15c3f14565f2edb9f08f08ea3f2bf123dc9</id>
<content type='text'>
Add R2 optimized variants of clear_bit, set_bit and test_and_clear_bit.
With gcc 4.1.1 this saves 1592 bytes on a defconfig (minus IPv6) kernel.
Turns out that R2 bitop instructions are no gain for the other bitop
functions.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] signals: Share even more code.</title>
<updated>2007-02-18T21:31:35+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-02-15T11:40:37+00:00</published>
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<id>urn:sha1:151fd6acd94e12ef3a7d5fa0911a2590690c493f</id>
<content type='text'>
native and compat do_signal and handle_signal are identical and can easily
be unified.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Iomap implementation.</title>
<updated>2007-02-18T21:31:34+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-12-07T14:35:43+00:00</published>
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<id>urn:sha1:140c1729a221dc6eacfcbf2a073dbf00fad13e43</id>
<content type='text'>
This implementation has support for the concept of one separate ioport
address space by PCI domain.  A pointer to the virtual address where
the port space of a domain has been mapped has been added to struct
pci_controller and systems should be fixed to fill in this value. For
single domain systems this will be the same value as passed to
set_io_port_base().

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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