<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/include/asm-mips/cpu-info.h, branch v2.6.27.4</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v2.6.27.4</id>
<link rel='self' href='http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v2.6.27.4'/>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/'/>
<updated>2008-06-16T14:14:48+00:00</updated>
<entry>
<title>[MIPS] vpe_id is required for VSMP and SMTC builds</title>
<updated>2008-06-16T14:14:48+00:00</updated>
<author>
<name>Chris Dearman</name>
<email>chris@mips.com</email>
</author>
<published>2008-05-17T00:29:54+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=d6c3048cad3c9eb312c070e11fdbea56498255ed'/>
<id>urn:sha1:d6c3048cad3c9eb312c070e11fdbea56498255ed</id>
<content type='text'>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] MT: Scheduler support for SMT</title>
<updated>2008-01-29T10:14:57+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-03-02T20:42:04+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b'/>
<id>urn:sha1:0ab7aefc4d43a6dee26c891b41ef9c7a67d2379b</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Fix shadow register support.</title>
<updated>2007-11-15T23:21:49+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-11-08T18:02:29+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8'/>
<id>urn:sha1:f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8</id>
<content type='text'>
Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Make facility to convert CPU types to strings generally available.</title>
<updated>2007-10-11T22:46:17+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-10-11T22:46:17+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=9966db25defba4e1dce263246db25237bc24479f'/>
<id>urn:sha1:9966db25defba4e1dce263246db25237bc24479f</id>
<content type='text'>
So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Remove IP27 specific structures from struct cpuinfo_mips</title>
<updated>2007-10-11T22:46:05+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-10-11T22:46:05+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=cc6e8e0812cf95aea397c457ff48de2ac069614f'/>
<id>urn:sha1:cc6e8e0812cf95aea397c457ff48de2ac069614f</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] FPU ownership management &amp; preemption fixes</title>
<updated>2007-03-17T01:03:26+00:00</updated>
<author>
<name>Atsushi Nemoto</name>
<email>anemo@mba.ocn.ne.jp</email>
</author>
<published>2007-03-09T16:07:45+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=53dc80287da43b75df2fe2658651d3c5160dad8e'/>
<id>urn:sha1:53dc80287da43b75df2fe2658651d3c5160dad8e</id>
<content type='text'>
Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Fix alignment hole in struct cache_desc; shrink struct.</title>
<updated>2006-11-30T01:14:45+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-11-30T01:14:45+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=6f2c3fa022312d5381f44359984395761e375f1b'/>
<id>urn:sha1:6f2c3fa022312d5381f44359984395761e375f1b</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>Don't include linux/config.h from anywhere else in include/</title>
<updated>2006-04-26T11:56:16+00:00</updated>
<author>
<name>David Woodhouse</name>
<email>dwmw2@infradead.org</email>
</author>
<published>2006-04-26T11:56:16+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f'/>
<id>urn:sha1:62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] MT: Improved multithreading support.</title>
<updated>2006-04-19T02:14:28+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2006-04-05T08:45:45+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=41c594ab65fc89573af296d192aa5235d09717ab'/>
<id>urn:sha1:41c594ab65fc89573af296d192aa5235d09717ab</id>
<content type='text'>
    
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] local_r4k_flush_cache_page fix</title>
<updated>2006-03-18T16:59:27+00:00</updated>
<author>
<name>Atsushi Nemoto</name>
<email>anemo@mba.ocn.ne.jp</email>
</author>
<published>2006-03-13T09:23:03+00:00</published>
<link rel='alternate' type='text/html' href='http://mirrors.hust.edu.cn/git/lwn.git/commit/?id=de62893bc0725f8b5f0445250577cd7a10b2d8f8'/>
<id>urn:sha1:de62893bc0725f8b5f0445250577cd7a10b2d8f8</id>
<content type='text'>
    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
