<feed xmlns='http://www.w3.org/2005/Atom'>
<title>lwn.git/drivers/pwm/pwm-tegra.c, branch v6.0-rc6</title>
<subtitle>Linux kernel documentation tree maintained by Jonathan Corbet</subtitle>
<id>http://mirrors.hust.edu.cn/git/lwn.git/atom?h=v6.0-rc6</id>
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<updated>2022-05-20T14:28:49+00:00</updated>
<entry>
<title>pwm: tegra: Implement .apply() callback</title>
<updated>2022-05-20T14:28:49+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2022-05-06T16:48:06+00:00</published>
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<id>urn:sha1:fd3ddd4355c0e5388b40d48321e2e834393a4912</id>
<content type='text'>
To eventually get rid of all legacy drivers convert this driver to the
modern world implementing .apply().
This just pushed a variant of pwm_apply_legacy() into the driver that was
slightly simplified because the driver doesn't provide a .set_polarity()
callback.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Optimize period calculation</title>
<updated>2022-05-20T14:20:07+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2022-04-25T13:22:44+00:00</published>
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<id>urn:sha1:8c193f4714df136a6747fb66f4218134771092be</id>
<content type='text'>
Dividing by the result of a division looses precision because the result is
rounded twice. E.g. with clk_rate = 48000000 and period = 32760033 the
following numbers result:

	rate = pc-&gt;clk_rate &gt;&gt; PWM_DUTY_WIDTH = 187500
	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns) = 3052
	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz) = 6144

The exact result would be 6142.5061875 and (apart from rounding) this is
found by using a single division. As a side effect is also a tad
cheaper to calculate.

Also using clk_rate &gt;&gt; PWM_DUTY_WIDTH looses precision. Consider for
example clk_rate = 47999999 and period = 106667:

	mul_u64_u64_div_u64(pc-&gt;clk_rate &gt;&gt; PWM_DUTY_WIDTH, period_ns,
			    NSEC_PER_SEC) = 19

	mul_u64_u64_div_u64(pc-&gt;clk_rate, period_ns,
			    NSEC_PER_SEC &lt;&lt; PWM_DUTY_WIDTH) = 20

(The exact result is 20.000062083332033.)

With this optimizations also switch from round-closest to round-down for
the period calculation. Given that the calculations were non-optimal for
quite some time now with variations in both directions which nobody
reported as a problem, this is the opportunity to align the driver's
behavior to the requirements of new drivers. This has several upsides:

 - Implementation is easier as there are no round-nearest variants of
   mul_u64_u64_div_u64().
 - Requests for too small periods are now consistently refused. This was
   kind of arbitrary before, where period_ns &lt; min_period_ns was
   refused, but in some cases min_period_ns isn't actually implementable
   and then values between min_period_ns and the actual minimum were
   rounded up to the actual minimum.

Note that the duty_cycle calculation isn't using the usual round-down
approach yet.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Rename variable pointing to driver private data</title>
<updated>2022-02-02T17:03:04+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-11-23T09:29:36+00:00</published>
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<id>urn:sha1:f19460c1d5cc7df74fcfa539132abe53fb31b42e</id>
<content type='text'>
Status quo is that variables of type struct tegra_pwm_chip * are named
"pwm", "chip" or "pc". The two formers are all not optimal because
usually only struct pwm_device * variables are named "pwm" and "chip" is
usually used for variabled of type struct pwm_chip *.

So consistently use the same and non-conflicting name "pc".

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Add runtime PM and OPP support</title>
<updated>2021-12-16T13:05:23+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:28+00:00</published>
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<id>urn:sha1:3da9b0feaa1617061eddfd0eedcc24164c71528a</id>
<content type='text'>
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance state in accordance to the rate. Add runtime PM and OPP
support to the PWM driver.

Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Assert reset only after the PWM was unregistered</title>
<updated>2021-06-30T17:12:20+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-06-17T09:51:43+00:00</published>
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<id>urn:sha1:2f1a3bd4510afd8cf5ab5a6169ad64981a62dccf</id>
<content type='text'>
The driver is supposed to stay functional until pwmchip_remove()
returns. So the reset must be asserted only after that.

pwmchip_remove() always returns 0, so the return code can be ignored
which keeps the tegra_pwm_remove() a bit simpler.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Don't needlessly enable and disable the clock in .remove()</title>
<updated>2021-06-30T17:12:20+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-06-17T09:51:42+00:00</published>
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<id>urn:sha1:3b8b571fcc49e794703eb01a97e9ed8b85e88304</id>
<content type='text'>
There is no reason to enable the PWM clock just to assert the reset
control. (If the reset control depends on the clock this is a bug and
probably it doesn't because in .probe() the reset is deasserted without
the clock being enabled.)

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Don't modify HW state in .remove callback</title>
<updated>2021-06-30T17:12:20+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-06-17T09:51:41+00:00</published>
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<id>urn:sha1:86f7fa71cd830d18d7ebcaf719dffd5ddfe1acdd</id>
<content type='text'>
A consumer is expected to disable a PWM before calling pwm_put(). And if
they didn't there is hopefully a good reason (or the consumer needs
fixing). Also if disabling an enabled PWM was the right thing to do,
this should better be done in the framework instead of in each low level
driver.

So drop the hardware modification from the .remove() callback.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Drop an if block with an always false condition</title>
<updated>2021-06-30T17:12:20+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-06-17T09:51:40+00:00</published>
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<id>urn:sha1:c1b8ac969febc8f413c4d71f0eefe2e107610449</id>
<content type='text'>
tegra_pwm_remove() is only called after tegra_pwm_probe() successfully
completed. In this case platform_set_drvdata() was called with a
non-NULL value and so platform_get_drvdata(pdev) cannot return NULL.

Returning an error code from a platform_driver's remove function is
ignored anyway, so it's a good thing this exit path is gone.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: Always allocate PWM chip base ID dynamically</title>
<updated>2021-03-22T10:53:00+00:00</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@pengutronix.de</email>
</author>
<published>2021-03-01T18:57:19+00:00</published>
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<id>urn:sha1:f9a8ee8c8bcd118e800d88772c6457381db45224</id>
<content type='text'>
Since commit 5e5da1e9fbee ("pwm: ab8500: Explicitly allocate pwm chip
base dynamically") all drivers use dynamic ID allocation explicitly. New
drivers are supposed to do the same, so remove support for driver
specified base IDs and drop all assignments in the low-level drivers.

Signed-off-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>pwm: tegra: Convert to devm_platform_ioremap_resource()</title>
<updated>2020-12-17T13:18:39+00:00</updated>
<author>
<name>Yangtao Li</name>
<email>tiny.windzz@gmail.com</email>
</author>
<published>2019-12-29T08:05:44+00:00</published>
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<id>urn:sha1:fa44fe41cc75523b835bf6f625ee1cbf3d0c566b</id>
<content type='text'>
Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li &lt;tiny.windzz@gmail.com&gt;
Reviewed-by: Uwe Kleine-König &lt;u.kleine-koenig@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
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