lwn.git/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c, branch docs-fixes

pinctrl: aspeed: Cleanup header includes

2026-01-19T00:11:46+00:00

Remove unused includes (no mutexes, string functions, no OF functions) and bring directly used mod_devicetable.h (previously pulled via of.h). Reviewed-by: Andrew Jeffery Signed-off-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Add PCIe RC PERST pin group

2025-07-23T11:22:41+00:00

The PCIe RC PERST uses SSPRST# as PERST# and enable this pin to output. Signed-off-by: Jacky Chou Acked-by: Linus Walleij Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed: Constify static 'pinctrl_desc'

2025-06-18T11:26:36+00:00

The local static 'struct pinctrl_desc' is not modified, so can be made const for code safety. Reviewed-by: Andrew Jeffery Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-5-b11c1d650384@linaro.org Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Support drive-strength for GPIOF/G

2024-10-28T12:58:43+00:00

Add drive strength configuration support for GPIO F and G groups. Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/20241023104406.4083460-1-billy_tsai@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Add NCSI pin group config

2024-06-26T10:41:07+00:00

Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO, reducing the number of required pins. LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf Signed-off-by: Potin Lai Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij

pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T

2024-03-28T09:15:15+00:00

The register offset to disable the internal pull-down of GPIOR~T is 0x630 instead of 0x620, as specified in the Ast2600 datasheet v15 The datasheet can download from the official Aspeed website. Fixes: 15711ba6ff19 ("pinctrl: aspeed-g6: Add AST2600 pinconf support") Reported-by: Delphine CC Chiu Signed-off-by: Billy Tsai Reviewed-by: Paul Menzel Reviewed-by: Andrew Jeffery Message-ID: <20240313092809.2596644-1-billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij

pinctrl: pinctrl-aspeed-g6: Add more settings for USB2AHP function

2023-09-25T12:32:39+00:00

AST2600 USB2AHP (USB PortA: PCIe EHCI to PHY) function needs to set the register SCUC20[16]. Set it to enable the PCIe EHCI device on PCIe bus. Besides, also add USB2AHP signal expressions into pin declarations. Signed-off-by: Joe Wang Link: https://lore.kernel.org/r/20230920103332.274151-1-joe_wang@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group

2022-04-13T02:23:52+00:00

Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by: Johnny Huang Signed-off-by: Jae Hyun Yoo Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20220329173932.2588289-5-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley

pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl

2022-04-13T02:23:52+00:00

FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Jae Hyun Yoo Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20220329173932.2588289-3-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley

Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2021-07-01T23:57:14+00:00

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.14 kernel. Not so much going on. No core changes, just drivers. The most interesting would be that MIPS Ralink is migrating to pin control and we have some bindings but not yet code for the Apple M1 pin controller. New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well" * tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits) pinctrl: ralink: rt305x: add missing include pinctrl: stm32: check for IRQ MUX validity during alloc() pinctrl: zynqmp: some code cleanups drivers: qcom: pinctrl: Add pinctrl driver for sm6125 dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios pinctrl: mcp23s08: Add optional reset GPIO pinctrl: mediatek: fix mode encoding pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() pinctrl: bcm: Constify static pinmux_ops pinctrl: bcm: Constify static pinctrl_ops pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file pinctrl: ralink: move ralink architecture pinmux header into the driver pinctrl: single: config: enable the pin's input pinctrl: mtk: Fix mt8365 Kconfig dependency pinctrl: mcp23s08: fix race condition in irq handler ...